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llvm-project/llvm/test/CodeGen/ARM/long_shift.ll

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[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
ARM big endian function argument passing llvm-svn: 208316
2014-05-08 22:06:24 +08:00
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
Changes to support making the shift instructions be true BinaryOperators. This feature is needed in order to support shifts of more than 255 bits on large integer types. This changes the syntax for llvm assembly to make shl, ashr and lshr instructions look like a binary operator: shl i32 %X, 1 instead of shl i32 %X, i8 1 Additionally, this should help a few passes perform additional optimizations. llvm-svn: 33776
2007-02-02 10:16:23 +08:00
define i64 @f0(i64 %A, i64 %B) {
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-LABEL: f0:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: lsrs r3, r3, #1
; CHECK-LE-NEXT: rrx r2, r2
; CHECK-LE-NEXT: subs r0, r0, r2
; CHECK-LE-NEXT: sbc r1, r1, r3
; CHECK-LE-NEXT: mov pc, lr
;
; CHECK-BE-LABEL: f0:
; CHECK-BE: @ %bb.0:
; CHECK-BE-NEXT: lsrs r2, r2, #1
; CHECK-BE-NEXT: rrx r3, r3
; CHECK-BE-NEXT: subs r1, r1, r3
; CHECK-BE-NEXT: sbc r0, r0, r2
; CHECK-BE-NEXT: mov pc, lr
%tmp = bitcast i64 %A to i64
%tmp2 = lshr i64 %B, 1
%tmp3 = sub i64 %tmp, %tmp2
ret i64 %tmp3
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
}
Changes to support making the shift instructions be true BinaryOperators. This feature is needed in order to support shifts of more than 255 bits on large integer types. This changes the syntax for llvm assembly to make shl, ashr and lshr instructions look like a binary operator: shl i32 %X, 1 instead of shl i32 %X, i8 1 Additionally, this should help a few passes perform additional optimizations. llvm-svn: 33776
2007-02-02 10:16:23 +08:00
define i32 @f1(i64 %x, i64 %y) {
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-LABEL: f1:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: lsl r0, r0, r2
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-LE-NEXT: subs r1, r2, #32
; CHECK-LE-NEXT: movpl r0, #0
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-NEXT: mov pc, lr
;
; CHECK-BE-LABEL: f1:
; CHECK-BE: @ %bb.0:
; CHECK-BE-NEXT: lsl r0, r1, r3
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-BE-NEXT: subs r1, r3, #32
; CHECK-BE-NEXT: movpl r0, #0
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-BE-NEXT: mov pc, lr
%a = shl i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
Merge tests. llvm-svn: 33560
2007-01-27 08:04:57 +08:00
}
Changes to support making the shift instructions be true BinaryOperators. This feature is needed in order to support shifts of more than 255 bits on large integer types. This changes the syntax for llvm assembly to make shl, ashr and lshr instructions look like a binary operator: shl i32 %X, 1 instead of shl i32 %X, i8 1 Additionally, this should help a few passes perform additional optimizations. llvm-svn: 33776
2007-02-02 10:16:23 +08:00
define i32 @f2(i64 %x, i64 %y) {
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-LABEL: f2:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: rsb r3, r2, #32
; CHECK-LE-NEXT: lsr r0, r0, r2
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-LE-NEXT: subs r2, r2, #32
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-LE-NEXT: asrpl r0, r1, r2
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-NEXT: mov pc, lr
;
; CHECK-BE-LABEL: f2:
; CHECK-BE: @ %bb.0:
; CHECK-BE-NEXT: rsb r2, r3, #32
; CHECK-BE-NEXT: lsr r1, r1, r3
; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-BE-NEXT: subs r2, r3, #32
; CHECK-BE-NEXT: asrpl r1, r0, r2
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-BE-NEXT: mov r0, r1
; CHECK-BE-NEXT: mov pc, lr
ARM big endian function argument passing llvm-svn: 208316
2014-05-08 22:06:24 +08:00
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
%a = ashr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
Merge tests. llvm-svn: 33560
2007-01-27 08:04:57 +08:00
}
Changes to support making the shift instructions be true BinaryOperators. This feature is needed in order to support shifts of more than 255 bits on large integer types. This changes the syntax for llvm assembly to make shl, ashr and lshr instructions look like a binary operator: shl i32 %X, 1 instead of shl i32 %X, i8 1 Additionally, this should help a few passes perform additional optimizations. llvm-svn: 33776
2007-02-02 10:16:23 +08:00
define i32 @f3(i64 %x, i64 %y) {
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-LABEL: f3:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: rsb r3, r2, #32
; CHECK-LE-NEXT: lsr r0, r0, r2
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-LE-NEXT: subs r2, r2, #32
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-LE-NEXT: lsrpl r0, r1, r2
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-LE-NEXT: mov pc, lr
;
; CHECK-BE-LABEL: f3:
; CHECK-BE: @ %bb.0:
; CHECK-BE-NEXT: rsb r2, r3, #32
; CHECK-BE-NEXT: lsr r1, r1, r3
; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
[ARM] Favour PL/MI over GE/LT when possible The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
2019-07-04 16:58:58 +08:00
; CHECK-BE-NEXT: subs r2, r3, #32
; CHECK-BE-NEXT: lsrpl r1, r0, r2
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
; CHECK-BE-NEXT: mov r0, r1
; CHECK-BE-NEXT: mov pc, lr
ARM big endian function argument passing llvm-svn: 208316
2014-05-08 22:06:24 +08:00
[ARM] Added testing for D64160. NFC Adds some extra vsel testing and regenerates long shift and saturation bitop tests. llvm-svn: 365116
2019-07-04 16:49:32 +08:00
%a = lshr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
Merge tests. llvm-svn: 33560
2007-01-27 08:04:57 +08:00
}