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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir

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AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
AMDGPU/GlobalISel: Fix tests without asserts The legality check is only done under NDEBUG, so the failure cases are different in a release build. llvm-svn: 366680
2019-07-22 20:43:41 +08:00
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
# FIXME: Ideally this would fail to select with ieee mode enabled.
---
name: fminnum_f32_f64_ieee_mode_on
legalized: true
regBankSelected: true
machineFunctionInfo:
mode:
ieee: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13
; minnum vs
%4:vgpr(s32) = G_FMINNUM %1, %0
; minnum sv
%5:vgpr(s32) = G_FMINNUM %0, %1
; minnum vv
%6:vgpr(s32) = G_FMINNUM %1, %2
G_STORE %4, %3 :: (store 4, addrspace 1)
G_STORE %5, %3 :: (store 4, addrspace 1)
G_STORE %6, %3 :: (store 4, addrspace 1)
; 64-bit
; minnum vs
%14:vgpr(s64) = G_FMINNUM %10, %11
; minnum sv
%15:vgpr(s64) = G_FMINNUM %11, %10
; minnum vv
%16:vgpr(s64) = G_FMINNUM %11, %12
S_ENDPGM 0, implicit %14, implicit %15, implicit %16
...
---
name: fminnum_f32_f64_ieee_mode_off
legalized: true
regBankSelected: true
machineFunctionInfo:
mode:
ieee: false
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13
; minnum vs
%4:vgpr(s32) = G_FMINNUM %1, %0
; minnum sv
%5:vgpr(s32) = G_FMINNUM %0, %1
; minnum vv
%6:vgpr(s32) = G_FMINNUM %1, %2
G_STORE %4, %3 :: (store 4, addrspace 1)
G_STORE %5, %3 :: (store 4, addrspace 1)
G_STORE %6, %3 :: (store 4, addrspace 1)
; 64-bit
; minnum vs
%14:vgpr(s64) = G_FMINNUM %10, %11
; minnum sv
%15:vgpr(s64) = G_FMINNUM %11, %10
; minnum vv
%16:vgpr(s64) = G_FMINNUM %11, %12
S_ENDPGM 0, implicit %14, implicit %15, implicit %16
...