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llvm-project/llvm/test/CodeGen/PTX/aggregates.ll

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PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; RUN: llc < %s -march=ptx32 -mattr=sm20 | FileCheck %s
PTX: fixup test cases for register changes llvm-svn: 140311
2011-09-23 00:45:51 +08:00
; XFAIL: *
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
%complex = type { float, float }
define ptx_device %complex @complex_add(%complex %a, %complex %b) {
entry:
; CHECK: ld.param.f32 r[[R0:[0-9]+]], [__param_1];
; CHECK-NEXT: ld.param.f32 r[[R2:[0-9]+]], [__param_3];
; CHECK-NEXT: ld.param.f32 r[[R1:[0-9]+]], [__param_2];
; CHECK-NEXT: ld.param.f32 r[[R3:[0-9]+]], [__param_4];
; CHECK-NEXT: add.rn.f32 r[[R0]], r[[R0]], r[[R2]];
; CHECK-NEXT: add.rn.f32 r[[R1]], r[[R1]], r[[R3]];
; CHECK-NEXT: ret;
%a.real = extractvalue %complex %a, 0
%a.imag = extractvalue %complex %a, 1
%b.real = extractvalue %complex %b, 0
%b.imag = extractvalue %complex %b, 1
%ret.real = fadd float %a.real, %b.real
%ret.imag = fadd float %a.imag, %b.imag
%ret.0 = insertvalue %complex undef, float %ret.real, 0
%ret.1 = insertvalue %complex %ret.0, float %ret.imag, 1
ret %complex %ret.1
}