maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-no...

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

388 lines
16 KiB
LLVM
Raw Normal View History

[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations -verify-machineinstrs < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
define amdgpu_kernel void @private_nontemporal_load_0(
; GFX6-LABEL: private_nontemporal_load_0:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX6-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX6-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX6-NEXT: s_add_u32 s8, s8, s7
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_addc_u32 s9, s9, 0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_mov_b32 s3, 0x100f000
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s6
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_nontemporal_load_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc slc
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_nontemporal_load_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_nontemporal_load_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_nontemporal_load_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[8:9]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s8, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s8, s8, s3
; SKIP-CACHE-INV-NEXT: s_addc_u32 s9, s9, 0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s4
; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry:
%val = load i32, i32 addrspace(5)* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @private_nontemporal_load_1(
; GFX6-LABEL: private_nontemporal_load_1:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX6-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX6-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX6-NEXT: s_add_u32 s8, s8, s7
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX6-NEXT: s_addc_u32 s9, s9, 0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s6, v0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_mov_b32 s3, 0x100f000
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_nontemporal_load_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc slc
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_nontemporal_load_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_nontemporal_load_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_nontemporal_load_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[8:9]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s8, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s8, s8, s3
; SKIP-CACHE-INV-NEXT: s_addc_u32 s9, s9, 0
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s4, v0
; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
%val = load i32, i32 addrspace(5)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @private_nontemporal_store_0(
; GFX6-LABEL: private_nontemporal_store_0:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX6-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX6-NEXT: s_add_u32 s8, s8, s7
; GFX6-NEXT: s_addc_u32 s9, s9, 0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX6-NEXT: v_mov_b32_e32 v1, s2
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen glc slc
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_nontemporal_store_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen glc slc
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_nontemporal_store_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen slc
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_nontemporal_store_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen slc
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_nontemporal_store_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[4:5]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s4, s4, s3
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_addc_u32 s5, s5, 0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen glc slc
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry:
%val = load i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(5)* %out, !nontemporal !0
ret void
}
define amdgpu_kernel void @private_nontemporal_store_1(
; GFX6-LABEL: private_nontemporal_store_1:
; GFX6: ; %bb.0: ; %entry
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX6-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX6-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX6-NEXT: s_add_u32 s8, s8, s7
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_addc_u32 s9, s9, 0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v0
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
[AMDGPU] Use MUBUF instructions for global address space access Currently, the compiler crashes in instruction selection of global load/stores in gfx600 due to the lack of FLAT instructions. This patch fix the crash by selecting MUBUF instructions for global load/stores in gfx600. Authored-by: Praveen Velliengiri <Praveen.Velliengiri@amd.com> Reviewed by: t-tye Differential revision: https://reviews.llvm.org/D92483
2020-12-24 17:44:01 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen glc slc
[AMDGPU] Extend and reorganize memory legalizer tests * Rename some tests to try to make a convention (where all components are optional) of: <addrspace>_<syncscope>_<memory-orders>_<operation> * Split up at a level of granularity appropriate for the different RUN lines (i.e. split on addrspace so GFX6 can avoid FLAT) and that makes running a specific test reasonable in terms of wall time taken. This also means when run as part of the test suite the testing is not one serial bottleneck. * Auto-generate check lines with `update_llc_test_checks.py` to make future maintenance more tractable. Reviewed By: rampitec, t-tye Differential Revision: https://reviews.llvm.org/D91545
2020-12-01 00:59:09 +08:00
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_nontemporal_store_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen glc slc
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_nontemporal_store_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen slc
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_nontemporal_store_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen slc
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_nontemporal_store_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[4:5]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s4, s4, s3
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_addc_u32 s5, s5, 0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen glc slc
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
store i32 %val, i32 addrspace(5)* %out.gep, !nontemporal !0
ret void
}
!0 = !{i32 1}
declare i32 @llvm.amdgcn.workitem.id.x()