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llvm-project/llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir

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[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. Differential Revision: https://reviews.llvm.org/D46154 llvm-svn: 331062
2018-04-28 01:59:15 +08:00
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s
AMDGPU: Insert wait at start of callee functions llvm-svn: 300000
2017-04-12 06:29:31 +08:00
--- |
define float @entry_callee_wait(float %arg) #0 {
ret float %arg
}
attributes #0 = { nounwind }
...
---
# CHECK-LABEL: name: entry_callee_wait{{$}}
# CHECK: bb.0:
# CHECK-NEXT: S_WAITCNT 0{{$}}
# CHECK-NEXT: V_ADD_F32
# CHECK-NEXT: S_SETPC_B64
liveins:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
- { reg: '$sgpr0_sgpr1' }
- { reg: '$vgpr0' }
AMDGPU: Insert wait at start of callee functions llvm-svn: 300000
2017-04-12 06:29:31 +08:00
name: entry_callee_wait
body: |
bb.0:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
$vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
S_SETPC_B64 killed $sgpr0_sgpr1
AMDGPU: Insert wait at start of callee functions llvm-svn: 300000
2017-04-12 06:29:31 +08:00
...