maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/nontemporal-3.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

1345 lines
42 KiB
LLVM
Raw Normal View History

[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefixes=SSE,SSE4A
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512DQ
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512BW
; Test codegen for under aligned nontemporal vector stores
; XMM versions.
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v2f64_align1(<2 x double>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v2f64_align1:
; SSE: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; SSE-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v2f64_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v2f64_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <2 x double> zeroinitializer, <2 x double>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v4f32_align1(<4 x float>* %dst) nounwind {
[X86] Make getZeroVector return floating point vectors in their native type on SSE2 and later. isel used to require zero vectors to be canonicalized to a single type to minimize the number of patterns needed to match. This is no longer required. I plan to do this to integers too, but floating point was simpler to start with. Integer has a complication where v32i16/v64i8 aren't legal when the other 512-bit integer types are. llvm-svn: 371325
2019-09-08 08:43:52 +08:00
; SSE-LABEL: test_zero_v4f32_align1:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 8(%rdi)
; SSE-NEXT: movntiq %rax, (%rdi)
; SSE-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v4f32_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v4f32_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <4 x float> zeroinitializer, <4 x float>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v2i64_align1(<2 x i64>* %dst) nounwind {
[X86] Make getZeroVector return floating point vectors in their native type on SSE2 and later. isel used to require zero vectors to be canonicalized to a single type to minimize the number of patterns needed to match. This is no longer required. I plan to do this to integers too, but floating point was simpler to start with. Integer has a complication where v32i16/v64i8 aren't legal when the other 512-bit integer types are. llvm-svn: 371325
2019-09-08 08:43:52 +08:00
; SSE-LABEL: test_zero_v2i64_align1:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 8(%rdi)
; SSE-NEXT: movntiq %rax, (%rdi)
; SSE-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v2i64_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v2i64_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <2 x i64> zeroinitializer, <2 x i64>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v4i32_align1(<4 x i32>* %dst) nounwind {
[X86] Make getZeroVector return floating point vectors in their native type on SSE2 and later. isel used to require zero vectors to be canonicalized to a single type to minimize the number of patterns needed to match. This is no longer required. I plan to do this to integers too, but floating point was simpler to start with. Integer has a complication where v32i16/v64i8 aren't legal when the other 512-bit integer types are. llvm-svn: 371325
2019-09-08 08:43:52 +08:00
; SSE-LABEL: test_zero_v4i32_align1:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 8(%rdi)
; SSE-NEXT: movntiq %rax, (%rdi)
; SSE-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v4i32_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v4i32_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <4 x i32> zeroinitializer, <4 x i32>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8i16_align1(<8 x i16>* %dst) nounwind {
[X86] Make getZeroVector return floating point vectors in their native type on SSE2 and later. isel used to require zero vectors to be canonicalized to a single type to minimize the number of patterns needed to match. This is no longer required. I plan to do this to integers too, but floating point was simpler to start with. Integer has a complication where v32i16/v64i8 aren't legal when the other 512-bit integer types are. llvm-svn: 371325
2019-09-08 08:43:52 +08:00
; SSE-LABEL: test_zero_v8i16_align1:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 8(%rdi)
; SSE-NEXT: movntiq %rax, (%rdi)
; SSE-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v8i16_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8i16_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x i16> zeroinitializer, <8 x i16>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16i8_align1(<16 x i8>* %dst) nounwind {
[X86] Make getZeroVector return floating point vectors in their native type on SSE2 and later. isel used to require zero vectors to be canonicalized to a single type to minimize the number of patterns needed to match. This is no longer required. I plan to do this to integers too, but floating point was simpler to start with. Integer has a complication where v32i16/v64i8 aren't legal when the other 512-bit integer types are. llvm-svn: 371325
2019-09-08 08:43:52 +08:00
; SSE-LABEL: test_zero_v16i8_align1:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 8(%rdi)
; SSE-NEXT: movntiq %rax, (%rdi)
; SSE-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v16i8_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16i8_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <16 x i8> zeroinitializer, <16 x i8>* %dst, align 1, !nontemporal !1
ret void
}
; YMM versions.
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v4f64_align1(<4 x double>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v4f64_align1:
; SSE: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; SSE-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE-NEXT: movntiq %rax, 24(%rdi)
; SSE-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v4f64_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 24(%rdi)
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v4f64_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 24(%rdi)
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <4 x double> zeroinitializer, <4 x double>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8f32_align1(<8 x float>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v8f32_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v8f32_align1:
; SSE4A: # %bb.0:
[X86] Make getZeroVector return floating point vectors in their native type on SSE2 and later. isel used to require zero vectors to be canonicalized to a single type to minimize the number of patterns needed to match. This is no longer required. I plan to do this to integers too, but floating point was simpler to start with. Integer has a complication where v32i16/v64i8 aren't legal when the other 512-bit integer types are. llvm-svn: 371325
2019-09-08 08:43:52 +08:00
; SSE4A-NEXT: xorl %eax, %eax
; SSE4A-NEXT: movntiq %rax, 8(%rdi)
; SSE4A-NEXT: movntiq %rax, 24(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v8f32_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v8f32_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 24(%rdi)
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8f32_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 24(%rdi)
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x float> zeroinitializer, <8 x float>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v4i64_align1(<4 x i64>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v4i64_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v4i64_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v4i64_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v4i64_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 24(%rdi)
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v4i64_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 24(%rdi)
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <4 x i64> zeroinitializer, <4 x i64>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8i32_align1(<8 x i32>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v8i32_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v8i32_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v8i32_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v8i32_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 24(%rdi)
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8i32_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 24(%rdi)
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x i32> zeroinitializer, <8 x i32>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16i16_align1(<16 x i16>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v16i16_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v16i16_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v16i16_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v16i16_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 24(%rdi)
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16i16_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 24(%rdi)
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <16 x i16> zeroinitializer, <16 x i16>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v32i8_align1(<32 x i8>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v32i8_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v32i8_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v32i8_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v32i8_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 24(%rdi)
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v32i8_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 24(%rdi)
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <32 x i8> zeroinitializer, <32 x i8>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v4f64_align16(<4 x double>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v4f64_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v4f64_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v4f64_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <4 x double> zeroinitializer, <4 x double>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8f32_align16(<8 x float>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v8f32_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v8f32_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8f32_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x float> zeroinitializer, <8 x float>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v4i64_align16(<4 x i64>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v4i64_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v4i64_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v4i64_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <4 x i64> zeroinitializer, <4 x i64>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8i32_align16(<8 x i32>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v8i32_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v8i32_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8i32_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x i32> zeroinitializer, <8 x i32>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16i16_align16(<16 x i16>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v16i16_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v16i16_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16i16_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <16 x i16> zeroinitializer, <16 x i16>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v32i8_align16(<32 x i8>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v32i8_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v32i8_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v32i8_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <32 x i8> zeroinitializer, <32 x i8>* %dst, align 16, !nontemporal !1
ret void
}
; ZMM versions.
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8f64_align1(<8 x double>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v8f64_align1:
; SSE: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v8f64_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8f64_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 24(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x double> zeroinitializer, <8 x double>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16f32_align1(<16 x float>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v16f32_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 56(%rdi)
; SSE2-NEXT: movntiq %rax, 48(%rdi)
; SSE2-NEXT: movntiq %rax, 40(%rdi)
; SSE2-NEXT: movntiq %rax, 32(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v16f32_align1:
; SSE4A: # %bb.0:
[X86] Make getZeroVector return floating point vectors in their native type on SSE2 and later. isel used to require zero vectors to be canonicalized to a single type to minimize the number of patterns needed to match. This is no longer required. I plan to do this to integers too, but floating point was simpler to start with. Integer has a complication where v32i16/v64i8 aren't legal when the other 512-bit integer types are. llvm-svn: 371325
2019-09-08 08:43:52 +08:00
; SSE4A-NEXT: xorl %eax, %eax
; SSE4A-NEXT: movntiq %rax, 24(%rdi)
; SSE4A-NEXT: movntiq %rax, 8(%rdi)
; SSE4A-NEXT: movntiq %rax, 56(%rdi)
; SSE4A-NEXT: movntiq %rax, 40(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 48(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 32(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v16f32_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 56(%rdi)
; SSE41-NEXT: movntiq %rax, 48(%rdi)
; SSE41-NEXT: movntiq %rax, 40(%rdi)
; SSE41-NEXT: movntiq %rax, 32(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v16f32_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16f32_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 24(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <16 x float> zeroinitializer, <16 x float>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8i64_align1(<8 x i64>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v8i64_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 56(%rdi)
; SSE2-NEXT: movntiq %rax, 48(%rdi)
; SSE2-NEXT: movntiq %rax, 40(%rdi)
; SSE2-NEXT: movntiq %rax, 32(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v8i64_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 56(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 48(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 40(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 32(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v8i64_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 56(%rdi)
; SSE41-NEXT: movntiq %rax, 48(%rdi)
; SSE41-NEXT: movntiq %rax, 40(%rdi)
; SSE41-NEXT: movntiq %rax, 32(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v8i64_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8i64_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 24(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x i64> zeroinitializer, <8 x i64>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16i32_align1(<16 x i32>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v16i32_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 56(%rdi)
; SSE2-NEXT: movntiq %rax, 48(%rdi)
; SSE2-NEXT: movntiq %rax, 40(%rdi)
; SSE2-NEXT: movntiq %rax, 32(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v16i32_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 56(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 48(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 40(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 32(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v16i32_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 56(%rdi)
; SSE41-NEXT: movntiq %rax, 48(%rdi)
; SSE41-NEXT: movntiq %rax, 40(%rdi)
; SSE41-NEXT: movntiq %rax, 32(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v16i32_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16i32_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 24(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <16 x i32> zeroinitializer, <16 x i32>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v32i16_align1(<32 x i16>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v32i16_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 56(%rdi)
; SSE2-NEXT: movntiq %rax, 48(%rdi)
; SSE2-NEXT: movntiq %rax, 40(%rdi)
; SSE2-NEXT: movntiq %rax, 32(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v32i16_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 56(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 48(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 40(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 32(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v32i16_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 56(%rdi)
; SSE41-NEXT: movntiq %rax, 48(%rdi)
; SSE41-NEXT: movntiq %rax, 40(%rdi)
; SSE41-NEXT: movntiq %rax, 32(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v32i16_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-LABEL: test_zero_v32i16_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 32(%rdi)
; AVX512-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
store <32 x i16> zeroinitializer, <32 x i16>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v64i8_align1(<64 x i8>* %dst) nounwind {
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; SSE2-LABEL: test_zero_v64i8_align1:
; SSE2: # %bb.0:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: movntiq %rax, 24(%rdi)
; SSE2-NEXT: movntiq %rax, 16(%rdi)
; SSE2-NEXT: movntiq %rax, 8(%rdi)
; SSE2-NEXT: movntiq %rax, (%rdi)
; SSE2-NEXT: movntiq %rax, 56(%rdi)
; SSE2-NEXT: movntiq %rax, 48(%rdi)
; SSE2-NEXT: movntiq %rax, 40(%rdi)
; SSE2-NEXT: movntiq %rax, 32(%rdi)
; SSE2-NEXT: retq
;
; SSE4A-LABEL: test_zero_v64i8_align1:
; SSE4A: # %bb.0:
; SSE4A-NEXT: xorps %xmm0, %xmm0
; SSE4A-NEXT: movntsd %xmm0, 24(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 16(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 8(%rdi)
; SSE4A-NEXT: movntsd %xmm0, (%rdi)
; SSE4A-NEXT: movntsd %xmm0, 56(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 48(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 40(%rdi)
; SSE4A-NEXT: movntsd %xmm0, 32(%rdi)
; SSE4A-NEXT: retq
;
; SSE41-LABEL: test_zero_v64i8_align1:
; SSE41: # %bb.0:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: movntiq %rax, 24(%rdi)
; SSE41-NEXT: movntiq %rax, 16(%rdi)
; SSE41-NEXT: movntiq %rax, 8(%rdi)
; SSE41-NEXT: movntiq %rax, (%rdi)
; SSE41-NEXT: movntiq %rax, 56(%rdi)
; SSE41-NEXT: movntiq %rax, 48(%rdi)
; SSE41-NEXT: movntiq %rax, 40(%rdi)
; SSE41-NEXT: movntiq %rax, 32(%rdi)
; SSE41-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
;
; AVX-LABEL: test_zero_v64i8_align1:
; AVX: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: movntiq %rax, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-LABEL: test_zero_v64i8_align1:
; AVX512: # %bb.0:
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: xorl %eax, %eax
; AVX512-NEXT: movntiq %rax, 24(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 16(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 8(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, (%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 56(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 48(%rdi)
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026) If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64). llvm-svn: 363592
2019-06-18 02:20:04 +08:00
; AVX512-NEXT: movntiq %rax, 40(%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: movntiq %rax, 32(%rdi)
; AVX512-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
store <64 x i8> zeroinitializer, <64 x i8>* %dst, align 1, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8f64_align16(<8 x double>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v8f64_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v8f64_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
; AVX-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8f64_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x double> zeroinitializer, <8 x double>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16f32_align16(<16 x float>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v16f32_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v16f32_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
; AVX-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16f32_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <16 x float> zeroinitializer, <16 x float>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8i64_align16(<8 x i64>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v8i64_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v8i64_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
; AVX-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8i64_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <8 x i64> zeroinitializer, <8 x i64>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16i32_align16(<16 x i32>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v16i32_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v16i32_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
; AVX-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16i32_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: retq
store <16 x i32> zeroinitializer, <16 x i32>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v32i16_align16(<32 x i16>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v32i16_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v32i16_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
; AVX-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-LABEL: test_zero_v32i16_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
; AVX512-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
store <32 x i16> zeroinitializer, <32 x i16>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v64i8_align16(<64 x i8>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v64i8_align16:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v64i8_align16:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX-NEXT: vmovntps %xmm0, (%rdi)
; AVX-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX-NEXT: vmovntps %xmm0, 32(%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX-NEXT: retq
;
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-LABEL: test_zero_v64i8_align16:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
; AVX512-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
store <64 x i8> zeroinitializer, <64 x i8>* %dst, align 16, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8f64_align32(<8 x double>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v8f64_align32:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v8f64_align32:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8f64_align32:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
store <8 x double> zeroinitializer, <8 x double>* %dst, align 32, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16f32_align32(<16 x float>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v16f32_align32:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v16f32_align32:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16f32_align32:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
store <16 x float> zeroinitializer, <16 x float>* %dst, align 32, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v8i64_align32(<8 x i64>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v8i64_align32:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v8i64_align32:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v8i64_align32:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
store <8 x i64> zeroinitializer, <8 x i64>* %dst, align 32, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v16i32_align32(<16 x i32>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v16i32_align32:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v16i32_align32:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
; AVX512-LABEL: test_zero_v16i32_align32:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
[X86][SSE] Prevent misaligned non-temporal vector load/store combines For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway. First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets. Differential Revision: https://reviews.llvm.org/D63246 llvm-svn: 363564
2019-06-17 22:26:10 +08:00
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
store <16 x i32> zeroinitializer, <16 x i32>* %dst, align 32, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v32i16_align32(<32 x i16>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v32i16_align32:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v32i16_align32:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-LABEL: test_zero_v32i16_align32:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
store <32 x i16> zeroinitializer, <32 x i16>* %dst, align 32, !nontemporal !1
ret void
}
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests. llvm-svn: 363552
2019-06-17 20:35:26 +08:00
define void @test_zero_v64i8_align32(<64 x i8>* %dst) nounwind {
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
; SSE-LABEL: test_zero_v64i8_align32:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movntps %xmm0, 48(%rdi)
; SSE-NEXT: movntps %xmm0, 32(%rdi)
; SSE-NEXT: movntps %xmm0, 16(%rdi)
; SSE-NEXT: movntps %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: test_zero_v64i8_align32:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX-NEXT: vmovntps %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
[X86][AVX] Split under-aligned vector nt-stores. If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it. llvm-svn: 363582
2019-06-18 01:22:38 +08:00
; AVX512-LABEL: test_zero_v64i8_align32:
; AVX512: # %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
[X86][SSE] Add tests for underaligned nt stores Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split) llvm-svn: 363249
2019-06-13 18:41:56 +08:00
store <64 x i8> zeroinitializer, <64 x i8>* %dst, align 32, !nontemporal !1
ret void
}
!1 = !{i32 1}