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llvm-project/llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll

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X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc < %s -mtriple=i686-- -disable-block-placement | FileCheck %s
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
;
; Test RegistersDefinedFromSameValue. We have multiple copies of the same vreg:
; while.body85.i:
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
; %1 = copy %2
; %2 = add
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; critical edge from land.lhs.true.i -> if.end117.i:
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
; %27 = %2
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; critical edge from land.lhs.true103.i -> if.end117.i:
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
; %27 = %2
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; if.then108.i:
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
; %27 = %1
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
;
; Prior to fixing PR10920 401.bzip miscompile, the coalescer would
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
; consider %1 and %27 to be copies of the same value. It would
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; then remove one of the critical edge copes, which cannot safely be removed.
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; There are two obvious ways the register-allocator could go here, either
; reusing the pre-addition register later, or the post-addition one. Currently,
; it does the latter, so we check:
Don't delete empty preheaders in CodeGenPrepare if it would create a critical edge Presently, CodeGenPrepare deletes all nearly empty (only phi and branch) basic blocks. This pass can delete loop preheaders which frequently creates critical edges. A preheader can be a convenient place to spill registers to the stack. If the entrance to a loop body is a critical edge, then spills may occur in the loop body rather than immediately before it. This patch protects loop preheaders from deletion in CodeGenPrepare even if they are nearly empty. Since the patch alters the CFG, it affects a large number of test cases. In most cases, the changes are merely cosmetic (basic blocks have different names or instruction orders change slightly). I am somewhat concerned about the test/CodeGen/Mips/brdelayslot.ll test case. If the loop preheader is not deleted, then the MIPS backend does not take advantage of a branch delay slot. Consequently, I would like some close review by a MIPS expert. The patch also partially subsumes D16893 from George Burgess IV. George correctly notes that CodeGenPrepare does not actually preserve the dominator tree. I think the dominator tree was usually not valid when CodeGenPrepare ran, but I am using LoopInfo to mark preheaders, so the dominator tree is now always valid before CodeGenPrepare. Author: Tom Jablin (tjablin) Reviewers: hfinkel george.burgess.iv vkalintiris dsanders kbarton cycheng http://reviews.llvm.org/D16984 llvm-svn: 265397
2016-04-05 22:06:20 +08:00
; CHECK: # %while.body85.i{{$}}
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; CHECK-NOT: # %
; CHECK-NOT: add
; CHECK: movl %[[POSTR:e[abcdxi]+]], %[[PRER:e[abcdxi]+]]
; CHECK: addl %{{.*}}, %[[POSTR]]
; CHECK: # %while.end.i
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; CHECK-NOT: movl %[[POSTR]]
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; CHECK: # %land.lhs.true.i
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; CHECK-NOT: movl %[[POSTR]]
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; CHECK: # %land.lhs.true103.i
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; CHECK-NOT: movl %[[POSTR]]
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; CHECK: # %if.then108.i
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; CHECK: movl %[[PRER]], %[[POSTR]]
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
; CHECK: # %if.end117.i
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; and use it for fprintf:
; CHECK: movl %[[POSTR]], 12(%esp)
; If it ever reverts to reusing the pre-addition register then we should
; *probably* check this instead (it certainly worked last time):
; CHECKALT: # %while.body85.i
; CHECKALT-NOT: # %
; CHECKALT-NOT: add
; CHECKALT: movl %[[POSTR:e[abcdxi]+]], %[[PRER:e[abcdxi]+]]
; CHECKALT: addl %{{.*}}, %[[POSTR]]
; CHECKALT: # %while.end.i
; CHECKALT: movl %[[POSTR]], %[[USER:e[abcdxi]+]]
; CHECKALT: # %land.lhs.true.i
; CHECKALT: movl %[[POSTR]], %[[USER]]
; CHECKALT: # %land.lhs.true103.i
; CHECKALT: movl %[[POSTR]], %[[USER]]
; CHECKALT: # %if.then108.i
; [[PRER] live out, so nothing on this path should define it.
; CHECKALT-NOT: , %[[PRER]]
; CHECKALT: # %if.end117.i
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
@.str3 = external unnamed_addr constant [59 x i8], align 1
define void @BZ2_compressBlock() nounwind ssp {
entry:
br i1 undef, label %if.then68, label %if.end85
if.then68: ; preds = %entry
br label %for.body.i.i
for.body.i.i: ; preds = %for.inc.i.i, %if.then68
br i1 undef, label %for.inc.i.i, label %if.then.i.i
if.then.i.i: ; preds = %for.body.i.i
br label %for.inc.i.i
for.inc.i.i: ; preds = %if.then.i.i, %for.body.i.i
br i1 undef, label %makeMaps_e.exit.i, label %for.body.i.i
makeMaps_e.exit.i: ; preds = %for.inc.i.i
br i1 undef, label %for.cond19.preheader.i, label %for.cond.for.cond19.preheader_crit_edge.i
for.cond.for.cond19.preheader_crit_edge.i: ; preds = %makeMaps_e.exit.i
unreachable
for.cond19.preheader.i: ; preds = %makeMaps_e.exit.i
br i1 undef, label %for.body25.lr.ph.i, label %for.cond33.preheader.i
for.body25.lr.ph.i: ; preds = %for.cond19.preheader.i
br label %for.body25.i
for.cond33.preheader.i: ; preds = %for.body25.i, %for.cond19.preheader.i
br i1 undef, label %if.then.i, label %if.end.i
for.body25.i: ; preds = %for.body25.i, %for.body25.lr.ph.i
br i1 undef, label %for.body25.i, label %for.cond33.preheader.i
if.then.i: ; preds = %for.cond33.preheader.i
br label %if.end.i
if.end.i: ; preds = %if.then.i, %for.cond33.preheader.i
br i1 undef, label %for.inc27.us.5.i, label %for.end30.i
for.end30.i: ; preds = %for.inc27.us.5.i, %if.end.i
br i1 undef, label %if.end36.i, label %if.then35.i
if.then35.i: ; preds = %for.end30.i
unreachable
if.end36.i: ; preds = %for.end30.i
%sub83.i = add nsw i32 undef, 1
br label %while.body.i188
for.cond182.preheader.i: ; preds = %for.end173.i
br i1 undef, label %for.inc220.us.i, label %while.body300.preheader.i
while.body.i188: ; preds = %for.end173.i, %if.end36.i
%gs.0526.i = phi i32 [ 0, %if.end36.i ], [ %add177.i, %for.end173.i ]
%or.cond514517.i = and i1 false, undef
br i1 %or.cond514517.i, label %while.body85.i, label %if.end117.i
while.body85.i: ; preds = %while.body85.i, %while.body.i188
%aFreq.0518.i = phi i32 [ %add93.i, %while.body85.i ], [ 0, %while.body.i188 ]
%inc87.i = add nsw i32 0, 1
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp91.i = load i32, i32* undef, align 4
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
%add93.i = add nsw i32 %tmp91.i, %aFreq.0518.i
%or.cond514.i = and i1 undef, false
br i1 %or.cond514.i, label %while.body85.i, label %while.end.i
while.end.i: ; preds = %while.body85.i
br i1 undef, label %land.lhs.true.i, label %if.end117.i
land.lhs.true.i: ; preds = %while.end.i
br i1 undef, label %land.lhs.true103.i, label %if.end117.i
land.lhs.true103.i: ; preds = %land.lhs.true.i
br i1 undef, label %if.then108.i, label %if.end117.i
if.then108.i: ; preds = %land.lhs.true103.i
br label %if.end117.i
if.end117.i: ; preds = %if.then108.i, %land.lhs.true103.i, %land.lhs.true.i, %while.end.i, %while.body.i188
%aFreq.1.i = phi i32 [ %aFreq.0518.i, %if.then108.i ], [ %add93.i, %land.lhs.true103.i ], [ %add93.i, %land.lhs.true.i ], [ %add93.i, %while.end.i ], [ 0, %while.body.i188 ]
%ge.1.i = phi i32 [ 0, %if.then108.i ], [ %inc87.i, %land.lhs.true103.i ], [ %inc87.i, %land.lhs.true.i ], [ %inc87.i, %while.end.i ], [ 0, %while.body.i188 ]
br i1 undef, label %if.then122.i, label %for.cond138.preheader.i
if.then122.i: ; preds = %if.end117.i
[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction See r230786 and r230794 for similar changes to gep and load respectively. Call is a bit different because it often doesn't have a single explicit type - usually the type is deduced from the arguments, and just the return type is explicit. In those cases there's no need to change the IR. When that's not the case, the IR usually contains the pointer type of the first operand - but since typed pointers are going away, that representation is insufficient so I'm just stripping the "pointerness" of the explicit type away. This does make the IR a bit weird - it /sort of/ reads like the type of the first operand: "call void () %x(" but %x is actually of type "void ()*" and will eventually be just of type "ptr". But this seems not too bad and I don't think it would benefit from repeating the type ("void (), void () * %x(" and then eventually "void (), ptr %x(") as has been done with gep and load. This also has a side benefit: since the explicit type is no longer a pointer, there's no ambiguity between an explicit type and a function that returns a function pointer. Previously this case needed an explicit type (eg: a function returning a void() function was written as "call void () () * @x(" rather than "call void () * @x(" because of the ambiguity between a function returning a pointer to a void() function and a function returning void). No ambiguity means even function pointer return types can just be written alone, without writing the whole function's type. This leaves /only/ the varargs case where the explicit type is required. Given the special type syntax in call instructions, the regex-fu used for migration was a bit more involved in its own unique way (as every one of these is) so here it is. Use it in conjunction with the apply.sh script and associated find/xargs commands I've provided in rr230786 to migrate your out of tree tests. Do let me know if any of this doesn't cover your cases & we can iterate on a more general script/regexes to help others with out of tree tests. About 9 test cases couldn't be automatically migrated - half of those were functions returning function pointers, where I just had to manually delete the function argument types now that we didn't need an explicit function type there. The other half were typedefs of function types used in calls - just had to manually drop the * from those. import fileinput import sys import re pat = re.compile(r'((?:=|:|^|\s)call\s(?:[^@]*?))(\s*$|\s*(?:(?:\[\[[a-zA-Z0-9_]+\]\]|[@%](?:(")?[\\\?@a-zA-Z0-9_.]*?(?(3)"|)|{{.*}}))(?:\(|$)|undef|inttoptr|bitcast|null|asm).*$)') addrspace_end = re.compile(r"addrspace\(\d+\)\s*\*$") func_end = re.compile("(?:void.*|\)\s*)\*$") def conv(match, line): if not match or re.search(addrspace_end, match.group(1)) or not re.search(func_end, match.group(1)): return line return line[:match.start()] + match.group(1)[:match.group(1).rfind('*')].rstrip() + match.group(2) + line[match.end():] for line in sys.stdin: sys.stdout.write(conv(re.search(pat, line), line)) llvm-svn: 235145
2015-04-17 07:24:18 +08:00
call void (...) @fprintf(i32 undef, i32 %gs.0526.i, i32 %ge.1.i, i32 %aFreq.1.i, double undef) nounwind
Test cases that assume layout should use -disable-code-place. llvm-svn: 154908
2012-04-17 14:20:42 +08:00
br label %for.cond138.preheader.i
for.cond138.preheader.i: ; preds = %if.then122.i, %if.end117.i
br i1 undef, label %for.body143.lr.ph.i, label %for.end173.i
for.body143.lr.ph.i: ; preds = %for.cond138.preheader.i
br label %for.body143.i
for.body143.i: ; preds = %for.body143.i, %for.body143.lr.ph.i
br i1 undef, label %for.end173.i, label %for.body143.i
for.end173.i: ; preds = %for.body143.i, %for.cond138.preheader.i
%add177.i = add nsw i32 %ge.1.i, 1
%cmp73.i = icmp sgt i32 undef, 0
br i1 %cmp73.i, label %while.body.i188, label %for.cond182.preheader.i
for.inc220.us.i: ; preds = %for.cond182.preheader.i
unreachable
while.body300.preheader.i: ; preds = %for.cond182.preheader.i
br i1 undef, label %for.end335.i, label %while.end2742.i
for.end335.i: ; preds = %for.end2039.i, %while.body300.preheader.i
br label %for.body2021.i
for.body2021.i: ; preds = %for.body2021.i, %for.end335.i
br i1 undef, label %for.body2021.i, label %for.end2039.i
for.end2039.i: ; preds = %for.body2021.i
br label %for.end335.i
while.end2742.i: ; preds = %while.body300.preheader.i
br i1 undef, label %if.then2748.i, label %for.body2778.i
if.then2748.i: ; preds = %while.end2742.i
unreachable
for.body2778.i: ; preds = %while.end2742.i
unreachable
for.inc27.us.5.i: ; preds = %if.end.i
br label %for.end30.i
if.end85: ; preds = %entry
ret void
}
declare void @fprintf(...) nounwind