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llvm-project/llvm/lib/Target/Mips/Mips.td

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remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
//
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
support for Schedule included on Mips.td llvm-svn: 41159
2007-08-18 10:18:07 +08:00
// This is the top level entry point for the Mips target.
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
support for Schedule included on Mips.td llvm-svn: 41159
2007-08-18 10:18:07 +08:00
// Target-independent interfaces
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. llvm-svn: 59953
2008-11-24 15:34:46 +08:00
include "llvm/Target/Target.td"
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
2014-05-07 18:27:09 +08:00
// The overall idea of the PredicateControl class is to chop the Predicates list
// into subsets that are usually overridden independently. This allows
// subclasses to partially override the predicates of their superclasses without
// having to re-add all the existing predicates.
class PredicateControl {
// Predicates for the encoding scheme in use such as HasStdEnc
list<Predicate> EncodingPredicates = [];
[mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 llvm-svn: 208201
2014-05-07 20:48:37 +08:00
// Predicates for the GPR size such as IsGP64bit
list<Predicate> GPRPredicates = [];
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
// Predicates for the PTR size such as IsPTR64bit
list<Predicate> PTRPredicates = [];
[mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 llvm-svn: 208201
2014-05-07 20:48:37 +08:00
// Predicates for the FGR size and layout such as IsFP64bit
list<Predicate> FGRPredicates = [];
[mips] Split out ASEPredicate from InsnPredicates (NFC) This simplifies tagging instructions with the correct ISA and ASE, albeit making instruction definitions a bit more verbose. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44299 llvm-svn: 327265
2018-03-12 21:16:12 +08:00
// Predicates for the instruction group membership such as ISA's.
[mips] Add ISA_<name> adverbs and start using them instead of AdditionalPredicates overrides Summary: One small functional change. The recently added PAUSE instruction now has the HasStdEnc predicate which was accidentally removed by a Requires<>. Depends on D3640 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3641 llvm-svn: 208209
2014-05-07 21:57:22 +08:00
list<Predicate> InsnPredicates = [];
[mips] Split out ASEPredicate from InsnPredicates (NFC) This simplifies tagging instructions with the correct ISA and ASE, albeit making instruction definitions a bit more verbose. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44299 llvm-svn: 327265
2018-03-12 21:16:12 +08:00
// Predicate for the ASE that an instruction belongs to.
list<Predicate> ASEPredicate = [];
[mips] Add the SoftFloat MipsSubtarget feature. Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
2015-05-07 18:29:52 +08:00
// Predicate for marking the instruction as usable in hard-float mode only.
list<Predicate> HardFloatPredicate = [];
[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
2014-05-07 18:27:09 +08:00
// Predicates for anything else
list<Predicate> AdditionalPredicates = [];
list<Predicate> Predicates = !listconcat(EncodingPredicates,
[mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 llvm-svn: 208201
2014-05-07 20:48:37 +08:00
GPRPredicates,
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
PTRPredicates,
[mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 llvm-svn: 208201
2014-05-07 20:48:37 +08:00
FGRPredicates,
[mips] Add ISA_<name> adverbs and start using them instead of AdditionalPredicates overrides Summary: One small functional change. The recently added PAUSE instruction now has the HasStdEnc predicate which was accidentally removed by a Requires<>. Depends on D3640 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3641 llvm-svn: 208209
2014-05-07 21:57:22 +08:00
InsnPredicates,
[mips] Add the SoftFloat MipsSubtarget feature. Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
2015-05-07 18:29:52 +08:00
HardFloatPredicate,
[mips] Split out ASEPredicate from InsnPredicates (NFC) This simplifies tagging instructions with the correct ISA and ASE, albeit making instruction definitions a bit more verbose. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44299 llvm-svn: 327265
2018-03-12 21:16:12 +08:00
ASEPredicate,
[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
2014-05-07 18:27:09 +08:00
AdditionalPredicates);
}
// Like Requires<> but for the AdditionalPredicates list
class AdditionalRequires<list<Predicate> preds> {
list<Predicate> AdditionalPredicates = preds;
}
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
// Register File, Calling Conv, Instruction Descriptions
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
include "MipsRegisterInfo.td"
support for Schedule included on Mips.td llvm-svn: 41159
2007-08-18 10:18:07 +08:00
include "MipsSchedule.td"
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
include "MipsInstrInfo.td"
support for Schedule included on Mips.td llvm-svn: 41159
2007-08-18 10:18:07 +08:00
include "MipsCallingConv.td"
[MIPS GlobalISel] Select add i32, i32 Add the minimal support necessary to lower a function that returns the sum of two i32 values. Support argument/return lowering of i32 values through registers only. Add tablegen for regbankselect and instructionselect. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D44304 llvm-svn: 329819
2018-04-11 23:12:32 +08:00
include "MipsRegisterBanks.td"
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
[mips] Update the P5600 scheduler for isComplete = 1 These changes update the schedule model for the P5600 and includes the rest of the MSA and MIPS32R5 instruction sets. Reviewers: dsanders, vkalintris Differential Revision: https://reviews.llvm.org/D21835 llvm-svn: 277441
2016-08-02 18:32:00 +08:00
// Avoid forward declaration issues.
include "MipsScheduleP5600.td"
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
include "MipsScheduleGeneric.td"
[mips] Update the P5600 scheduler for isComplete = 1 These changes update the schedule model for the P5600 and includes the rest of the MSA and MIPS32R5 instruction sets. Reviewers: dsanders, vkalintris Differential Revision: https://reviews.llvm.org/D21835 llvm-svn: 277441
2016-08-02 18:32:00 +08:00
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
2010-04-05 11:10:20 +08:00
def MipsInstrInfo : InstrInfo;
support for Schedule included on Mips.td llvm-svn: 41159
2007-08-18 10:18:07 +08:00
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
// Mips Subtarget features //
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
[mips] Invert the abicalls feature bit to be noabicalls so that it's possible for -mno-abicalls to take effect. Also added the testcase that should have been in r215194. This behaviour has surprised me a few times now. The problem is that the generated MipsSubtarget::ParseSubtargetFeatures() contains code like this: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; so '-abicalls' means 'leave it at the default' and '+abicalls' means 'set it to true'. In this case, (and the similar -modd-spreg case) I'd like the code to be IsABICalls = (Bits & Mips::FeatureABICalls) != 0; or possibly: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; else IsABICalls = false; and preferably arrange for 'Bits & Mips::FeatureABICalls' to be true by default (on some triples). llvm-svn: 215211
2014-08-08 23:47:17 +08:00
def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
[mips] Remove redundant periods from -mattr=help descriptions for MIPS. Summary: Also fixes an infringement of the 80-column limit rule. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7910 llvm-svn: 230748
2015-02-27 18:44:02 +08:00
"Disable SVR4-style position-independent code">;
[mips][atomics] Fix atomic instruction descriptions and uses. PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
2016-06-14 19:29:28 +08:00
def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
"Pointers are 64-bit wide">;
Fixed features usage. llvm-svn: 53277
2008-07-09 13:32:22 +08:00
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
[mips] Remove redundant periods from -mattr=help descriptions for MIPS. Summary: Also fixes an infringement of the 80-column limit rule. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7910 llvm-svn: 230748
2015-02-27 18:44:02 +08:00
"General Purpose Registers are 64-bit wide">;
Fixed features usage. llvm-svn: 53277
2008-07-09 13:32:22 +08:00
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
[mips] Remove redundant periods from -mattr=help descriptions for MIPS. Summary: Also fixes an infringement of the 80-column limit rule. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7910 llvm-svn: 230748
2015-02-27 18:44:02 +08:00
"Support 64-bit FP registers">;
[mips] Added FPXX modeless calling convention. Differential Revision: http://reviews.llvm.org/D4293 llvm-svn: 212726
2014-07-10 23:36:12 +08:00
def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
[mips] Remove redundant periods from -mattr=help descriptions for MIPS. Summary: Also fixes an infringement of the 80-column limit rule. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7910 llvm-svn: 230748
2015-02-27 18:44:02 +08:00
"Support for FPXX">;
[mips] Add initial support for NaN2008 in the back-end. This is so that EF_MIPS_NAN2008 is set if we are using IEEE 754-2008 NaN encoding (-mnan=2008). This patch also adds support for parsing '.nan legacy' and '.nan 2008' assembly directives. The handling of these directives should match GAS' behaviour i.e., the last directive in use sets the ELF header bit (EF_MIPS_NAN2008). Differential Revision: http://reviews.llvm.org/D3346 llvm-svn: 206396
2014-04-16 23:48:55 +08:00
def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
[mips] Remove redundant periods from -mattr=help descriptions for MIPS. Summary: Also fixes an infringement of the 80-column limit rule. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7910 llvm-svn: 230748
2015-02-27 18:44:02 +08:00
"IEEE 754-2008 NaN encoding">;
Fixed features usage. llvm-svn: 53277
2008-07-09 13:32:22 +08:00
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
"true", "Only supports single precision float">;
[mips] Add the SoftFloat MipsSubtarget feature. Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
2015-05-07 18:29:52 +08:00
def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
"Does not support floating point instructions">;
[mips] Add support for -modd-spreg/-mno-odd-spreg Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
2014-07-10 21:38:23 +08:00
def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
"Disable odd numbered single-precision "
"registers">;
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com) llvm-svn: 118447
2010-11-09 05:42:32 +08:00
def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
[mips] Remove redundant periods from -mattr=help descriptions for MIPS. Summary: Also fixes an infringement of the 80-column limit rule. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7910 llvm-svn: 230748
2015-02-27 18:44:02 +08:00
"true", "Enable vector FPU instructions">;
[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 llvm-svn: 208221
2014-05-08 00:25:22 +08:00
def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
"Mips I ISA Support [highly experimental]">;
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips II ISA Support [highly experimental]",
[FeatureMips1]>;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
"Subset of MIPS-III that is also in MIPS32 "
"[highly experimental]">;
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
"Subset of MIPS-III that is also in MIPS32r2 "
"[highly experimental]">;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
"MIPS III ISA Support [highly experimental]",
[FeatureMips2, FeatureMips3_32,
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
FeatureMips3_32r2, FeatureGP64Bit,
FeatureFP64Bit]>;
[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
2014-05-09 22:06:17 +08:00
def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
"Subset of MIPS-IV that is also in MIPS32 "
"[highly experimental]">;
[mips] Replace FeatureFPIdx with FeatureMips4_32r2 Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
2014-05-12 19:56:16 +08:00
def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
"Subset of MIPS-IV that is also in MIPS32r2 "
"[highly experimental]">;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
"Mips4", "MIPS IV ISA Support",
[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
2014-05-09 22:06:17 +08:00
[FeatureMips3, FeatureMips4_32,
[mips] Replace FeatureFPIdx with FeatureMips4_32r2 Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
2014-05-12 19:56:16 +08:00
FeatureMips4_32r2]>;
[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
2014-05-12 20:52:44 +08:00
def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
"Subset of MIPS-V that is also in MIPS32r2 "
"[highly experimental]">;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
"MIPS V ISA Support [highly experimental]",
[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
2014-05-12 20:52:44 +08:00
[FeatureMips4, FeatureMips5_32r2]>;
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
"Mips32 ISA Support",
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
[FeatureMips2, FeatureMips3_32,
[mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64 Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
2014-05-12 20:41:59 +08:00
FeatureMips4_32]>;
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com) llvm-svn: 118447
2010-11-09 05:42:32 +08:00
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support",
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
[FeatureMips3_32r2, FeatureMips4_32r2,
FeatureMips5_32r2, FeatureMips32]>;
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion",
"Mips32r3", "Mips32r3 ISA Support",
[FeatureMips32r2]>;
def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion",
"Mips32r5", "Mips32r5 ISA Support",
[FeatureMips32r3]>;
[mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 llvm-svn: 208399
2014-05-09 17:46:21 +08:00
def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
"Mips32r6",
"Mips32r6 ISA Support [experimental]",
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
[FeatureMips32r5, FeatureFP64Bit,
[mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 llvm-svn: 208399
2014-05-09 17:46:21 +08:00
FeatureNaN2008]>;
Initial Mips64 support. Patch by Liu with some modifications. llvm-svn: 140178
2011-09-21 04:28:08 +08:00
def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
"Mips64", "Mips64 ISA Support",
[mips] Replace FeatureFPIdx with FeatureMips4_32r2 Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
2014-05-12 19:56:16 +08:00
[FeatureMips5, FeatureMips32]>;
Initial Mips64 support. Patch by Liu with some modifications. llvm-svn: 140178
2011-09-21 04:28:08 +08:00
def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
"Mips64r2", "Mips64r2 ISA Support",
[FeatureMips64, FeatureMips32r2]>;
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion",
"Mips64r3", "Mips64r3 ISA Support",
[FeatureMips64r2, FeatureMips32r3]>;
def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion",
"Mips64r5", "Mips64r5 ISA Support",
[FeatureMips64r3, FeatureMips32r5]>;
[mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 llvm-svn: 208399
2014-05-09 17:46:21 +08:00
def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
"Mips64r6",
"Mips64r6 ISA Support [experimental]",
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
[FeatureMips32r6, FeatureMips64r5,
[mips][mips64r6] Added mul/mulu/muh/muhu Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 llvm-svn: 208576
2014-05-12 23:12:45 +08:00
FeatureNaN2008]>;
[mips] Recommit: "N64 static relocation model support" This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! This version corrects a "Conditional jump or move depends on uninitialised value(s)" error detected by valgrind present in the original commit. Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293279
2017-01-27 19:36:52 +08:00
def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true",
"Symbols are 32 bit on Mips64">;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
This patch adds the register class for MIPS16 as well as the ability for llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
2012-05-17 06:19:56 +08:00
def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
"Mips16 mode">;
Add flags and feature bits for mips dsp. llvm-svn: 164428
2012-09-22 07:41:49 +08:00
def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
"Mips DSP-R2 ASE", [FeatureDSP]>;
[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 llvm-svn: 250058
2015-10-13 00:07:25 +08:00
def FeatureDSPR3
: SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
[ FeatureDSP, FeatureDSPR2 ]>;
Add flags and feature bits for mips dsp. llvm-svn: 164428
2012-09-22 07:41:49 +08:00
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
[mips] Add support for CRC ASE This includes Instructions: crc32b, crc32h, crc32w, crc32d, crc32cb, crc32ch, crc32cw, crc32cd Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc Attribute: crc .MIPS.abiflags: CRC (0x8000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44176 llvm-svn: 327511
2018-03-14 22:13:31 +08:00
def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;
[mips] Add support for Virtualization ASE This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
2018-04-27 17:12:08 +08:00
def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true",
"Mips Virtualization ASE">;
[mips] Add support for Global INValidate ASE This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
2018-05-18 00:30:32 +08:00
def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
"Mips Global Invalidate ASE">;
This patch that sets the Mips ELF header flag for MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
2013-02-05 17:30:03 +08:00
def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
"microMips mode">;
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
"true", "Octeon cnMIPS Support",
[FeatureMips64r2]>;
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
def FeatureUseTCCInDIV : SubtargetFeature<
"use-tcc-in-div",
"UseTCCInDIV", "false",
"Force the assembler to use trapping">;
[mips] Add madd4 subtarget feature Addition of a feature and a predicate used to control generation of madd.fmt and similar instructions. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33400 llvm-svn: 304801
2017-06-06 23:33:01 +08:00
def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
"Disable 4-operand madd.fmt and related instructions">;
[mips][mt][1/7] Add the MT ASE as a subtarget feature. Preparatory work for adding the MIPS MT (multi-threading) ASE instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35247 llvm-svn: 307679
2017-07-12 02:03:20 +08:00
def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
[mips] Handle the `long-calls` feature flags in the MIPS backend If the `long-calls` feature flags is enabled, disable use of the `jal` instruction. Instead of that call a function by by first loading its address into a register, and then using the contents of that register. Differential revision: https://reviews.llvm.org/D35168 llvm-svn: 308087
2017-07-15 15:14:25 +08:00
def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
"Disable use of the jal instruction">;
[mips] Spectre variant two mitigation for MIPSR2 This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 llvm-svn: 325653
2018-02-21 08:06:53 +08:00
def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
"UseIndirectJumpsHazard",
"true", "Use indirect jump"
" guards to prevent certain speculation based attacks">;
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
// Mips processors supported.
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. llvm-svn: 129612
2011-04-16 05:51:11 +08:00
//===----------------------------------------------------------------------===//
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
[mips][p5600] Added P5600 processor and initial scheduler. Summary: The P5600 is an out-of-order, superscalar implementation of the MIPS32R5 architecture. The scheduler has a few missing details (see the 'Tricky Instructions' section and some quirks of the P5600 are deliberately omitted due to implementation difficulty and low chance of significant benefit (e.g. the predicate on P5600WriteEitherALU). However, testing on SingleSource is showing significant performance benefits on some apps (seven in the 10-30% range) and only one significant regression (12%) when -pre-RA-sched=linearize is given. Without -pre-RA-sched=linearize the results are more variable. Some do even better (up to 55% improvement) but increased numbers of copies are slowing others down (up to 12%). Overall, the scheduler as it currently stands is a 2.4% win with -pre-RA-sched=linearize and a 2.7% win without -pre-RA-sched=linearize. I'm sure we can improve on this further. For completeness, the FPGA this was tested on shows some failures with and without the P5600 scheduler. These appear to be scheduling related since the two test runs have fairly different sets of failing tests even after accounting for other factors (e.g. spurious connection failures) however it's not P5600 specific since we also get some for the generic scheduler. Reviewers: vkalintiris Subscribers: mpf, llvm-commits, atrick, vkalintiris Differential Revision: http://reviews.llvm.org/D12193 llvm-svn: 248725
2015-09-29 02:24:08 +08:00
def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
"MipsSubtarget::CPU::P5600",
"The P5600 Processor", [FeatureMips32r5]>;
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
class Proc<string Name, list<SubtargetFeature> Features>
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
: ProcessorModel<Name, MipsGenericModel, Features>;
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
2008-07-06 03:05:21 +08:00
Move the Mips target to storing the ABI in the TargetMachine rather than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
2015-01-27 01:33:46 +08:00
def : Proc<"mips1", [FeatureMips1]>;
def : Proc<"mips2", [FeatureMips2]>;
def : Proc<"mips32", [FeatureMips32]>;
def : Proc<"mips32r2", [FeatureMips32r2]>;
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
def : Proc<"mips32r3", [FeatureMips32r3]>;
def : Proc<"mips32r5", [FeatureMips32r5]>;
Move the Mips target to storing the ABI in the TargetMachine rather than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
2015-01-27 01:33:46 +08:00
def : Proc<"mips32r6", [FeatureMips32r6]>;
def : Proc<"mips3", [FeatureMips3]>;
def : Proc<"mips4", [FeatureMips4]>;
def : Proc<"mips5", [FeatureMips5]>;
def : Proc<"mips64", [FeatureMips64]>;
def : Proc<"mips64r2", [FeatureMips64r2]>;
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
def : Proc<"mips64r3", [FeatureMips64r3]>;
def : Proc<"mips64r5", [FeatureMips64r5]>;
Move the Mips target to storing the ABI in the TargetMachine rather than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
2015-01-27 01:33:46 +08:00
def : Proc<"mips64r6", [FeatureMips64r6]>;
def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
[mips][p5600] Added P5600 processor and initial scheduler. Summary: The P5600 is an out-of-order, superscalar implementation of the MIPS32R5 architecture. The scheduler has a few missing details (see the 'Tricky Instructions' section and some quirks of the P5600 are deliberately omitted due to implementation difficulty and low chance of significant benefit (e.g. the predicate on P5600WriteEitherALU). However, testing on SingleSource is showing significant performance benefits on some apps (seven in the 10-30% range) and only one significant regression (12%) when -pre-RA-sched=linearize is given. Without -pre-RA-sched=linearize the results are more variable. Some do even better (up to 55% improvement) but increased numbers of copies are slowing others down (up to 12%). Overall, the scheduler as it currently stands is a 2.4% win with -pre-RA-sched=linearize and a 2.7% win without -pre-RA-sched=linearize. I'm sure we can improve on this further. For completeness, the FPGA this was tested on shows some failures with and without the P5600 scheduler. These appear to be scheduling related since the two test runs have fairly different sets of failing tests even after accounting for other factors (e.g. spurious connection failures) however it's not P5600 specific since we also get some for the generic scheduler. Reviewers: vkalintiris Subscribers: mpf, llvm-commits, atrick, vkalintiris Differential Revision: http://reviews.llvm.org/D12193 llvm-svn: 248725
2015-09-29 02:24:08 +08:00
def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com) llvm-svn: 118447
2010-11-09 05:42:32 +08:00
Add stub methods for mips assembly matcher. Patch by Vladimir Medic. llvm-svn: 162124
2012-08-18 04:16:42 +08:00
def MipsAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
}
def MipsAsmParserVariant : AsmParserVariant {
int Variant = 0;
// Recognize hard coded registers.
string RegisterPrefix = "$";
}
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
def Mips : Target {
let InstructionSet = MipsInstrInfo;
Add stub methods for mips assembly matcher. Patch by Vladimir Medic. llvm-svn: 162124
2012-08-18 04:16:42 +08:00
let AssemblyParsers = [MipsAsmParser];
let AssemblyParserVariants = [MipsAsmParserVariant];
[MachineOperand][Target] MachineOperand::isRenamable semantics changes Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
2018-02-24 02:25:08 +08:00
let AllowRegisterRenaming = 1;
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
2007-06-06 15:42:06 +08:00
}