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llvm-project/llvm/test/CodeGen/X86/pr22774.ll

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[X86] Regenerate test. NFC. llvm-svn: 281099
2016-09-10 05:36:17 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Fix line ending in test CodeGen/X86/pr22774.ll. NFC. Also, replaced line with 'target triple' with flag -mtriple on the RUN line. Removed the data layout string as it is not needed. llvm-svn: 231654
2015-03-09 23:02:01 +08:00
; RUN: llc -mtriple=x86_64-pc-linux-gnu -mattr=+avx < %s | FileCheck %s
[DAGCombine] Fix a bug in a BUILD_VECTOR combine When trying to convert a BUILD_VECTOR into a shuffle, we try to split a single source vector that is twice as wide as the destination vector. We can not do this when we also need the zero vector to create a blend. This fixes PR22774. Differential Revision: http://reviews.llvm.org/D8040 llvm-svn: 231219
2015-03-04 15:27:39 +08:00
@in = global <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, align 32
@out = global <2 x i64> zeroinitializer, align 16
define i32 @_Z3foov() {
[X86] Regenerate test. NFC. llvm-svn: 281099
2016-09-10 05:36:17 +08:00
; CHECK-LABEL: _Z3foov:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: vmovdqa {{.*}}(%rip), %ymm0
; CHECK-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; CHECK-NEXT: vmovdqa %xmm0, {{.*}}(%rip)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
[DAGCombine] Fix a bug in a BUILD_VECTOR combine When trying to convert a BUILD_VECTOR into a shuffle, we try to split a single source vector that is twice as wide as the destination vector. We can not do this when we also need the zero vector to create a blend. This fixes PR22774. Differential Revision: http://reviews.llvm.org/D8040 llvm-svn: 231219
2015-03-04 15:27:39 +08:00
entry:
%0 = load <4 x i64>, <4 x i64>* @in, align 32
%vecext = extractelement <4 x i64> %0, i32 0
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
%vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
store <2 x i64> %vecinit1, <2 x i64>* @out, align 16
ret i32 0
}