llvm-project/llvm/test/CodeGen/X86/pr14204.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s

define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {
; CHECK-LABEL: foo:
; CHECK:       # BB#0:
; CHECK-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; CHECK-NEXT:    vpslld $31, %ymm0, %ymm0
; CHECK-NEXT:    vpsrad $31, %ymm0, %ymm0
; CHECK-NEXT:    retq
  %s = sext <8 x i1> %bar to <8 x i32>
  ret <8 x i32> %s
}
[X86][AVX2] Removed FIXME comment and regenerated test. The comment talked about replacing vpmovzxwd+vpslld+vpsrad with vpmovsxwd - which isn't valid as we're sign extending a <8 x i1> bool vector not an all/nobits <8 x i16> llvm-svn: 292948 2017-01-25 00:56:23 +08:00			`; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py`
[x86] auto-generate checks llvm-svn: 283812 2016-10-11 06:04:12 +08:00			`; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 \| FileCheck %s`
Fix PR14204 - Add missing pattern on X86ISD::VZEXT from VR256 to VR256 when AVX2 is enabled. llvm-svn: 166947 2012-10-30 01:57:12 +08:00
			`define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {`
[x86] auto-generate checks llvm-svn: 283812 2016-10-11 06:04:12 +08:00			`; CHECK-LABEL: foo:`
			`; CHECK: # BB#0:`
			`; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero`
			`; CHECK-NEXT: vpslld $31, %ymm0, %ymm0`
			`; CHECK-NEXT: vpsrad $31, %ymm0, %ymm0`
			`; CHECK-NEXT: retq`
Fix PR14204 - Add missing pattern on X86ISD::VZEXT from VR256 to VR256 when AVX2 is enabled. llvm-svn: 166947 2012-10-30 01:57:12 +08:00			`%s = sext <8 x i1> %bar to <8 x i32>`
			`ret <8 x i32> %s`
			`}`
[x86] auto-generate checks llvm-svn: 283812 2016-10-11 06:04:12 +08:00