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llvm-project/llvm/test/CodeGen/AVR/com.ll

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[update_llc_test_checks] Support AVR Reviewed By: arichardson Differential Revision: https://reviews.llvm.org/D95240
2021-01-26 17:50:56 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=avr | FileCheck %s
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
define i8 @com8(i8 %x) {
; CHECK-LABEL: com8:
[update_llc_test_checks] Support AVR Reviewed By: arichardson Differential Revision: https://reviews.llvm.org/D95240
2021-01-26 17:50:56 +08:00
; CHECK: ; %bb.0:
; CHECK-NEXT: com r24
; CHECK-NEXT: ret
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
%neg = xor i8 %x, -1
ret i8 %neg
}
define i16 @com16(i16 %x) {
; CHECK-LABEL: com16:
[update_llc_test_checks] Support AVR Reviewed By: arichardson Differential Revision: https://reviews.llvm.org/D95240
2021-01-26 17:50:56 +08:00
; CHECK: ; %bb.0:
; CHECK-NEXT: com r24
; CHECK-NEXT: com r25
; CHECK-NEXT: ret
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
%neg = xor i16 %x, -1
ret i16 %neg
}
define i32 @com32(i32 %x) {
; CHECK-LABEL: com32:
[update_llc_test_checks] Support AVR Reviewed By: arichardson Differential Revision: https://reviews.llvm.org/D95240
2021-01-26 17:50:56 +08:00
; CHECK: ; %bb.0:
; CHECK-NEXT: com r22
; CHECK-NEXT: com r23
; CHECK-NEXT: com r24
; CHECK-NEXT: com r25
; CHECK-NEXT: ret
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
%neg = xor i32 %x, -1
ret i32 %neg
}
define i64 @com64(i64 %x) {
; CHECK-LABEL: com64:
[update_llc_test_checks] Support AVR Reviewed By: arichardson Differential Revision: https://reviews.llvm.org/D95240
2021-01-26 17:50:56 +08:00
; CHECK: ; %bb.0:
; CHECK-NEXT: com r18
; CHECK-NEXT: com r19
; CHECK-NEXT: com r20
; CHECK-NEXT: com r21
; CHECK-NEXT: com r22
; CHECK-NEXT: com r23
; CHECK-NEXT: com r24
; CHECK-NEXT: com r25
; CHECK-NEXT: ret
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
%neg = xor i64 %x, -1
ret i64 %neg
}