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llvm-project/llvm/test/CodeGen/ARM/va_arg.ll

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[ARM] Always enable UseAA in the arm backend This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
2019-11-05 18:46:56 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
2011-04-13 08:38:32 +08:00
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
When splitting a VAARG, remember its alignment. This produces terrible but correct code. llvm-svn: 106952
2010-06-27 02:22:20 +08:00
; Test that we correctly align elements when using va_arg
Fix va_arg for doubles. With this patch VAARG nodes always contain the correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
2010-07-11 12:01:49 +08:00
define i64 @test1(i32 %i, ...) nounwind optsize {
[ARM] Always enable UseAA in the arm backend This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
2019-11-05 18:46:56 +08:00
; CHECK-LABEL: test1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #12
; CHECK-NEXT: sub sp, sp, #12
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, sp, #4
; CHECK-NEXT: add r0, sp, #4
; CHECK-NEXT: stmib sp, {r1, r2, r3}
; CHECK-NEXT: add r0, r0, #7
; CHECK-NEXT: bic r1, r0, #7
[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2)) Reviewers: arsenm Subscribers: sdardis, wdng, hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, ecnelises, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81708
2020-06-04 14:01:49 +08:00
; CHECK-NEXT: orr r0, r1, #4
; CHECK-NEXT: str r0, [sp]
[ARM] Always enable UseAA in the arm backend This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
2019-11-05 18:46:56 +08:00
; CHECK-NEXT: ldr r0, [r1]
[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2)) Reviewers: arsenm Subscribers: sdardis, wdng, hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, ecnelises, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81708
2020-06-04 14:01:49 +08:00
; CHECK-NEXT: add r2, r1, #8
[ARM] Always enable UseAA in the arm backend This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
2019-11-05 18:46:56 +08:00
; CHECK-NEXT: str r2, [sp]
; CHECK-NEXT: ldr r1, [r1, #4]
; CHECK-NEXT: add sp, sp, #4
; CHECK-NEXT: add sp, sp, #12
; CHECK-NEXT: bx lr
When splitting a VAARG, remember its alignment. This produces terrible but correct code. llvm-svn: 106952
2010-06-27 02:22:20 +08:00
entry:
%g = alloca i8*, align 4
%g1 = bitcast i8** %g to i8*
call void @llvm.va_start(i8* %g1)
%0 = va_arg i8** %g, i64
call void @llvm.va_end(i8* %g1)
ret i64 %0
}
AArch64 & ARM: remove undefined behaviour from some tests. llvm-svn: 209880
2014-05-30 16:59:55 +08:00
define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
[ARM] Always enable UseAA in the arm backend This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
2019-11-05 18:46:56 +08:00
; CHECK-LABEL: test2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, sp, #8
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, sp, #4
; CHECK-NEXT: add r0, sp, #4
; CHECK-NEXT: stmib sp, {r2, r3}
; CHECK-NEXT: add r0, r0, #11
; CHECK-NEXT: bic r0, r0, #3
; CHECK-NEXT: str r2, [r1]
; CHECK-NEXT: add r1, r0, #8
; CHECK-NEXT: str r1, [sp]
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: add sp, sp, #4
; CHECK-NEXT: add sp, sp, #8
; CHECK-NEXT: bx lr
Fix va_arg for doubles. With this patch VAARG nodes always contain the correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
2010-07-11 12:01:49 +08:00
entry:
%ap = alloca i8*, align 4 ; <i8**> [#uses=3]
%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]
call void @llvm.va_start(i8* %ap1)
%0 = va_arg i8** %ap, i32 ; <i32> [#uses=0]
AArch64 & ARM: remove undefined behaviour from some tests. llvm-svn: 209880
2014-05-30 16:59:55 +08:00
store i32 %0, i32* %b
Fix va_arg for doubles. With this patch VAARG nodes always contain the correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
2010-07-11 12:01:49 +08:00
%1 = va_arg i8** %ap, double ; <double> [#uses=1]
call void @llvm.va_end(i8* %ap1)
ret double %1
}
When splitting a VAARG, remember its alignment. This produces terrible but correct code. llvm-svn: 106952
2010-06-27 02:22:20 +08:00
declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_end(i8*) nounwind