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llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

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Fix name in comments. llvm-svn: 147119
2011-12-22 09:06:53 +08:00
//===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===//
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/ARMMCTargetDesc.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "MCTargetDesc/ARMFixupKinds.h"
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCValue.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
using namespace llvm;
namespace {
class ARMELFObjectWriter : public MCELFObjectTargetWriter {
enum { DefaultEABIVersion = 0x05000000U };
unsigned GetRelocTypeInner(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const;
public:
ARMELFObjectWriter(uint8_t OSABI);
virtual ~ARMELFObjectWriter();
Make the virtual methods in ARMELFObjectWriter public. llvm-svn: 147132
2011-12-22 10:58:12 +08:00
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsPCRel, bool IsRelocWithSymbol,
int64_t Addend) const;
Make the virtual methods in ARMELFObjectWriter public. llvm-svn: 147132
2011-12-22 10:58:12 +08:00
virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
const MCValue &Target,
const MCFragment &F,
const MCFixup &Fixup,
bool IsPCRel) const;
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
};
}
ARMELFObjectWriter::ARMELFObjectWriter(uint8_t OSABI)
: MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI,
ELF::EM_ARM,
/*HasRelocationAddend*/ false) {}
ARMELFObjectWriter::~ARMELFObjectWriter() {}
// In ARM, _MergedGlobals and other most symbols get emitted directly.
// I.e. not as an offset to a section symbol.
// This code is an approximation of what ARM/gcc does.
STATISTIC(PCRelCount, "Total number of PIC Relocations");
STATISTIC(NonPCRelCount, "Total number of non-PIC relocations");
const MCSymbol *ARMELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm,
const MCValue &Target,
const MCFragment &F,
const MCFixup &Fixup,
bool IsPCRel) const {
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. Fixes PR11877 llvm-svn: 149180
2012-01-28 23:58:32 +08:00
const MCSymbol &Symbol = Target.getSymA()->getSymbol().AliasedSymbol();
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
bool EmitThisSym = false;
const MCSectionELF &Section =
static_cast<const MCSectionELF&>(Symbol.getSection());
bool InNormalSection = true;
unsigned RelocType = 0;
RelocType = GetRelocTypeInner(Target, Fixup, IsPCRel);
DEBUG(
const MCSymbolRefExpr::VariantKind Kind = Target.getSymA()->getKind();
MCSymbolRefExpr::VariantKind Kind2;
Kind2 = Target.getSymB() ? Target.getSymB()->getKind() :
MCSymbolRefExpr::VK_None;
dbgs() << "considering symbol "
<< Section.getSectionName() << "/"
<< Symbol.getName() << "/"
<< " Rel:" << (unsigned)RelocType
<< " Kind: " << (int)Kind << "/" << (int)Kind2
<< " Tmp:"
<< Symbol.isAbsolute() << "/" << Symbol.isDefined() << "/"
<< Symbol.isVariable() << "/" << Symbol.isTemporary()
<< " Counts:" << PCRelCount << "/" << NonPCRelCount << "\n");
if (IsPCRel) { ++PCRelCount;
switch (RelocType) {
default:
// Most relocation types are emitted as explicit symbols
InNormalSection =
StringSwitch<bool>(Section.getSectionName())
.Case(".data.rel.ro.local", false)
.Case(".data.rel", false)
.Case(".bss", false)
.Default(true);
EmitThisSym = true;
break;
case ELF::R_ARM_ABS32:
// But things get strange with R_ARM_ABS32
// In this case, most things that go in .rodata show up
// as section relative relocations
InNormalSection =
StringSwitch<bool>(Section.getSectionName())
.Case(".data.rel.ro.local", false)
.Case(".data.rel", false)
.Case(".rodata", false)
.Case(".bss", false)
.Default(true);
EmitThisSym = false;
break;
}
} else {
NonPCRelCount++;
InNormalSection =
StringSwitch<bool>(Section.getSectionName())
.Case(".data.rel.ro.local", false)
.Case(".rodata", false)
.Case(".data.rel", false)
.Case(".bss", false)
.Default(true);
switch (RelocType) {
default: EmitThisSym = true; break;
case ELF::R_ARM_ABS32: EmitThisSym = false; break;
Add ARM NONE and PREL31 relocation types. Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. llvm-svn: 169965
2012-12-12 15:14:46 +08:00
case ELF::R_ARM_PREL31: EmitThisSym = false; break;
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
}
}
if (EmitThisSym)
return &Symbol;
if (! Symbol.isTemporary() && InNormalSection) {
return &Symbol;
}
return NULL;
}
// Need to examine the Fixup when determining whether to
// emit the relocation as an explicit symbol or as a section relative
// offset
unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel,
bool IsRelocWithSymbol,
int64_t Addend) const {
return GetRelocTypeInner(Target, Fixup, IsPCRel);
}
unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ?
MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
unsigned Type = 0;
if (IsPCRel) {
switch ((unsigned)Fixup.getKind()) {
Convert assert(0) to llvm_unreachable llvm-svn: 149961
2012-02-07 10:50:20 +08:00
default: llvm_unreachable("Unimplemented");
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
case FK_Data_4:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
case MCSymbolRefExpr::VK_None:
Type = ELF::R_ARM_REL32;
break;
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_TLSGD:
Convert assert(0) to llvm_unreachable llvm-svn: 149961
2012-02-07 10:50:20 +08:00
llvm_unreachable("unimplemented");
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_GOTTPOFF:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_TLS_IE32;
break;
}
break;
ARM BL/BLX instruction fixups should use relocations. We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
2012-02-28 05:36:23 +08:00
case ARM::fixup_arm_blx:
Have ARM ELF use correct reloc for "b" instr. The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. llvm-svn: 158722
2012-06-20 00:03:02 +08:00
case ARM::fixup_arm_uncondbl:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
switch (Modifier) {
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_PLT:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_PLT32;
break;
ARM: support tlscall relocations This adds support for TLS CALL relocations. TLS CALL relocations are used to indicate to the linker to generate appropriate entries to resolve TLS references via an appropriate function invocation (e.g. __tls_get_addr(PLT)). In order to accomodate the linker relaxation of the TLS access model for the references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete. This requires that the partial inplace value is also incomplete (i.e. 0). We simply avoid the offset value calculation at the time of the fixup adjustment in the ARM assembler backend. llvm-svn: 200446
2014-01-30 12:02:31 +08:00
case MCSymbolRefExpr::VK_ARM_TLSCALL:
Type = ELF::R_ARM_TLS_CALL;
break;
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
default:
Type = ELF::R_ARM_CALL;
break;
}
break;
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
2012-03-30 17:15:32 +08:00
case ARM::fixup_arm_condbl:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
case ARM::fixup_arm_condbranch:
Have ARM ELF use correct reloc for "b" instr. The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. llvm-svn: 158722
2012-06-20 00:03:02 +08:00
case ARM::fixup_arm_uncondbranch:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_JUMP24;
break;
Fix Thumb2 fixup kind in the integrated-as. llvm-svn: 163063
2012-09-01 23:06:36 +08:00
case ARM::fixup_t2_condbranch:
case ARM::fixup_t2_uncondbranch:
Type = ELF::R_ARM_THM_JUMP24;
break;
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
case ARM::fixup_arm_movt_hi16:
case ARM::fixup_arm_movt_hi16_pcrel:
Type = ELF::R_ARM_MOVT_PREL;
break;
case ARM::fixup_arm_movw_lo16:
case ARM::fixup_arm_movw_lo16_pcrel:
Type = ELF::R_ARM_MOVW_PREL_NC;
break;
case ARM::fixup_t2_movt_hi16:
case ARM::fixup_t2_movt_hi16_pcrel:
Type = ELF::R_ARM_THM_MOVT_PREL;
break;
case ARM::fixup_t2_movw_lo16:
case ARM::fixup_t2_movw_lo16_pcrel:
Type = ELF::R_ARM_THM_MOVW_PREL_NC;
break;
case ARM::fixup_arm_thumb_bl:
case ARM::fixup_arm_thumb_blx:
ARM: support tlscall relocations This adds support for TLS CALL relocations. TLS CALL relocations are used to indicate to the linker to generate appropriate entries to resolve TLS references via an appropriate function invocation (e.g. __tls_get_addr(PLT)). In order to accomodate the linker relaxation of the TLS access model for the references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete. This requires that the partial inplace value is also incomplete (i.e. 0). We simply avoid the offset value calculation at the time of the fixup adjustment in the ARM assembler backend. llvm-svn: 200446
2014-01-30 12:02:31 +08:00
switch (Modifier) {
case MCSymbolRefExpr::VK_ARM_TLSCALL:
Type = ELF::R_ARM_THM_TLS_CALL;
break;
default:
Type = ELF::R_ARM_THM_CALL;
break;
}
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
break;
}
} else {
switch ((unsigned)Fixup.getKind()) {
default: llvm_unreachable("invalid fixup kind!");
case FK_Data_4:
switch (Modifier) {
More dead code removal (using -Wunreachable-code) llvm-svn: 148578
2012-01-21 05:51:11 +08:00
default: llvm_unreachable("Unsupported Modifier");
Add ARM NONE and PREL31 relocation types. Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. llvm-svn: 169965
2012-12-12 15:14:46 +08:00
case MCSymbolRefExpr::VK_ARM_NONE:
Type = ELF::R_ARM_NONE;
break;
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_GOT:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_GOT_BREL;
break;
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_TLSGD:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_TLS_GD32;
break;
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_TPOFF:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_TLS_LE32;
break;
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_GOTTPOFF:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_TLS_IE32;
break;
case MCSymbolRefExpr::VK_None:
Type = ELF::R_ARM_ABS32;
break;
Add support for parsing ARM symbol variants on ELF targets ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
2013-12-05 06:43:20 +08:00
case MCSymbolRefExpr::VK_GOTOFF:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_GOTOFF32;
break;
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
2012-01-26 17:25:43 +08:00
case MCSymbolRefExpr::VK_ARM_TARGET1:
Type = ELF::R_ARM_TARGET1;
break;
Add ARM TARGET2 relocation. The testcase will follow with actualy use-case. Based on the patch by Logan Chien! llvm-svn: 167633
2012-11-10 04:20:12 +08:00
case MCSymbolRefExpr::VK_ARM_TARGET2:
Type = ELF::R_ARM_TARGET2;
break;
Add ARM NONE and PREL31 relocation types. Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. llvm-svn: 169965
2012-12-12 15:14:46 +08:00
case MCSymbolRefExpr::VK_ARM_PREL31:
Type = ELF::R_ARM_PREL31;
break;
ARM: add tlsldo relocation Add support for the symbol(tlsldo) relocation. This is required in order to solve PR18554. Reviewed by R. Golin, A. Korobeynikov. llvm-svn: 199644
2014-01-20 19:00:40 +08:00
case MCSymbolRefExpr::VK_ARM_TLSLDO:
Type = ELF::R_ARM_TLS_LDO32;
break;
ARM: support tlscall relocations This adds support for TLS CALL relocations. TLS CALL relocations are used to indicate to the linker to generate appropriate entries to resolve TLS references via an appropriate function invocation (e.g. __tls_get_addr(PLT)). In order to accomodate the linker relaxation of the TLS access model for the references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete. This requires that the partial inplace value is also incomplete (i.e. 0). We simply avoid the offset value calculation at the time of the fixup adjustment in the ARM assembler backend. llvm-svn: 200446
2014-01-30 12:02:31 +08:00
case MCSymbolRefExpr::VK_ARM_TLSCALL:
Type = ELF::R_ARM_TLS_CALL;
break;
ARM: support TLS descriptor relocations Add support for tlsdesc relocations which are part of the ABI, marked as experimental. These relocations permit the linker to perform TLS reference optimizations. llvm-svn: 200447
2014-01-30 12:02:38 +08:00
case MCSymbolRefExpr::VK_ARM_TLSDESC:
Type = ELF::R_ARM_TLS_GOTDESC;
break;
ARM: suuport .tlsdescseq directive This enhances the ARMAsmParser to handle .tlsdescseq directives. This is a slightly special relocation. We must be able to generate them, but not consume them in assembly. The relocation is meant to assist the linker in generating a TLS descriptor sequence. The ELF target streamer is enhanced to append additional fixups into the current segment and that is used to emit the new R_ARM_TLS_DESCSEQ relocations. llvm-svn: 200448
2014-01-30 12:02:47 +08:00
case MCSymbolRefExpr::VK_ARM_TLSDESCSEQ:
Type = ELF::R_ARM_TLS_DESCSEQ;
break;
Add ARM NONE and PREL31 relocation types. Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. llvm-svn: 169965
2012-12-12 15:14:46 +08:00
}
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
break;
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_adr_pcrel_12:
case ARM::fixup_arm_thumb_bl:
case ARM::fixup_arm_thumb_cb:
case ARM::fixup_arm_thumb_cp:
case ARM::fixup_arm_thumb_br:
Convert assert(0) to llvm_unreachable llvm-svn: 149961
2012-02-07 10:50:20 +08:00
llvm_unreachable("Unimplemented");
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
case ARM::fixup_arm_condbranch:
Have ARM ELF use correct reloc for "b" instr. The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. llvm-svn: 158722
2012-06-20 00:03:02 +08:00
case ARM::fixup_arm_uncondbranch:
Move the ARM specific parts of the ELF writer to Target/ARM. llvm-svn: 147115
2011-12-22 08:37:50 +08:00
Type = ELF::R_ARM_JUMP24;
break;
case ARM::fixup_arm_movt_hi16:
Type = ELF::R_ARM_MOVT_ABS;
break;
case ARM::fixup_arm_movw_lo16:
Type = ELF::R_ARM_MOVW_ABS_NC;
break;
case ARM::fixup_t2_movt_hi16:
Type = ELF::R_ARM_THM_MOVT_ABS;
break;
case ARM::fixup_t2_movw_lo16:
Type = ELF::R_ARM_THM_MOVW_ABS_NC;
break;
}
}
return Type;
}
MCObjectWriter *llvm::createARMELFObjectWriter(raw_ostream &OS,
uint8_t OSABI) {
MCELFObjectTargetWriter *MOTW = new ARMELFObjectWriter(OSABI);
return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true);
}