2012-02-18 20:03:15 +08:00
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//===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
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2006-05-15 06:18:28 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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2006-05-15 06:18:28 +08:00
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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2007-01-19 15:51:42 +08:00
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#include "ARMMachineFunctionInfo.h"
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2011-07-21 07:34:39 +08:00
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#include "MCTargetDesc/ARMAddressingModes.h"
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2007-09-07 12:06:50 +08:00
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#include "llvm/ADT/STLExtras.h"
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2007-01-19 15:51:42 +08:00
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#include "llvm/CodeGen/LiveVariables.h"
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2008-01-05 07:57:37 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2007-01-30 07:45:17 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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2009-08-23 04:48:53 +08:00
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#include "llvm/MC/MCAsmInfo.h"
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2012-02-29 07:53:30 +08:00
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#include "llvm/MC/MCInst.h"
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2006-05-15 06:18:28 +08:00
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using namespace llvm;
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2009-06-27 05:28:53 +08:00
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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2009-11-02 08:10:38 +08:00
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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2009-06-27 05:28:53 +08:00
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}
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2006-08-09 04:35:03 +08:00
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2012-02-29 07:53:30 +08:00
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/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
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void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
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if (hasNOP()) {
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NopInst.setOpcode(ARM::NOP);
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NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::CreateReg(0));
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} else {
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NopInst.setOpcode(ARM::MOVr);
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NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
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NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
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NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::CreateReg(0));
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NopInst.addOperand(MCOperand::CreateReg(0));
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}
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}
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2009-08-02 13:20:37 +08:00
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unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
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2007-01-19 15:51:42 +08:00
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switch (Opc) {
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default: break;
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2011-08-27 04:43:14 +08:00
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case ARM::LDR_PRE_IMM:
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case ARM::LDR_PRE_REG:
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2011-07-27 04:54:26 +08:00
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case ARM::LDR_POST_IMM:
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case ARM::LDR_POST_REG:
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2010-10-27 06:37:02 +08:00
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return ARM::LDRi12;
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2007-01-19 15:51:42 +08:00
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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2011-08-27 04:43:14 +08:00
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case ARM::LDRB_PRE_IMM:
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case ARM::LDRB_PRE_REG:
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2011-07-27 04:54:26 +08:00
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case ARM::LDRB_POST_IMM:
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case ARM::LDRB_POST_REG:
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2010-10-27 08:19:44 +08:00
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return ARM::LDRBi12;
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2007-01-19 15:51:42 +08:00
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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2011-07-27 04:54:26 +08:00
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case ARM::STR_PRE_IMM:
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case ARM::STR_PRE_REG:
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case ARM::STR_POST_IMM:
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case ARM::STR_POST_REG:
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2010-10-28 07:12:14 +08:00
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return ARM::STRi12;
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2007-01-19 15:51:42 +08:00
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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2011-07-27 04:54:26 +08:00
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case ARM::STRB_PRE_IMM:
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case ARM::STRB_PRE_REG:
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case ARM::STRB_POST_IMM:
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case ARM::STRB_POST_REG:
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2010-10-28 07:12:14 +08:00
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return ARM::STRBi12;
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2006-09-13 20:09:43 +08:00
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}
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2009-07-09 00:09:28 +08:00
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2007-01-19 15:51:42 +08:00
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return 0;
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2006-05-15 06:18:28 +08:00
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}
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