2015-05-23 02:10:47 +08:00
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//===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions to allow proper scheduling, if-conversion, other late
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// optimizations, or simply the encoding of the instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86FrameLowering.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/GlobalValue.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-pseudo"
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namespace {
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class X86ExpandPseudo : public MachineFunctionPass {
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public:
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static char ID;
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X86ExpandPseudo() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const X86Subtarget *STI;
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const X86InstrInfo *TII;
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const X86RegisterInfo *TRI;
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const X86FrameLowering *X86FL;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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const char *getPassName() const override {
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return "X86 pseudo instruction expansion pass";
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}
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private:
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bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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bool ExpandMBB(MachineBasicBlock &MBB);
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};
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char X86ExpandPseudo::ID = 0;
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} // End anonymous namespace.
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/// If \p MBBI is a pseudo instruction, this method expands
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/// it to the corresponding (sequence of) actual instruction(s).
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/// \returns true if \p MBBI has been expanded.
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bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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DebugLoc DL = MBBI->getDebugLoc();
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switch (Opcode) {
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default:
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return false;
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case X86::TCRETURNdi:
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case X86::TCRETURNri:
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case X86::TCRETURNmi:
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case X86::TCRETURNdi64:
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case X86::TCRETURNri64:
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case X86::TCRETURNmi64: {
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bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
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assert(StackAdjust.isImm() && "Expecting immediate value.");
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// Adjust stack pointer.
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int StackAdj = StackAdjust.getImm();
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if (StackAdj) {
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// Check for possible merge with preceding ADD instruction.
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2015-06-19 04:22:12 +08:00
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StackAdj += X86FL->mergeSPUpdates(MBB, MBBI, true);
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X86FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);
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2015-05-23 02:10:47 +08:00
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}
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// Jump to label or value in register.
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bool IsWin64 = STI->isTargetWin64();
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if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdi64) {
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unsigned Op = (Opcode == X86::TCRETURNdi)
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? X86::TAILJMPd
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: (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
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if (JumpTarget.isGlobal())
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MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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else {
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assert(JumpTarget.isSymbol());
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MIB.addExternalSymbol(JumpTarget.getSymbolName(),
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JumpTarget.getTargetFlags());
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}
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} else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
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unsigned Op = (Opcode == X86::TCRETURNmi)
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? X86::TAILJMPm
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: (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
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for (unsigned i = 0; i != 5; ++i)
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MIB.addOperand(MBBI->getOperand(i));
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} else if (Opcode == X86::TCRETURNri64) {
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BuildMI(MBB, MBBI, DL,
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TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
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.addReg(JumpTarget.getReg(), RegState::Kill);
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} else {
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BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
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.addReg(JumpTarget.getReg(), RegState::Kill);
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}
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MachineInstr *NewMI = std::prev(MBBI);
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NewMI->copyImplicitOps(*MBBI->getParent()->getParent(), MBBI);
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// Delete the pseudo instruction TCRETURN.
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MBB.erase(MBBI);
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return true;
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}
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case X86::EH_RETURN:
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case X86::EH_RETURN64: {
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MachineOperand &DestAddr = MBBI->getOperand(0);
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assert(DestAddr.isReg() && "Offset should be in register!");
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const bool Uses64BitFramePtr =
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STI->isTarget64BitLP64() || STI->isTargetNaCl64();
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unsigned StackPtr = TRI->getStackRegister();
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BuildMI(MBB, MBBI, DL,
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TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
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.addReg(DestAddr.getReg());
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// The EH_RETURN pseudo is really removed during the MC Lowering.
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return true;
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}
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}
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llvm_unreachable("Previous switch has a fallthrough?");
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}
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/// Expand all pseudo instructions contained in \p MBB.
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/// \returns true if any expansion occurred for \p MBB.
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bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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// MBBI may be invalidated by the expansion.
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= ExpandMI(MBB, MBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
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TII = STI->getInstrInfo();
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TRI = STI->getRegisterInfo();
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X86FL = STI->getFrameLowering();
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bool Modified = false;
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for (MachineBasicBlock &MBB : MF)
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Modified |= ExpandMBB(MBB);
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return Modified;
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}
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/// Returns an instance of the pseudo instruction expansion pass.
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FunctionPass *llvm::createX86ExpandPseudoPass() {
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return new X86ExpandPseudo();
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}
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