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llvm-project/llvm/test/MachineVerifier/test_g_shuffle_vector.mir

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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
2020-02-12 15:01:35 +08:00
# RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
GlobalISel: Change representation of shuffle masks Currently shufflemasks get emitted as any other constant, and you end up with a bunch of virtual registers of G_CONSTANT with a G_BUILD_VECTOR. The AArch64 selector then asserts on anything that doesn't fit this pattern. This isn't an ideal representation, and should avoid legalization and have fewer opportunities for a representational error. Rather than invent a new shuffle mask operand type, similar to what ShuffleVectorSDNode does, just track the original IR Constant mask operand. I don't completely like the idea of adding another link to the IR, but MIR is already quite dependent on IR constants already, and this will allow sharing the shuffle mask utility functions with the IR. llvm-svn: 368704
2019-08-13 23:34:38 +08:00
# REQUIRES: aarch64-registered-target
---
name: g_shuffle_vector
tracksRegLiveness: true
liveins:
body: |
bb.0:
%0:_(<2 x s32>) = G_IMPLICIT_DEF
%1:_(<2 x s32>) = G_IMPLICIT_DEF
%2:_(<4 x s32>) = G_IMPLICIT_DEF
%3:_(s32) = G_CONSTANT i32 0
%4:_(s32) = G_CONSTANT i32 1
%5:_(<2 x s32>) = G_BUILD_VECTOR %3, %4
; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR
%6:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, %2
; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR
%7:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, %5
; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR
%8:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, 0
; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR
%9:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, i32 0
GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR llvm-svn: 368705
2019-08-13 23:52:21 +08:00
; CHECK: Bad machine code: Wrong result type for shufflemask
%10:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 2)
; CHECK: Bad machine code: Wrong result type for shufflemask
%11:_(<2 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 2, 1, 1)
; CHECK: Bad machine code: G_SHUFFLE_VECTOR cannot change element type
%12:_(<4 x s16>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 2, 1, 1)
; CHECK: Bad machine code: Source operands must be the same type
%13:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %2, shufflemask(0, 2, 1, 1)
; CHECK: Bad machine code: Out of bounds shuffle index
%14:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 2, 1, 4)
; CHECK: Bad machine code: Out of bounds shuffle index
%15:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 2, 1, 5)
%19:_(s16) = G_CONSTANT i16 0
; CHECK: Bad machine code: Source operands must be the same type
%20:_(<2 x s32>) = G_SHUFFLE_VECTOR %3, %19, shufflemask(1, 0)
; CHECK: Bad machine code: G_SHUFFLE_VECTOR cannot change element type
%21:_(s16) = G_SHUFFLE_VECTOR %3, %4, shufflemask(0)
[GlobalISel]: Fix lowering of G_SHUFFLE_VECTOR with scalar sources https://reviews.llvm.org/D66171 llvm-svn: 368753
2019-08-14 05:49:11 +08:00
; CHECK: Bad machine code: Out of bounds shuffle index
%22:_(s32) = G_IMPLICIT_DEF
%20:_(<2 x s32>) = G_SHUFFLE_VECTOR %22, %22, shufflemask(0, 2)
GlobalISel: Change representation of shuffle masks Currently shufflemasks get emitted as any other constant, and you end up with a bunch of virtual registers of G_CONSTANT with a G_BUILD_VECTOR. The AArch64 selector then asserts on anything that doesn't fit this pattern. This isn't an ideal representation, and should avoid legalization and have fewer opportunities for a representational error. Rather than invent a new shuffle mask operand type, similar to what ShuffleVectorSDNode does, just track the original IR Constant mask operand. I don't completely like the idea of adding another link to the IR, but MIR is already quite dependent on IR constants already, and this will allow sharing the shuffle mask utility functions with the IR. llvm-svn: 368704
2019-08-13 23:34:38 +08:00
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