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llvm-project/llvm/test/CodeGen/SystemZ/scalar-ctlz.ll

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[SystemZ] Improved handling of the @llvm.ctlz intrinsic. Since SystemZ supports counting of leading zeros with the FLOGR instruction, isCheapToSpeculateCtlz() should return true, which it now does. ISD::CTLZ_ZERO_UNDEF i32 is now handled the same way as ISD::CTLZ is, which is needed since promotion to i64 is required and CTLZ_ZERO_UNDEF is only expanded to CTLZ if it is Legal or Custom. Review: Ulrich Weigand https://reviews.llvm.org/D57710 llvm-svn: 353330
2019-02-07 03:23:31 +08:00
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
;
; FIXME: two consecutive immediate adds not fused in i16/i8 functions.
declare i64 @llvm.ctlz.i64(i64, i1)
declare i32 @llvm.ctlz.i32(i32, i1)
declare i16 @llvm.ctlz.i16(i16, i1)
declare i8 @llvm.ctlz.i8(i8, i1)
define i64 @f0(i64 %arg) {
; CHECK-LABEL: f0:
; CHECK-LABEL: %bb.0:
; CHECK-NOT: %bb.1:
; CHECK: flogr
%1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 false)
ret i64 %1
}
define i64 @f1(i64 %arg) {
; CHECK-LABEL: f1:
; CHECK-LABEL: %bb.0:
; CHECK-NEXT: flogr
; CHECK-NEXT: # kill
; CHECK-NEXT: br %r14
%1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 true)
ret i64 %1
}
define i32 @f2(i32 %arg) {
; CHECK-LABEL: f2:
; CHECK-LABEL: %bb.0:
; CHECK-NEXT: llgfr %r0, %r2
; CHECK-NEXT: flogr %r2, %r0
; CHECK-NEXT: aghi %r2, -32
; CHECK-NEXT: # kill
; CHECK-NEXT: br %r14
%1 = tail call i32 @llvm.ctlz.i32(i32 %arg, i1 false)
ret i32 %1
}
define i32 @f3(i32 %arg) {
; CHECK-LABEL: f3:
; CHECK-LABEL: %bb.0:
; CHECK-NEXT: llgfr %r0, %r2
; CHECK-NEXT: flogr %r2, %r0
; CHECK-NEXT: aghi %r2, -32
; CHECK-NEXT: # kill
; CHECK-NEXT: br %r14
%1 = tail call i32 @llvm.ctlz.i32(i32 %arg, i1 true)
ret i32 %1
}
define i16 @f4(i16 %arg) {
; CHECK-LABEL: f4:
; CHECK-LABEL: %bb.0:
; CHECK-NEXT: # kill
; CHECK-NEXT: llghr %r0, %r2
[SystemZ, RegAlloc] Favor 3-address instructions during instruction selection. This patch aims to reduce spilling and register moves by using the 3-address versions of instructions per default instead of the 2-address equivalent ones. It seems that both spilling and register moves are improved noticeably generally. Regalloc hints are passed to increase conversions to 2-address instructions which are done in SystemZShortenInst.cpp (after regalloc). Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are the same), foldMemoryOperandImpl() can no longer trivially fold a spilled source register since the reg/reg instruction is now 3-address. In order to remedy this, new 3-address pseudo memory instructions are used to perform the folding only when the dst and lhs virtual registers are known to be allocated to the same physreg. In order to not let MachineCopyPropagation run and change registers on these transformed instructions (making it 3-address), a new target pass called SystemZPostRewrite.cpp is run just after VirtRegRewriter, that immediately lowers the pseudo to a target instruction. If it would have been possibe to insert a COPY instruction and change a register operand (convert to 2-address) in foldMemoryOperandImpl() while trusting that the caller (e.g. InlineSpiller) would update/repair the involved LiveIntervals, the solution involving pseudo instructions would not have been needed. This is perhaps a potential improvement (see Phabricator post). Common code changes: * A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a target pass immediately before MachineCopyPropagation. * VirtRegMap is passed as an argument to foldMemoryOperand(). Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D60888 llvm-svn: 362868
2019-06-08 14:19:15 +08:00
; CHECK-NEXT: flogr %r0, %r0
; CHECK-NEXT: aghi %r0, -32
; CHECK-NEXT: ahik %r2, %r0, -16
[SystemZ] Improved handling of the @llvm.ctlz intrinsic. Since SystemZ supports counting of leading zeros with the FLOGR instruction, isCheapToSpeculateCtlz() should return true, which it now does. ISD::CTLZ_ZERO_UNDEF i32 is now handled the same way as ISD::CTLZ is, which is needed since promotion to i64 is required and CTLZ_ZERO_UNDEF is only expanded to CTLZ if it is Legal or Custom. Review: Ulrich Weigand https://reviews.llvm.org/D57710 llvm-svn: 353330
2019-02-07 03:23:31 +08:00
; CHECK-NEXT: br %r14
%1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)
ret i16 %1
}
define i16 @f5(i16 %arg) {
; CHECK-LABEL: f5:
; CHECK-LABEL: %bb.0:
; CHECK-NEXT: # kill
; CHECK-NEXT: llghr %r0, %r2
[SystemZ, RegAlloc] Favor 3-address instructions during instruction selection. This patch aims to reduce spilling and register moves by using the 3-address versions of instructions per default instead of the 2-address equivalent ones. It seems that both spilling and register moves are improved noticeably generally. Regalloc hints are passed to increase conversions to 2-address instructions which are done in SystemZShortenInst.cpp (after regalloc). Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are the same), foldMemoryOperandImpl() can no longer trivially fold a spilled source register since the reg/reg instruction is now 3-address. In order to remedy this, new 3-address pseudo memory instructions are used to perform the folding only when the dst and lhs virtual registers are known to be allocated to the same physreg. In order to not let MachineCopyPropagation run and change registers on these transformed instructions (making it 3-address), a new target pass called SystemZPostRewrite.cpp is run just after VirtRegRewriter, that immediately lowers the pseudo to a target instruction. If it would have been possibe to insert a COPY instruction and change a register operand (convert to 2-address) in foldMemoryOperandImpl() while trusting that the caller (e.g. InlineSpiller) would update/repair the involved LiveIntervals, the solution involving pseudo instructions would not have been needed. This is perhaps a potential improvement (see Phabricator post). Common code changes: * A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a target pass immediately before MachineCopyPropagation. * VirtRegMap is passed as an argument to foldMemoryOperand(). Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D60888 llvm-svn: 362868
2019-06-08 14:19:15 +08:00
; CHECK-NEXT: flogr %r0, %r0
; CHECK-NEXT: aghi %r0, -32
; CHECK-NEXT: ahik %r2, %r0, -16
[SystemZ] Improved handling of the @llvm.ctlz intrinsic. Since SystemZ supports counting of leading zeros with the FLOGR instruction, isCheapToSpeculateCtlz() should return true, which it now does. ISD::CTLZ_ZERO_UNDEF i32 is now handled the same way as ISD::CTLZ is, which is needed since promotion to i64 is required and CTLZ_ZERO_UNDEF is only expanded to CTLZ if it is Legal or Custom. Review: Ulrich Weigand https://reviews.llvm.org/D57710 llvm-svn: 353330
2019-02-07 03:23:31 +08:00
; CHECK-NEXT: br %r14
%1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 true)
ret i16 %1
}
define i8 @f6(i8 %arg) {
; CHECK-LABEL: f6:
; CHECK-LABEL: %bb.0:
; CHECK-NEXT: # kill
; CHECK-NEXT: llgcr %r0, %r2
[SystemZ, RegAlloc] Favor 3-address instructions during instruction selection. This patch aims to reduce spilling and register moves by using the 3-address versions of instructions per default instead of the 2-address equivalent ones. It seems that both spilling and register moves are improved noticeably generally. Regalloc hints are passed to increase conversions to 2-address instructions which are done in SystemZShortenInst.cpp (after regalloc). Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are the same), foldMemoryOperandImpl() can no longer trivially fold a spilled source register since the reg/reg instruction is now 3-address. In order to remedy this, new 3-address pseudo memory instructions are used to perform the folding only when the dst and lhs virtual registers are known to be allocated to the same physreg. In order to not let MachineCopyPropagation run and change registers on these transformed instructions (making it 3-address), a new target pass called SystemZPostRewrite.cpp is run just after VirtRegRewriter, that immediately lowers the pseudo to a target instruction. If it would have been possibe to insert a COPY instruction and change a register operand (convert to 2-address) in foldMemoryOperandImpl() while trusting that the caller (e.g. InlineSpiller) would update/repair the involved LiveIntervals, the solution involving pseudo instructions would not have been needed. This is perhaps a potential improvement (see Phabricator post). Common code changes: * A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a target pass immediately before MachineCopyPropagation. * VirtRegMap is passed as an argument to foldMemoryOperand(). Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D60888 llvm-svn: 362868
2019-06-08 14:19:15 +08:00
; CHECK-NEXT: flogr %r0, %r0
; CHECK-NEXT: aghi %r0, -32
; CHECK-NEXT: ahik %r2, %r0, -24
[SystemZ] Improved handling of the @llvm.ctlz intrinsic. Since SystemZ supports counting of leading zeros with the FLOGR instruction, isCheapToSpeculateCtlz() should return true, which it now does. ISD::CTLZ_ZERO_UNDEF i32 is now handled the same way as ISD::CTLZ is, which is needed since promotion to i64 is required and CTLZ_ZERO_UNDEF is only expanded to CTLZ if it is Legal or Custom. Review: Ulrich Weigand https://reviews.llvm.org/D57710 llvm-svn: 353330
2019-02-07 03:23:31 +08:00
; CHECK-NEXT: br %r14
%1 = tail call i8 @llvm.ctlz.i8(i8 %arg, i1 false)
ret i8 %1
}
define i8 @f7(i8 %arg) {
; CHECK-LABEL: f7:
; CHECK-LABEL: %bb.0:
; CHECK-NEXT: # kill
; CHECK-NEXT: llgcr %r0, %r2
[SystemZ, RegAlloc] Favor 3-address instructions during instruction selection. This patch aims to reduce spilling and register moves by using the 3-address versions of instructions per default instead of the 2-address equivalent ones. It seems that both spilling and register moves are improved noticeably generally. Regalloc hints are passed to increase conversions to 2-address instructions which are done in SystemZShortenInst.cpp (after regalloc). Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are the same), foldMemoryOperandImpl() can no longer trivially fold a spilled source register since the reg/reg instruction is now 3-address. In order to remedy this, new 3-address pseudo memory instructions are used to perform the folding only when the dst and lhs virtual registers are known to be allocated to the same physreg. In order to not let MachineCopyPropagation run and change registers on these transformed instructions (making it 3-address), a new target pass called SystemZPostRewrite.cpp is run just after VirtRegRewriter, that immediately lowers the pseudo to a target instruction. If it would have been possibe to insert a COPY instruction and change a register operand (convert to 2-address) in foldMemoryOperandImpl() while trusting that the caller (e.g. InlineSpiller) would update/repair the involved LiveIntervals, the solution involving pseudo instructions would not have been needed. This is perhaps a potential improvement (see Phabricator post). Common code changes: * A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a target pass immediately before MachineCopyPropagation. * VirtRegMap is passed as an argument to foldMemoryOperand(). Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D60888 llvm-svn: 362868
2019-06-08 14:19:15 +08:00
; CHECK-NEXT: flogr %r0, %r0
; CHECK-NEXT: aghi %r0, -32
; CHECK-NEXT: ahik %r2, %r0, -24
[SystemZ] Improved handling of the @llvm.ctlz intrinsic. Since SystemZ supports counting of leading zeros with the FLOGR instruction, isCheapToSpeculateCtlz() should return true, which it now does. ISD::CTLZ_ZERO_UNDEF i32 is now handled the same way as ISD::CTLZ is, which is needed since promotion to i64 is required and CTLZ_ZERO_UNDEF is only expanded to CTLZ if it is Legal or Custom. Review: Ulrich Weigand https://reviews.llvm.org/D57710 llvm-svn: 353330
2019-02-07 03:23:31 +08:00
; CHECK-NEXT: br %r14
%1 = tail call i8 @llvm.ctlz.i8(i8 %arg, i1 true)
ret i8 %1
}