maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/PowerPC/ppc64-dq-expr.s

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

40 lines
1.1 KiB
ArmAsm
Raw Normal View History

[PowerPC][MC] Support expressions in getMemRIX16Encoding. Loosens an assert in getMemRIX16Encoding that restricts DQ-form instructions to using an immediate, so that we can assemble instructions like lxv/stxv where the offset is an expression. Differential Revision: https://reviews.llvm.org/D51122 llvm-svn: 340761
2018-08-28 01:37:43 +08:00
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu %s -filetype=obj -o - | \
# RUN: llvm-objdump -D -r - | FileCheck %s
Test commit: add a blank line in test case ppc64-dq-expr.s llvm-svn: 355942
2019-03-13 01:33:07 +08:00
[PowerPC][MC] Support expressions in getMemRIX16Encoding. Loosens an assert in getMemRIX16Encoding that restricts DQ-form instructions to using an immediate, so that we can assemble instructions like lxv/stxv where the offset is an expression. Differential Revision: https://reviews.llvm.org/D51122 llvm-svn: 340761
2018-08-28 01:37:43 +08:00
.text
.abiversion 2
.global test
.p2align 4
.type test,@function
test:
.Lgep:
addis 2, 12, .TOC.-.Lgep@ha
addi 2, 2, .TOC.-.Lgep@l
.Llep:
.localentry test, .Llep-.Lgep
addis 3, 2, vecA@toc@ha
lxv 3, vecA@toc@l(3)
addis 3, 2, vecB@toc@ha
stxv 3, vecB@toc@l(3)
blr
.comm vecA, 16, 16
.comm vecB, 16, 16
# CHECK: Disassembly of section .text:
[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:` The new behavior matches GNU objdump. A pair of angle brackets makes tests slightly easier. `.foo:` is not unique and thus cannot be used in a `CHECK-LABEL:` directive. Without `-LABEL`, the CHECK line can match the `Disassembly of section` line and causes the next `CHECK-NEXT:` to fail. ``` Disassembly of section .foo: 0000000000001634 .foo: ``` Bdragon: <> has metalinguistic connotation. it just "feels right" Reviewed By: rupprecht Differential Revision: https://reviews.llvm.org/D75713
2020-03-06 06:18:38 +08:00
# CHECK-LABEL: <test>:
[PowerPC][MC] Support expressions in getMemRIX16Encoding. Loosens an assert in getMemRIX16Encoding that restricts DQ-form instructions to using an immediate, so that we can assemble instructions like lxv/stxv where the offset is an expression. Differential Revision: https://reviews.llvm.org/D51122 llvm-svn: 340761
2018-08-28 01:37:43 +08:00
# CHECK-NEXT: addis 2, 12, 0
# CHECK-NEXT: R_PPC64_REL16_HA .TOC.
# CHECK-NEXT: addi 2, 2, 0
# CHECK-NEXT: R_PPC64_REL16_LO .TOC.
# CHECK-NEXT: addis 3, 2, 0
# CHECK-NEXT: R_PPC64_TOC16_HA vecA
# CHECK-NEXT: lxv 3, 0(3)
# CHECK-NEXT: R_PPC64_TOC16_LO_DS vecA
# CHECK-NEXT: addis 3, 2, 0
# CHECK-NEXT: R_PPC64_TOC16_HA vecB
# CHECK-NEXT: stxv 3, 0(3)
# CHECK-NEXT: R_PPC64_TOC16_LO_DS vecB
# CHECK-NEXT: blr