maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/AArch64/neon-scalar-by-elem-mla.s

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

49 lines
2.1 KiB
ArmAsm
Raw Normal View History

[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -show-encoding < %s | FileCheck %s
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. llvm-svn: 194501
2013-11-13 03:13:08 +08:00
//------------------------------------------------------------------------------
// Floating Point fused multiply-add (scalar, by element)
//------------------------------------------------------------------------------
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
fmla h0, h1, v1.h[5]
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. llvm-svn: 194501
2013-11-13 03:13:08 +08:00
fmla s0, s1, v1.s[0]
fmla s30, s11, v1.s[1]
fmla s4, s5, v7.s[2]
fmla s16, s22, v16.s[3]
fmla d0, d1, v1.d[0]
fmla d30, d11, v1.d[1]
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// CHECK: fmla h0, h1, v1.h[5] // encoding: [0x20,0x18,0x11,0x5f]
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. llvm-svn: 194501
2013-11-13 03:13:08 +08:00
// CHECK: fmla s0, s1, v1.s[0] // encoding: [0x20,0x10,0x81,0x5f]
// CHECK: fmla s30, s11, v1.s[1] // encoding: [0x7e,0x11,0xa1,0x5f]
// CHECK: fmla s4, s5, v7.s[2] // encoding: [0xa4,0x18,0x87,0x5f]
// CHECK: fmla s16, s22, v16.s[3] // encoding: [0xd0,0x1a,0xb0,0x5f]
// CHECK: fmla d0, d1, v1.d[0] // encoding: [0x20,0x10,0xc1,0x5f]
// CHECK: fmla d30, d11, v1.d[1] // encoding: [0x7e,0x19,0xc1,0x5f]
//------------------------------------------------------------------------------
// Floating Point fused multiply-subtract (scalar, by element)
//------------------------------------------------------------------------------
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
fmls h2, h3, v4.h[5]
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. llvm-svn: 194501
2013-11-13 03:13:08 +08:00
fmls s2, s3, v4.s[0]
fmls s29, s10, v28.s[1]
fmls s5, s12, v23.s[2]
fmls s7, s17, v26.s[3]
fmls d0, d1, v1.d[0]
fmls d30, d11, v1.d[1]
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// CHECK: fmls h2, h3, v4.h[5] // encoding: [0x62,0x58,0x14,0x5f]
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. llvm-svn: 194501
2013-11-13 03:13:08 +08:00
// CHECK: fmls s2, s3, v4.s[0] // encoding: [0x62,0x50,0x84,0x5f]
// CHECK: fmls s29, s10, v28.s[1] // encoding: [0x5d,0x51,0xbc,0x5f]
// CHECK: fmls s5, s12, v23.s[2] // encoding: [0x85,0x59,0x97,0x5f]
// CHECK: fmls s7, s17, v26.s[3] // encoding: [0x27,0x5a,0xba,0x5f]
// CHECK: fmls d0, d1, v1.d[0] // encoding: [0x20,0x50,0xc1,0x5f]
// CHECK: fmls d30, d11, v1.d[1] // encoding: [0x7e,0x59,0xc1,0x5f]