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llvm-project/llvm/test/CodeGen/PowerPC/2012-10-12-bitcast.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mattr=-vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mattr=+vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s
Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCAST On PowerPC, a bitcast of <16 x i8> to i128 may run through a code path in ExpandRes_BITCAST that attempts to do an intermediate bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts of the resulting i128 by pairing up two of those i32 vector elements each. The code already recognizes that on a big-endian system, the first two vector elements form the Hi part, and the final two vector elements form the Lo part (vice-versa from the little-endian situation). However, we also need to take endianness into account when forming each of those separate pairs: on a big-endian system, vector element 0 is the *high* part of the pair making up the Hi part of the result, and vector element 1 is the low part of the pair. The code currently always uses vector element 0 as the low part and vector element 1 as the high part, as is appropriate for little-endian platforms only. This patch fixes this by swapping the vector elements as they are paired up as appropriate. llvm-svn: 165802
2012-10-12 23:42:58 +08:00
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define i32 @test(<16 x i8> %v) nounwind {
entry:
%0 = bitcast <16 x i8> %v to i128
%1 = lshr i128 %0, 96
%2 = trunc i128 %1 to i32
ret i32 %2
}
; Verify that bitcast handles big-endian platforms correctly
; by checking we load the result from the correct offset
; CHECK: addi [[REGISTER:[0-9]+]], 1, -16
; CHECK: stvx 2, 0, [[REGISTER]]
; CHECK: lwz 3, -16(1)
; CHECK: blr
[PPC] Adjust some PowerPC tests to account for presence/absence of VSX Patch by Bill Seurer; committed on his behalf. These test cases generate slightly different code sequences when VSX is activated and thus fail. The update turns off VSX explicitly for the existing checks and then adds a second set of checks for most of them that test the VSX instruction output. llvm-svn: 220019
2014-10-17 09:41:22 +08:00
; CHECK-VSX: addi [[REGISTER:[0-9]+]], 1, -16
; CHECK-VSX: stxvd2x 34, 0, [[REGISTER]]
; CHECK-VSX: lwz 3, -16(1)
; CHECK-VSX: blr