forked from OSchip/llvm-project
60 lines
1.7 KiB
LLVM
60 lines
1.7 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; DAG combiner folds sequences of shifts, which can sometimes obscure
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; optimization opportunities. For example
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;
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; unsigned int c(unsigned int b, unsigned int *a) {
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; unsigned int bitidx = b >> 5;
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; return a[bitidx];
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; }
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;
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; produces
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; (add x (shl (srl y 5) 2))
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; which is then folded into
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; (add x (and (srl y 3) 1FFFFFFC))
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;
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; That results in a constant-extended and:
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; r0 = and(##536870908,lsr(r0,#3))
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; r0 = memw(r1+r0<<#0)
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; whereas
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; r0 = lsr(r0,#5)
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; r0 = memw(r1+r0<<#2)
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; is more desirable.
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target triple = "hexagon"
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; CHECK-LABEL: load_0
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; CHECK: memw(r{{[0-9]+}}+r{{[0-9]}}<<#2)
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define i32 @load_0(i32 %b, i32* nocapture readonly %a) #0 {
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entry:
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%shr = lshr i32 %b, 5
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%arrayidx = getelementptr inbounds i32, i32* %a, i32 %shr
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%0 = load i32, i32* %arrayidx, align 4
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ret i32 %0
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}
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; This would require r0<<#3, which is not legal.
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; CHECK-LABEL: load_1
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; CHECK: memw(r{{[0-9]+}}+r{{[0-9]}}<<#0)
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define i32 @load_1(i32 %b, [3 x i32]* nocapture readonly %a) #0 {
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entry:
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%shr = lshr i32 %b, 5
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%arrayidx = getelementptr inbounds [3 x i32], [3 x i32]* %a, i32 %shr, i32 0
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%0 = load i32, i32* %arrayidx, align 4
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ret i32 %0
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}
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; CHECK-LABEL: store_0
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; CHECK: memw(r{{[0-9]+}}+r{{[0-9]}}<<#2)
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define void @store_0(i32 %b, i32* nocapture %a, i32 %v) #1 {
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entry:
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%shr = lshr i32 %b, 5
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%arrayidx = getelementptr inbounds i32, i32* %a, i32 %shr
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store i32 %v, i32* %arrayidx, align 4
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ret void
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}
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attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
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attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" }
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