2012-02-28 15:46:26 +08:00
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//===-- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
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2007-08-18 09:46:44 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-08-18 09:46:44 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-08-18 09:46:44 +08:00
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-08-18 09:46:44 +08:00
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// Functional units across Mips chips sets. Based on GCC/Mips backend files.
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-08-18 09:46:44 +08:00
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def ALU : FuncUnit;
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def IMULDIV : FuncUnit;
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2011-03-05 01:51:39 +08:00
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// Instruction Itinerary classes used for Mips
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2015-09-22 20:36:28 +08:00
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// IIM16Alu is a placeholder class for most MIPS16 instructions.
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def IIM16Alu : InstrItinClass;
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2007-08-18 09:46:44 +08:00
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def IIPseudo : InstrItinClass;
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2014-01-21 18:56:23 +08:00
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def II_ABS : InstrItinClass;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def II_ADDI : InstrItinClass;
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def II_ADDIU : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_ADDIUPC : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_ADD : InstrItinClass;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def II_ADDU : InstrItinClass;
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2014-01-21 20:38:07 +08:00
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def II_ADD_D : InstrItinClass;
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def II_ADD_S : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_ALIGN : InstrItinClass;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def II_AND : InstrItinClass;
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2014-01-16 23:57:05 +08:00
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def II_ANDI : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_ALUIPC : InstrItinClass;
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def II_AUI : InstrItinClass;
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def II_AUIPC : InstrItinClass;
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2015-09-22 21:36:28 +08:00
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def II_B : InstrItinClass;
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2014-03-20 19:51:58 +08:00
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def II_BADDU : InstrItinClass;
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2015-09-22 21:36:28 +08:00
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def II_BBIT : InstrItinClass; // bbit[01], bbit[01]32
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2016-03-11 21:05:06 +08:00
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def II_BALC : InstrItinClass;
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2015-09-22 21:36:28 +08:00
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def II_BC : InstrItinClass;
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def II_BC1F : InstrItinClass;
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def II_BC1FL : InstrItinClass;
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def II_BC1T : InstrItinClass;
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def II_BC1TL : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_BC1CCZ : InstrItinClass;
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2016-08-24 21:00:47 +08:00
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def II_BC2CCZ : InstrItinClass;
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2015-09-22 21:36:28 +08:00
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def II_BCC : InstrItinClass; // beq and bne
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def II_BCCZ : InstrItinClass; // b[gl][et]z
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2016-03-11 21:05:06 +08:00
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def II_BCCC : InstrItinClass; // b<cc>c
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2015-09-22 21:36:28 +08:00
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def II_BCCZAL : InstrItinClass; // bgezal and bltzal
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def II_BCCZALS : InstrItinClass; // bgezals and bltzals
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def II_BCCZC : InstrItinClass; // beqzc, bnezc
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2016-03-11 21:05:06 +08:00
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def II_BITSWAP : InstrItinClass;
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2014-01-21 18:56:23 +08:00
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def II_CEIL : InstrItinClass;
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2014-01-21 19:28:03 +08:00
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def II_CFC1 : InstrItinClass;
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2016-08-04 19:22:52 +08:00
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def II_CFC2 : InstrItinClass;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def II_CLO : InstrItinClass;
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def II_CLZ : InstrItinClass;
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[mips] Add support for CRC ASE
This includes
Instructions: crc32b, crc32h, crc32w, crc32d,
crc32cb, crc32ch, crc32cw, crc32cd
Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc
Attribute: crc
.MIPS.abiflags: CRC (0x8000)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44176
llvm-svn: 327511
2018-03-14 22:13:31 +08:00
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def II_CRC32B : InstrItinClass;
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def II_CRC32CB : InstrItinClass;
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def II_CRC32CD : InstrItinClass;
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def II_CRC32CH : InstrItinClass;
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def II_CRC32CW : InstrItinClass;
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def II_CRC32D : InstrItinClass;
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def II_CRC32H : InstrItinClass;
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def II_CRC32W : InstrItinClass;
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2014-01-21 19:28:03 +08:00
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def II_CTC1 : InstrItinClass;
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2016-08-04 19:22:52 +08:00
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def II_CTC2 : InstrItinClass;
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2014-01-21 18:56:23 +08:00
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def II_CVT : InstrItinClass;
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2014-01-21 19:42:48 +08:00
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def II_C_CC_D : InstrItinClass; // Any c.<cc>.d instruction
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def II_C_CC_S : InstrItinClass; // Any c.<cc>.s instruction
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2016-08-24 21:00:47 +08:00
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def II_CMP_CC_D : InstrItinClass; // Any cmp.<cc>.d instruction
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def II_CMP_CC_S : InstrItinClass; // Any cmp.<cc>.s instruction
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def II_CLASS_D : InstrItinClass;
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def II_CLASS_S : InstrItinClass;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def II_DADDIU : InstrItinClass;
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def II_DADDU : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_DADDI : InstrItinClass;
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2014-03-24 22:05:39 +08:00
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def II_DADD : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_DAHI : InstrItinClass;
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def II_DATI : InstrItinClass;
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def II_DAUI : InstrItinClass;
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def II_DALIGN : InstrItinClass;
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def II_DBITSWAP : InstrItinClass;
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def II_DCLO : InstrItinClass;
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def II_DCLZ : InstrItinClass;
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2014-01-17 22:48:06 +08:00
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def II_DDIV : InstrItinClass;
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def II_DDIVU : InstrItinClass;
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def II_DIV : InstrItinClass;
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def II_DIVU : InstrItinClass;
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2014-01-21 21:22:08 +08:00
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def II_DIV_D : InstrItinClass;
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def II_DIV_S : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_DMFC0 : InstrItinClass;
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2017-07-12 19:57:44 +08:00
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def II_DMT : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_DMTC0 : InstrItinClass;
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2014-01-21 23:03:52 +08:00
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def II_DMFC1 : InstrItinClass;
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def II_DMTC1 : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_DMOD : InstrItinClass;
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def II_DMODU : InstrItinClass;
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def II_DMUH : InstrItinClass;
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def II_DMUHU : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_DMFC2 : InstrItinClass;
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def II_DMTC2 : InstrItinClass;
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2014-03-20 19:51:58 +08:00
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def II_DMUL : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_DMULU : InstrItinClass;
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2014-01-17 22:32:41 +08:00
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def II_DMULT : InstrItinClass;
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def II_DMULTU : InstrItinClass;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def II_DROTR : InstrItinClass;
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def II_DROTR32 : InstrItinClass;
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def II_DROTRV : InstrItinClass;
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def II_DSLL : InstrItinClass;
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def II_DSLL32 : InstrItinClass;
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def II_DSLLV : InstrItinClass;
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def II_DSRA : InstrItinClass;
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def II_DSRA32 : InstrItinClass;
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def II_DSRAV : InstrItinClass;
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def II_DSRL : InstrItinClass;
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def II_DSRL32 : InstrItinClass;
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def II_DSRLV : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_DSBH : InstrItinClass;
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def II_DSHD : InstrItinClass;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def II_DSUBU : InstrItinClass;
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2014-03-24 22:05:39 +08:00
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def II_DSUB : InstrItinClass;
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2017-07-12 22:48:27 +08:00
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def II_DVPE : InstrItinClass;
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2017-07-12 19:57:44 +08:00
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def II_EMT : InstrItinClass;
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2017-07-12 22:48:27 +08:00
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def II_EVPE : InstrItinClass;
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2015-03-18 14:28:38 +08:00
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def II_EXT : InstrItinClass; // Any EXT instruction
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2014-01-21 18:56:23 +08:00
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def II_FLOOR : InstrItinClass;
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2017-07-13 00:23:57 +08:00
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def II_FORK : InstrItinClass;
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2015-03-18 14:28:38 +08:00
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def II_INS : InstrItinClass; // Any INS instruction
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2015-09-22 21:36:28 +08:00
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def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
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def II_J : InstrItinClass;
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def II_JAL : InstrItinClass;
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def II_JALR : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_JALR_HB : InstrItinClass;
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2015-09-22 21:36:28 +08:00
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def II_JALRC : InstrItinClass;
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def II_JALRS : InstrItinClass;
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def II_JALS : InstrItinClass;
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2016-03-11 21:05:06 +08:00
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def II_JIC : InstrItinClass;
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def II_JIALC : InstrItinClass;
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2015-09-22 21:36:28 +08:00
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def II_JR : InstrItinClass;
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2016-06-14 17:35:29 +08:00
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def II_JR_HB : InstrItinClass;
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2015-09-22 21:36:28 +08:00
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def II_JRADDIUSP : InstrItinClass;
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def II_JRC : InstrItinClass;
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def II_ReturnPseudo : InstrItinClass; // Return pseudo.
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2016-06-14 17:35:29 +08:00
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def II_ERET : InstrItinClass;
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def II_DERET : InstrItinClass;
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def II_ERETNC : InstrItinClass;
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def II_EHB : InstrItinClass;
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def II_SDBBP : InstrItinClass;
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def II_SSNOP : InstrItinClass;
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def II_SYSCALL : InstrItinClass;
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def II_PAUSE : InstrItinClass;
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def II_WAIT : InstrItinClass;
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def II_EI : InstrItinClass;
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def II_DI : InstrItinClass;
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|
|
|
|
def II_TEQ : InstrItinClass;
|
|
|
|
|
def II_TEQI : InstrItinClass;
|
|
|
|
|
def II_TGE : InstrItinClass;
|
|
|
|
|
def II_TGEI : InstrItinClass;
|
|
|
|
|
def II_TGEIU : InstrItinClass;
|
|
|
|
|
def II_TGEU : InstrItinClass;
|
|
|
|
|
def II_TNE : InstrItinClass;
|
|
|
|
|
def II_TNEI : InstrItinClass;
|
|
|
|
|
def II_TLT : InstrItinClass;
|
|
|
|
|
def II_TLTI : InstrItinClass;
|
|
|
|
|
def II_TLTU : InstrItinClass;
|
|
|
|
|
def II_TTLTIU : InstrItinClass;
|
|
|
|
|
def II_TLBP : InstrItinClass;
|
|
|
|
|
def II_TLBR : InstrItinClass;
|
|
|
|
|
def II_TLBWI : InstrItinClass;
|
|
|
|
|
def II_TLBWR : InstrItinClass;
|
|
|
|
|
def II_TRAP : InstrItinClass;
|
|
|
|
|
def II_BREAK : InstrItinClass;
|
|
|
|
|
def II_SYNC : InstrItinClass;
|
|
|
|
|
def II_SYNCI : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LB : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_LBE : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LBU : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_LBUE : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LD : InstrItinClass;
|
2014-01-21 21:59:56 +08:00
|
|
|
def II_LDC1 : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_LDC2 : InstrItinClass;
|
|
|
|
|
def II_LDC3 : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LDL : InstrItinClass;
|
|
|
|
|
def II_LDR : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_LDPC : InstrItinClass;
|
2014-01-21 21:59:56 +08:00
|
|
|
def II_LDXC1 : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LH : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_LHE : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LHU : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_LHUE : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_LL : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_LI : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_LLD : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_LUI : InstrItinClass;
|
2014-01-21 21:59:56 +08:00
|
|
|
def II_LUXC1 : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LW : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_LWE : InstrItinClass;
|
2014-01-21 21:59:56 +08:00
|
|
|
def II_LWC1 : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_LWC2 : InstrItinClass;
|
|
|
|
|
def II_LWC3 : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_LWM : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LWL : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_LWLE : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_LWPC : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_LWP : InstrItinClass;
|
2014-01-21 23:21:14 +08:00
|
|
|
def II_LWR : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_LWRE : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_LWU : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_LWUPC : InstrItinClass;
|
2014-01-21 21:59:56 +08:00
|
|
|
def II_LWXC1 : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_LWXS : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_LSA : InstrItinClass;
|
|
|
|
|
def II_DLSA : InstrItinClass;
|
2014-01-17 22:32:41 +08:00
|
|
|
def II_MADD : InstrItinClass;
|
|
|
|
|
def II_MADDU : InstrItinClass;
|
2014-01-21 21:07:31 +08:00
|
|
|
def II_MADD_D : InstrItinClass;
|
2014-01-21 20:51:44 +08:00
|
|
|
def II_MADD_S : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_MADDF_D : InstrItinClass;
|
|
|
|
|
def II_MADDF_S : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_MAX_D : InstrItinClass;
|
|
|
|
|
def II_MAX_S : InstrItinClass;
|
|
|
|
|
def II_MAXA_D : InstrItinClass;
|
|
|
|
|
def II_MAXA_S : InstrItinClass;
|
|
|
|
|
def II_MIN_D : InstrItinClass;
|
|
|
|
|
def II_MIN_S : InstrItinClass;
|
|
|
|
|
def II_MINA_D : InstrItinClass;
|
|
|
|
|
def II_MINA_S : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_MFC0 : InstrItinClass;
|
2016-09-01 22:53:53 +08:00
|
|
|
def II_MFHC0 : InstrItinClass;
|
2014-01-21 23:03:52 +08:00
|
|
|
def II_MFC1 : InstrItinClass;
|
|
|
|
|
def II_MFHC1 : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_MFC2 : InstrItinClass;
|
2014-01-17 22:17:34 +08:00
|
|
|
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
|
2017-11-15 06:26:42 +08:00
|
|
|
def II_MFTR : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_MOD : InstrItinClass;
|
|
|
|
|
def II_MODU : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_MOVE : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_MOVF : InstrItinClass;
|
2014-01-21 19:28:03 +08:00
|
|
|
def II_MOVF_D : InstrItinClass;
|
|
|
|
|
def II_MOVF_S : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_MOVN : InstrItinClass;
|
2014-01-21 19:28:03 +08:00
|
|
|
def II_MOVN_D : InstrItinClass;
|
|
|
|
|
def II_MOVN_S : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_MOVT : InstrItinClass;
|
2014-01-21 19:28:03 +08:00
|
|
|
def II_MOVT_D : InstrItinClass;
|
|
|
|
|
def II_MOVT_S : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_MOVZ : InstrItinClass;
|
2014-01-21 19:28:03 +08:00
|
|
|
def II_MOVZ_D : InstrItinClass;
|
|
|
|
|
def II_MOVZ_S : InstrItinClass;
|
|
|
|
|
def II_MOV_D : InstrItinClass;
|
|
|
|
|
def II_MOV_S : InstrItinClass;
|
2014-01-21 18:56:23 +08:00
|
|
|
def II_MSUB : InstrItinClass;
|
|
|
|
|
def II_MSUBU : InstrItinClass;
|
2014-01-21 21:07:31 +08:00
|
|
|
def II_MSUB_D : InstrItinClass;
|
2014-01-21 20:51:44 +08:00
|
|
|
def II_MSUB_S : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_MSUBF_D : InstrItinClass;
|
|
|
|
|
def II_MSUBF_S : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_MTC0 : InstrItinClass;
|
2016-09-01 22:53:53 +08:00
|
|
|
def II_MTHC0 : InstrItinClass;
|
2014-01-21 23:03:52 +08:00
|
|
|
def II_MTC1 : InstrItinClass;
|
|
|
|
|
def II_MTHC1 : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_MTC2 : InstrItinClass;
|
2014-01-21 18:56:23 +08:00
|
|
|
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
|
2017-11-15 06:26:42 +08:00
|
|
|
def II_MTTR : InstrItinClass;
|
2014-01-17 22:32:41 +08:00
|
|
|
def II_MUL : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_MUH : InstrItinClass;
|
|
|
|
|
def II_MUHU : InstrItinClass;
|
|
|
|
|
def II_MULU : InstrItinClass;
|
2014-01-17 22:32:41 +08:00
|
|
|
def II_MULT : InstrItinClass;
|
|
|
|
|
def II_MULTU : InstrItinClass;
|
2014-01-21 21:07:31 +08:00
|
|
|
def II_MUL_D : InstrItinClass;
|
2014-01-21 20:51:44 +08:00
|
|
|
def II_MUL_S : InstrItinClass;
|
2014-01-21 18:56:23 +08:00
|
|
|
def II_NEG : InstrItinClass;
|
2014-01-21 21:07:31 +08:00
|
|
|
def II_NMADD_D : InstrItinClass;
|
2014-01-21 20:51:44 +08:00
|
|
|
def II_NMADD_S : InstrItinClass;
|
2014-01-21 21:07:31 +08:00
|
|
|
def II_NMSUB_D : InstrItinClass;
|
2014-01-21 20:51:44 +08:00
|
|
|
def II_NMSUB_S : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_NOR : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_NOT : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_OR : InstrItinClass;
|
|
|
|
|
def II_ORI : InstrItinClass;
|
2014-03-20 19:51:58 +08:00
|
|
|
def II_POP : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_RDHWR : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_RESTORE : InstrItinClass;
|
2016-10-06 00:11:01 +08:00
|
|
|
def II_RECIP_S : InstrItinClass;
|
|
|
|
|
def II_RECIP_D : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_RINT_S : InstrItinClass;
|
|
|
|
|
def II_RINT_D : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_ROTR : InstrItinClass;
|
|
|
|
|
def II_ROTRV : InstrItinClass;
|
2014-01-21 18:56:23 +08:00
|
|
|
def II_ROUND : InstrItinClass;
|
2016-10-06 00:11:01 +08:00
|
|
|
def II_RSQRT_S : InstrItinClass;
|
|
|
|
|
def II_RSQRT_D : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SAVE : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_SC : InstrItinClass;
|
|
|
|
|
def II_SCD : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SB : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_SBE : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SD : InstrItinClass;
|
2014-01-21 22:50:20 +08:00
|
|
|
def II_SDC1 : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_SDC2 : InstrItinClass;
|
|
|
|
|
def II_SDC3 : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SDL : InstrItinClass;
|
|
|
|
|
def II_SDR : InstrItinClass;
|
2014-01-21 22:50:20 +08:00
|
|
|
def II_SDXC1 : InstrItinClass;
|
2014-01-17 00:19:38 +08:00
|
|
|
def II_SEB : InstrItinClass;
|
|
|
|
|
def II_SEH : InstrItinClass;
|
2016-03-11 21:05:06 +08:00
|
|
|
def II_SELCCZ : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_SELCCZ_D : InstrItinClass;
|
|
|
|
|
def II_SELCCZ_S : InstrItinClass;
|
2014-03-20 19:51:58 +08:00
|
|
|
def II_SEQ_SNE : InstrItinClass; // seq and sne
|
|
|
|
|
def II_SEQI_SNEI : InstrItinClass; // seqi and snei
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SH : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_SHE : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_SLL : InstrItinClass;
|
|
|
|
|
def II_SLLV : InstrItinClass;
|
2014-01-21 18:42:13 +08:00
|
|
|
def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu
|
|
|
|
|
def II_SLT_SLTU : InstrItinClass; // slt and sltu
|
2014-01-21 21:36:45 +08:00
|
|
|
def II_SQRT_D : InstrItinClass;
|
|
|
|
|
def II_SQRT_S : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_SEL_D : InstrItinClass;
|
|
|
|
|
def II_SEL_S : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_SRA : InstrItinClass;
|
|
|
|
|
def II_SRAV : InstrItinClass;
|
|
|
|
|
def II_SRL : InstrItinClass;
|
|
|
|
|
def II_SRLV : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_SUB : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_SUBU : InstrItinClass;
|
2014-01-21 20:38:07 +08:00
|
|
|
def II_SUB_D : InstrItinClass;
|
|
|
|
|
def II_SUB_S : InstrItinClass;
|
2014-01-21 22:50:20 +08:00
|
|
|
def II_SUXC1 : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SW : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_SWE : InstrItinClass;
|
2014-01-21 22:50:20 +08:00
|
|
|
def II_SWC1 : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_SWC2 : InstrItinClass;
|
|
|
|
|
def II_SWC3 : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SWL : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_SWLE : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_SWM : InstrItinClass;
|
|
|
|
|
def II_SWP : InstrItinClass;
|
2014-01-23 18:31:31 +08:00
|
|
|
def II_SWR : InstrItinClass;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
def II_SWRE : InstrItinClass;
|
2014-01-21 22:50:20 +08:00
|
|
|
def II_SWXC1 : InstrItinClass;
|
2014-01-21 18:56:23 +08:00
|
|
|
def II_TRUNC : InstrItinClass;
|
2015-09-22 18:01:13 +08:00
|
|
|
def II_WSBH : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
def II_XOR : InstrItinClass;
|
2014-01-16 23:57:05 +08:00
|
|
|
def II_XORI : InstrItinClass;
|
2016-06-14 17:35:29 +08:00
|
|
|
def II_CACHE : InstrItinClass;
|
|
|
|
|
def II_PREF : InstrItinClass;
|
|
|
|
|
def II_CACHEE : InstrItinClass;
|
|
|
|
|
def II_PREFE : InstrItinClass;
|
|
|
|
|
def II_LLE : InstrItinClass;
|
|
|
|
|
def II_SCE : InstrItinClass;
|
|
|
|
|
def II_TLBINV : InstrItinClass;
|
|
|
|
|
def II_TLBINVF : InstrItinClass;
|
2016-08-24 21:00:47 +08:00
|
|
|
def II_WRPGPR : InstrItinClass;
|
|
|
|
|
def II_RDPGPR : InstrItinClass;
|
|
|
|
|
def II_DVP : InstrItinClass;
|
|
|
|
|
def II_EVP : InstrItinClass;
|
2017-07-13 00:23:57 +08:00
|
|
|
def II_YIELD : InstrItinClass;
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-18 09:46:44 +08:00
|
|
|
// Mips Generic instruction itineraries.
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-09-29 07:50:49 +08:00
|
|
|
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
2015-09-22 20:36:28 +08:00
|
|
|
InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ALIGN , [InstrStage<1, [ALU]>]>,
|
2014-03-20 19:51:58 +08:00
|
|
|
InstrItinData<II_BADDU , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_BITSWAP , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ROTR , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SLLV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SRAV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SRLV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ROTRV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CLO , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CLZ , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DADDI , [InstrStage<1, [ALU]>]>,
|
2014-03-24 22:05:39 +08:00
|
|
|
InstrItinData<II_DADD , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_DALIGN , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DAHI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DATI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DAUI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DBITSWAP , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DMOD , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_DMODU , [InstrStage<17, [IMULDIV]>]>,
|
2017-07-12 19:57:44 +08:00
|
|
|
InstrItinData<II_DMT , [InstrStage<2, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DSLL32 , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DSRL32 , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DSRA32 , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_DSLLV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DSRLV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DSRAV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DSUBU , [InstrStage<1, [ALU]>]>,
|
2014-03-24 22:05:39 +08:00
|
|
|
InstrItinData<II_DSUB , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DROTR32 , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DSBH , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DSHD , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
|
2017-07-12 22:48:27 +08:00
|
|
|
InstrItinData<II_DVPE , [InstrStage<2, [ALU]>]>,
|
2017-07-12 19:57:44 +08:00
|
|
|
InstrItinData<II_EMT , [InstrStage<2, [ALU]>]>,
|
2017-07-12 22:48:27 +08:00
|
|
|
InstrItinData<II_EVPE , [InstrStage<2, [ALU]>]>,
|
2015-03-18 14:28:38 +08:00
|
|
|
InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
|
2017-07-13 00:23:57 +08:00
|
|
|
InstrItinData<II_FORK , [InstrStage<1, [ALU]>]>,
|
2015-03-18 14:28:38 +08:00
|
|
|
InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_MOVE , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>,
|
2014-01-21 19:28:03 +08:00
|
|
|
InstrItinData<II_MOVN_S , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVN_D , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_NOT , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_OR , [InstrStage<1, [ALU]>]>,
|
2014-03-20 19:51:58 +08:00
|
|
|
InstrItinData<II_POP , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_SUB , [InstrStage<1, [ALU]>]>,
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
InstrItinData<II_SUBU , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_XOR , [InstrStage<1, [ALU]>]>,
|
2014-01-16 23:57:05 +08:00
|
|
|
InstrItinData<II_ANDI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ORI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_XORI , [InstrStage<1, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_LB , [InstrStage<3, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_LBE , [InstrStage<3, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_LBU , [InstrStage<3, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_LBUE , [InstrStage<3, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_LH , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_LHUE , [InstrStage<3, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_LW , [InstrStage<3, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_LWM , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LWP , [InstrStage<3, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_LWPC , [InstrStage<3, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_LWLE , [InstrStage<3, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_LWR , [InstrStage<3, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_LWRE , [InstrStage<3, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_LWUPC , [InstrStage<3, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_LD , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LDR , [InstrStage<3, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_LDPC , [InstrStage<3, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_LI , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_LL , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LLD , [InstrStage<3, [ALU]>]>,
|
2014-01-21 23:21:14 +08:00
|
|
|
InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>,
|
2014-01-23 18:31:31 +08:00
|
|
|
InstrItinData<II_SB , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SH , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_SHE , [InstrStage<1, [ALU]>]>,
|
2014-01-23 18:31:31 +08:00
|
|
|
InstrItinData<II_SW , [InstrStage<1, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_SWM , [InstrStage<1, [ALU]>]>,
|
2014-01-23 18:31:31 +08:00
|
|
|
InstrItinData<II_SWL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SWR , [InstrStage<1, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_SWP , [InstrStage<1, [ALU]>]>,
|
2014-01-23 18:31:31 +08:00
|
|
|
InstrItinData<II_SDL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SD , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_SC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>,
|
2014-01-23 18:31:31 +08:00
|
|
|
InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_SELCCZ_S , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SELCCZ_D , [InstrStage<1, [ALU]>]>,
|
2014-03-20 19:51:58 +08:00
|
|
|
InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_SLTI_SLTIU , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SLT_SLTU , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_B , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_BALC , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_BBIT , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BC1F , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BC1FL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_BC1CCZ , [InstrStage<1, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_BC2CCZ , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_BCCC , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BCCZC , [InstrStage<1, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_CLASS_D , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CLASS_S , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_IndirectBranchPseudo, [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_J , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_JALR , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_JALR_HB , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_JALRC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_JALRS , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_JALS , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_JIC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_JIALC , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_JR , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_JR_HB , [InstrStage<1, [ALU]>]>,
|
2015-09-22 21:36:28 +08:00
|
|
|
InstrItinData<II_JRADDIUSP , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_JRC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ReturnPseudo , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<IIPseudo , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_DMUH , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_DMUHU , [InstrStage<17, [IMULDIV]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_ERET , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DERET , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ERETNC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_EHB , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SDBBP , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SSNOP , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SYSCALL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_WAIT , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_EI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TEQ , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TEQI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TGE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TGEI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TGEIU , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TGEU , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TNE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TNEI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLT , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLTI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLTU , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TTLTIU , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLBP , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLBR , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLBWI , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLBWR , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TRAP , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_BREAK , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SYNC , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SYNCI , [InstrStage<1, [ALU]>]>,
|
2014-03-20 19:51:58 +08:00
|
|
|
InstrItinData<II_DMUL , [InstrStage<17, [IMULDIV]>]>,
|
2014-01-17 22:32:41 +08:00
|
|
|
InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_DMULU , [InstrStage<17, [IMULDIV]>]>,
|
2014-01-17 22:32:41 +08:00
|
|
|
InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>,
|
2014-01-17 22:17:34 +08:00
|
|
|
InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_MAX_D , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MAX_S , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MAXA_D , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MAXA_S , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MIN_S , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MIN_D , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MINA_S , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MINA_D , [InstrStage<4, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_MOD , [InstrStage<38, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_MODU , [InstrStage<38, [IMULDIV]>]>,
|
2014-01-17 22:32:41 +08:00
|
|
|
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
|
2014-01-17 22:17:34 +08:00
|
|
|
InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_MUH , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_MUHU , [InstrStage<17, [IMULDIV]>]>,
|
2014-01-17 22:32:41 +08:00
|
|
|
InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_MULU , [InstrStage<17, [IMULDIV]>]>,
|
2014-01-17 22:48:06 +08:00
|
|
|
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>,
|
|
|
|
|
InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>,
|
2014-01-21 18:56:23 +08:00
|
|
|
InstrItinData<II_CEIL , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CVT , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ABS , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_FLOOR , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_NEG , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ROUND , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TRUNC , [InstrStage<1, [ALU]>]>,
|
2014-01-21 19:28:03 +08:00
|
|
|
InstrItinData<II_MOV_D , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOV_S , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CFC1 , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CTC1 , [InstrStage<2, [ALU]>]>,
|
2016-08-04 19:22:52 +08:00
|
|
|
InstrItinData<II_CFC2 , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CTC2 , [InstrStage<2, [ALU]>]>,
|
2014-01-21 19:28:03 +08:00
|
|
|
InstrItinData<II_MOVF_D , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVF_S , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVT_D , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVT_S , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVZ_D , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MOVZ_S , [InstrStage<2, [ALU]>]>,
|
2014-01-21 19:42:48 +08:00
|
|
|
InstrItinData<II_C_CC_S , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_C_CC_D , [InstrStage<3, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_CMP_CC_S , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CMP_CC_D , [InstrStage<3, [ALU]>]>,
|
2014-01-21 20:38:07 +08:00
|
|
|
InstrItinData<II_ADD_D , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_ADD_S , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SUB_D , [InstrStage<4, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SUB_S , [InstrStage<4, [ALU]>]>,
|
2014-01-21 20:51:44 +08:00
|
|
|
InstrItinData<II_MUL_S , [InstrStage<7, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MADD_S , [InstrStage<7, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_MADDF_S , [InstrStage<7, [ALU]>]>,
|
2014-01-21 20:51:44 +08:00
|
|
|
InstrItinData<II_MSUB_S , [InstrStage<7, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_MSUBF_S , [InstrStage<7, [ALU]>]>,
|
2014-01-21 20:51:44 +08:00
|
|
|
InstrItinData<II_NMADD_S , [InstrStage<7, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_NMSUB_S , [InstrStage<7, [ALU]>]>,
|
2014-01-21 21:07:31 +08:00
|
|
|
InstrItinData<II_MUL_D , [InstrStage<8, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_MADDF_D , [InstrStage<8, [ALU]>]>,
|
2014-01-21 21:07:31 +08:00
|
|
|
InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_MSUBF_D , [InstrStage<8, [ALU]>]>,
|
2014-01-21 21:07:31 +08:00
|
|
|
InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
|
2014-01-21 21:22:08 +08:00
|
|
|
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
|
2016-10-06 00:11:01 +08:00
|
|
|
InstrItinData<II_RECIP_D , [InstrStage<25, [ALU]>]>,
|
|
|
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|
InstrItinData<II_RECIP_S , [InstrStage<13, [ALU]>]>,
|
|
|
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|
InstrItinData<II_RSQRT_D , [InstrStage<29, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_RSQRT_S , [InstrStage<14, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>,
|
2014-01-21 21:36:45 +08:00
|
|
|
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_SEL_D , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SEL_S , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_WSBH , [InstrStage<1, [ALU]>]>,
|
2016-03-11 21:05:06 +08:00
|
|
|
InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DLSA , [InstrStage<1, [ALU]>]>,
|
2014-01-21 21:59:56 +08:00
|
|
|
InstrItinData<II_LDC1 , [InstrStage<3, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_LDC2 , [InstrStage<3, [ALU]>]>,
|
|
|
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|
InstrItinData<II_LDC3 , [InstrStage<3, [ALU]>]>,
|
2014-01-21 21:59:56 +08:00
|
|
|
InstrItinData<II_LWC1 , [InstrStage<3, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_LWC2 , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LWC3 , [InstrStage<3, [ALU]>]>,
|
2014-01-21 21:59:56 +08:00
|
|
|
InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>,
|
|
|
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|
InstrItinData<II_LWXC1 , [InstrStage<3, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LUXC1 , [InstrStage<3, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_LWXS , [InstrStage<3, [ALU]>]>,
|
2014-01-21 22:50:20 +08:00
|
|
|
InstrItinData<II_SDC1 , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_SDC2 , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SDC3 , [InstrStage<1, [ALU]>]>,
|
2014-01-21 22:50:20 +08:00
|
|
|
InstrItinData<II_SWC1 , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_SWC2 , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SWC3 , [InstrStage<1, [ALU]>]>,
|
2014-01-21 22:50:20 +08:00
|
|
|
InstrItinData<II_SDXC1 , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SWXC1 , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_SUXC1 , [InstrStage<1, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DMFC0 , [InstrStage<2, [ALU]>]>,
|
2014-01-21 23:03:52 +08:00
|
|
|
InstrItinData<II_DMFC1 , [InstrStage<2, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DMFC2 , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DMTC0 , [InstrStage<2, [ALU]>]>,
|
2014-01-21 23:03:52 +08:00
|
|
|
InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_DMTC2 , [InstrStage<2, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_MFC0 , [InstrStage<2, [ALU]>]>,
|
2016-09-01 22:53:53 +08:00
|
|
|
InstrItinData<II_MFHC0 , [InstrStage<2, [ALU]>]>,
|
2014-01-21 23:03:52 +08:00
|
|
|
InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>,
|
2017-11-15 06:26:42 +08:00
|
|
|
InstrItinData<II_MFTR , [InstrStage<2, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>,
|
2016-09-01 22:53:53 +08:00
|
|
|
InstrItinData<II_MTHC0 , [InstrStage<2, [ALU]>]>,
|
2014-01-21 23:03:52 +08:00
|
|
|
InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>,
|
2014-01-21 23:03:52 +08:00
|
|
|
InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]>,
|
2017-11-15 06:26:42 +08:00
|
|
|
InstrItinData<II_MTTR , [InstrStage<2, [ALU]>]>,
|
2016-06-14 17:35:29 +08:00
|
|
|
InstrItinData<II_CACHE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_PREF , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CACHEE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_PREFE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLBINV , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_TLBINVF , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_LLE , [InstrStage<3, [ALU]>]>,
|
2016-08-24 21:00:47 +08:00
|
|
|
InstrItinData<II_SCE , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_WRPGPR , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_RDPGPR , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_DVP , [InstrStage<1, [ALU]>]>,
|
2017-07-13 00:23:57 +08:00
|
|
|
InstrItinData<II_EVP , [InstrStage<1, [ALU]>]>,
|
[mips] Add support for CRC ASE
This includes
Instructions: crc32b, crc32h, crc32w, crc32d,
crc32cb, crc32ch, crc32cw, crc32cd
Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc
Attribute: crc
.MIPS.abiflags: CRC (0x8000)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44176
llvm-svn: 327511
2018-03-14 22:13:31 +08:00
|
|
|
InstrItinData<II_YIELD , [InstrStage<5, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32B , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32H , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32W , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32D , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32CB , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32CH , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32CW , [InstrStage<1, [ALU]>]>,
|
|
|
|
|
InstrItinData<II_CRC32CD , [InstrStage<1, [ALU]>]>
|
2007-08-18 09:46:44 +08:00
|
|
|
]>;
|
