2017-12-15 17:24:46 +08:00
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -verify-machineinstrs -o - | FileCheck %s
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define i32 @test1a(i32 %a, i32 %b) {
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test1a:
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r0, r0, r1
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; CHECK-NEXT: subs r1, r0, #1
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; CHECK-NEXT: sbcs r0, r1
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2017-12-15 17:24:46 +08:00
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}
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define i32 @test1b(i32 %a, i32 %b) {
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test1b:
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r1, r0, r1
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2018-11-01 05:45:48 +08:00
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; CHECK-NEXT: rsbs r0, r1, #0
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2018-02-16 17:23:59 +08:00
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; CHECK-NEXT: adcs r0, r1
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2017-12-15 17:24:46 +08:00
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}
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define i32 @test2a(i32 %a, i32 %b) {
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test2a:
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r1, r0, r1
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2018-11-01 05:45:48 +08:00
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; CHECK-NEXT: rsbs r0, r1, #0
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2018-02-16 17:23:59 +08:00
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; CHECK-NEXT: adcs r0, r1
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2017-12-15 17:24:46 +08:00
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}
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define i32 @test2b(i32 %a, i32 %b) {
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test2b:
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r0, r0, r1
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; CHECK-NEXT: subs r1, r0, #1
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; CHECK-NEXT: sbcs r0, r1
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2017-12-15 17:24:46 +08:00
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}
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define i32 @test3a(i32 %a, i32 %b) {
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = select i1 %cmp, i32 0, i32 4
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test3a:
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r0, r0, r1
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; CHECK-NEXT: subs r1, r0, #1
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; CHECK-NEXT: sbcs r0, r1
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; CHECK-NEXT: lsls r0, r0, #2
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2017-12-15 17:24:46 +08:00
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}
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define i32 @test3b(i32 %a, i32 %b) {
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = select i1 %cmp, i32 4, i32 0
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test3b:
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r0, r0, r1
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2018-11-01 05:45:48 +08:00
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; CHECK-NEXT: rsbs r1, r0, #0
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2018-02-16 17:23:59 +08:00
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; CHECK-NEXT: adcs r1, r0
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; CHECK-NEXT: lsls r0, r1, #2
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2017-12-15 17:24:46 +08:00
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}
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define i32 @test4a(i32 %a, i32 %b) {
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = select i1 %cmp, i32 0, i32 4
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test4a:
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[SelectionDAG] swap select_cc operands to enable folding
The DAGCombiner tries to SimplifySelectCC as follows:
select_cc(x, y, 16, 0, cc) -> shl(zext(set_cc(x, y, cc)), 4)
It can't cope with the situation of reordered operands:
select_cc(x, y, 0, 16, cc)
In that case we just need to swap the operands and invert the Condition Code:
select_cc(x, y, 16, 0, ~cc)
Differential Revision: https://reviews.llvm.org/D53236
llvm-svn: 346484
2018-11-09 19:09:40 +08:00
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r0, r0, r1
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; CHECK-NEXT: rsbs r1, r0, #0
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; CHECK-NEXT: adcs r1, r0
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; CHECK-NEXT: lsls r0, r1, #2
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2017-12-15 17:24:46 +08:00
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}
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define i32 @test4b(i32 %a, i32 %b) {
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = select i1 %cmp, i32 4, i32 0
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ret i32 %cond
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2018-02-16 17:23:59 +08:00
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; CHECK-LABEL: test4b:
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; CHECK-NOT: b{{(ne)|(eq)}}
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; CHECK: subs r0, r0, r1
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; CHECK-NEXT: subs r1, r0, #1
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; CHECK-NEXT: sbcs r0, r1
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; CHECK-NEXT: lsls r0, r0, #2
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2017-12-15 17:24:46 +08:00
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}
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