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llvm-project/llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll

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Revert the test moves from 176733. Use "REQUIRES: asserts" instead. llvm-svn: 176873
2013-03-13 00:27:52 +08:00
; REQUIRES: asserts
Replace more uses of sse41 with sse4.1. llc using the host cpu features and *waning* on unknown features is probably not a good thing :-( llvm-svn: 189144
2013-08-24 04:39:19 +08:00
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "4 machine-licm"
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn | FileCheck %s
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. llvm-svn: 65592
2009-02-27 08:02:22 +08:00
; rdar://6627786
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. llvm-svn: 99575
2010-03-26 08:07:25 +08:00
; rdar://7792037
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. llvm-svn: 65592
2009-02-27 08:02:22 +08:00
target triple = "x86_64-apple-darwin10.0"
%struct.Key = type { i64 }
%struct.__Rec = type opaque
%struct.__vv = type { }
Make this test less trivial, to avoid spurious failures. llvm-svn: 93156
2010-01-12 01:23:56 +08:00
define %struct.__vv* @t(%struct.Key* %desc, i64 %p) nounwind ssp {
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. llvm-svn: 65592
2009-02-27 08:02:22 +08:00
entry:
br label %bb4
bb4: ; preds = %bb.i, %bb26, %bb4, %entry
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. llvm-svn: 99575
2010-03-26 08:07:25 +08:00
; CHECK: %bb4
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; CHECK: xorl
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. llvm-svn: 99575
2010-03-26 08:07:25 +08:00
; CHECK: callq
; CHECK: xorl
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; CHECK: xorl
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; CHECK: movq
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. llvm-svn: 99575
2010-03-26 08:07:25 +08:00
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. llvm-svn: 65592
2009-02-27 08:02:22 +08:00
%0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0]
Make this test less trivial, to avoid spurious failures. llvm-svn: 93156
2010-01-12 01:23:56 +08:00
%ins = or i64 %p, 2097152 ; <i64> [#uses=1]
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. llvm-svn: 65592
2009-02-27 08:02:22 +08:00
%1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind ; <i32> [#uses=1]
%cond = icmp eq i32 %1, 1 ; <i1> [#uses=1]
br i1 %cond, label %bb26, label %bb4
bb26: ; preds = %bb4
%2 = and i64 %ins, 15728640 ; <i64> [#uses=1]
%cond.i = icmp eq i64 %2, 1048576 ; <i1> [#uses=1]
br i1 %cond.i, label %bb.i, label %bb4
bb.i: ; preds = %bb26
%3 = load i32* null, align 4 ; <i32> [#uses=1]
%4 = uitofp i32 %3 to float ; <float> [#uses=1]
%.sum13.i = add i64 0, 4 ; <i64> [#uses=1]
%5 = getelementptr i8* null, i64 %.sum13.i ; <i8*> [#uses=1]
%6 = bitcast i8* %5 to i32* ; <i32*> [#uses=1]
%7 = load i32* %6, align 4 ; <i32> [#uses=1]
%8 = uitofp i32 %7 to float ; <float> [#uses=1]
%.sum.i = add i64 0, 8 ; <i64> [#uses=1]
%9 = getelementptr i8* null, i64 %.sum.i ; <i8*> [#uses=1]
%10 = bitcast i8* %9 to i32* ; <i32*> [#uses=1]
%11 = load i32* %10, align 4 ; <i32> [#uses=1]
%12 = uitofp i32 %11 to float ; <float> [#uses=1]
%13 = insertelement <4 x float> undef, float %4, i32 0 ; <<4 x float>> [#uses=1]
%14 = insertelement <4 x float> %13, float %8, i32 1 ; <<4 x float>> [#uses=1]
%15 = insertelement <4 x float> %14, float %12, i32 2 ; <<4 x float>> [#uses=1]
store <4 x float> %15, <4 x float>* null, align 16
br label %bb4
}
declare i32 @xxGetOffsetForCode(...)
declare i32 @xxCalculateMidType(...)