2017-08-25 05:21:39 +08:00
|
|
|
//===- LiveDebugValues.cpp - Tracking Debug Value MIs ---------------------===//
|
2015-12-16 19:09:48 +08:00
|
|
|
//
|
2019-01-19 16:50:56 +08:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2015-12-16 19:09:48 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
///
|
|
|
|
/// This pass implements a data flow analysis that propagates debug location
|
|
|
|
/// information by inserting additional DBG_VALUE instructions into the machine
|
|
|
|
/// instruction stream. The pass internally builds debug location liveness
|
|
|
|
/// ranges to determine the points where additional DBG_VALUEs need to be
|
|
|
|
/// inserted.
|
|
|
|
///
|
|
|
|
/// This is a separate pass from DbgValueHistoryCalculator to facilitate
|
|
|
|
/// testing and improve modularity.
|
|
|
|
///
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
#include "llvm/ADT/DenseMap.h"
|
2016-01-11 02:08:32 +08:00
|
|
|
#include "llvm/ADT/PostOrderIterator.h"
|
|
|
|
#include "llvm/ADT/SmallPtrSet.h"
|
2017-08-25 05:21:39 +08:00
|
|
|
#include "llvm/ADT/SmallVector.h"
|
2016-05-26 06:21:12 +08:00
|
|
|
#include "llvm/ADT/SparseBitVector.h"
|
2016-04-18 17:17:29 +08:00
|
|
|
#include "llvm/ADT/Statistic.h"
|
2016-05-26 06:21:12 +08:00
|
|
|
#include "llvm/ADT/UniqueVector.h"
|
2016-09-29 01:51:14 +08:00
|
|
|
#include "llvm/CodeGen/LexicalScopes.h"
|
2017-08-25 05:21:39 +08:00
|
|
|
#include "llvm/CodeGen/MachineBasicBlock.h"
|
2017-02-15 03:08:45 +08:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2015-12-16 19:09:48 +08:00
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
|
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
2017-08-25 05:21:39 +08:00
|
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
2015-12-16 19:09:48 +08:00
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
2017-02-15 03:08:45 +08:00
|
|
|
#include "llvm/CodeGen/MachineMemOperand.h"
|
2017-08-25 05:21:39 +08:00
|
|
|
#include "llvm/CodeGen/MachineOperand.h"
|
|
|
|
#include "llvm/CodeGen/PseudoSourceValue.h"
|
2019-01-31 02:34:07 +08:00
|
|
|
#include "llvm/CodeGen/RegisterScavenging.h"
|
2017-11-08 09:01:31 +08:00
|
|
|
#include "llvm/CodeGen/TargetFrameLowering.h"
|
|
|
|
#include "llvm/CodeGen/TargetInstrInfo.h"
|
2017-11-17 09:07:10 +08:00
|
|
|
#include "llvm/CodeGen/TargetLowering.h"
|
|
|
|
#include "llvm/CodeGen/TargetRegisterInfo.h"
|
|
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
2018-04-30 22:59:11 +08:00
|
|
|
#include "llvm/Config/llvm-config.h"
|
2019-01-31 02:34:07 +08:00
|
|
|
#include "llvm/IR/DIBuilder.h"
|
2017-08-25 05:21:39 +08:00
|
|
|
#include "llvm/IR/DebugInfoMetadata.h"
|
|
|
|
#include "llvm/IR/DebugLoc.h"
|
|
|
|
#include "llvm/IR/Function.h"
|
|
|
|
#include "llvm/IR/Module.h"
|
|
|
|
#include "llvm/MC/MCRegisterInfo.h"
|
|
|
|
#include "llvm/Pass.h"
|
|
|
|
#include "llvm/Support/Casting.h"
|
|
|
|
#include "llvm/Support/Compiler.h"
|
2015-12-16 19:09:48 +08:00
|
|
|
#include "llvm/Support/Debug.h"
|
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2017-08-25 05:21:39 +08:00
|
|
|
#include <algorithm>
|
|
|
|
#include <cassert>
|
|
|
|
#include <cstdint>
|
|
|
|
#include <functional>
|
2016-04-18 17:17:29 +08:00
|
|
|
#include <queue>
|
2017-08-25 05:21:39 +08:00
|
|
|
#include <utility>
|
|
|
|
#include <vector>
|
2015-12-16 19:09:48 +08:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2017-05-26 05:26:32 +08:00
|
|
|
#define DEBUG_TYPE "livedebugvalues"
|
2015-12-16 19:09:48 +08:00
|
|
|
|
|
|
|
STATISTIC(NumInserted, "Number of DBG_VALUE instructions inserted");
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
// If @MI is a DBG_VALUE with debug value described by a defined
|
2016-05-26 06:21:12 +08:00
|
|
|
// register, returns the number of this register. In the other case, returns 0.
|
2016-05-26 06:37:29 +08:00
|
|
|
static unsigned isDbgValueDescribedByReg(const MachineInstr &MI) {
|
2016-05-26 06:21:12 +08:00
|
|
|
assert(MI.isDebugValue() && "expected a DBG_VALUE");
|
|
|
|
assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE");
|
|
|
|
// If location of variable is described using a register (directly
|
|
|
|
// or indirectly), this register is always a first operand.
|
|
|
|
return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
|
|
|
|
}
|
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
namespace {
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
class LiveDebugValues : public MachineFunctionPass {
|
2015-12-16 19:09:48 +08:00
|
|
|
private:
|
|
|
|
const TargetRegisterInfo *TRI;
|
|
|
|
const TargetInstrInfo *TII;
|
2017-02-15 03:08:45 +08:00
|
|
|
const TargetFrameLowering *TFI;
|
2018-07-13 16:24:26 +08:00
|
|
|
BitVector CalleeSavedRegs;
|
2016-09-29 01:51:14 +08:00
|
|
|
LexicalScopes LS;
|
|
|
|
|
2019-01-31 02:34:07 +08:00
|
|
|
enum struct TransferKind { TransferCopy, TransferSpill, TransferRestore };
|
|
|
|
|
2016-09-29 01:51:14 +08:00
|
|
|
/// Keeps track of lexical scopes associated with a user value's source
|
|
|
|
/// location.
|
|
|
|
class UserValueScopes {
|
|
|
|
DebugLoc DL;
|
|
|
|
LexicalScopes &LS;
|
|
|
|
SmallPtrSet<const MachineBasicBlock *, 4> LBlocks;
|
|
|
|
|
|
|
|
public:
|
|
|
|
UserValueScopes(DebugLoc D, LexicalScopes &L) : DL(std::move(D)), LS(L) {}
|
|
|
|
|
|
|
|
/// Return true if current scope dominates at least one machine
|
|
|
|
/// instruction in a given machine basic block.
|
|
|
|
bool dominates(MachineBasicBlock *MBB) {
|
|
|
|
if (LBlocks.empty())
|
|
|
|
LS.getMachineBasicBlocks(DL, LBlocks);
|
|
|
|
return LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB);
|
|
|
|
}
|
|
|
|
};
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-27 05:42:47 +08:00
|
|
|
/// Based on std::pair so it can be used as an index into a DenseMap.
|
2017-08-25 05:21:39 +08:00
|
|
|
using DebugVariableBase =
|
|
|
|
std::pair<const DILocalVariable *, const DILocation *>;
|
2015-12-16 19:09:48 +08:00
|
|
|
/// A potentially inlined instance of a variable.
|
2016-05-27 05:42:47 +08:00
|
|
|
struct DebugVariable : public DebugVariableBase {
|
|
|
|
DebugVariable(const DILocalVariable *Var, const DILocation *InlinedAt)
|
|
|
|
: DebugVariableBase(Var, InlinedAt) {}
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
const DILocalVariable *getVar() const { return this->first; }
|
|
|
|
const DILocation *getInlinedAt() const { return this->second; }
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
bool operator<(const DebugVariable &DV) const {
|
2016-05-27 05:42:47 +08:00
|
|
|
if (getVar() == DV.getVar())
|
|
|
|
return getInlinedAt() < DV.getInlinedAt();
|
|
|
|
return getVar() < DV.getVar();
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
/// A pair of debug variable and value location.
|
2015-12-16 19:09:48 +08:00
|
|
|
struct VarLoc {
|
2019-01-31 02:34:07 +08:00
|
|
|
// The location at which a spilled variable resides. It consists of a
|
|
|
|
// register and an offset.
|
|
|
|
struct SpillLoc {
|
|
|
|
unsigned SpillBase;
|
|
|
|
int SpillOffset;
|
|
|
|
bool operator==(const SpillLoc &Other) const {
|
|
|
|
return SpillBase == Other.SpillBase && SpillOffset == Other.SpillOffset;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
const DebugVariable Var;
|
|
|
|
const MachineInstr &MI; ///< Only used for cloning a new DBG_VALUE.
|
2016-09-29 01:51:14 +08:00
|
|
|
mutable UserValueScopes UVS;
|
2019-01-31 02:34:07 +08:00
|
|
|
enum VarLocKind {
|
|
|
|
InvalidKind = 0,
|
|
|
|
RegisterKind,
|
|
|
|
SpillLocKind
|
|
|
|
} Kind = InvalidKind;
|
2016-05-26 06:21:12 +08:00
|
|
|
|
|
|
|
/// The value location. Stored separately to avoid repeatedly
|
|
|
|
/// extracting it from MI.
|
|
|
|
union {
|
2017-07-29 07:25:51 +08:00
|
|
|
uint64_t RegNo;
|
2019-01-31 02:34:07 +08:00
|
|
|
SpillLoc SpillLocation;
|
2016-05-26 06:21:12 +08:00
|
|
|
uint64_t Hash;
|
|
|
|
} Loc;
|
|
|
|
|
2016-09-29 01:51:14 +08:00
|
|
|
VarLoc(const MachineInstr &MI, LexicalScopes &LS)
|
2016-05-26 06:21:12 +08:00
|
|
|
: Var(MI.getDebugVariable(), MI.getDebugLoc()->getInlinedAt()), MI(MI),
|
2017-08-25 05:21:39 +08:00
|
|
|
UVS(MI.getDebugLoc(), LS) {
|
2016-05-26 06:21:12 +08:00
|
|
|
static_assert((sizeof(Loc) == sizeof(uint64_t)),
|
|
|
|
"hash does not cover all members of Loc");
|
|
|
|
assert(MI.isDebugValue() && "not a DBG_VALUE");
|
|
|
|
assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE");
|
2016-05-26 06:37:29 +08:00
|
|
|
if (int RegNo = isDbgValueDescribedByReg(MI)) {
|
2016-05-26 06:21:12 +08:00
|
|
|
Kind = RegisterKind;
|
2017-07-29 07:25:51 +08:00
|
|
|
Loc.RegNo = RegNo;
|
2016-05-26 06:21:12 +08:00
|
|
|
}
|
|
|
|
}
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2019-01-31 02:34:07 +08:00
|
|
|
/// The constructor for spill locations.
|
|
|
|
VarLoc(const MachineInstr &MI, unsigned SpillBase, int SpillOffset,
|
|
|
|
LexicalScopes &LS)
|
|
|
|
: Var(MI.getDebugVariable(), MI.getDebugLoc()->getInlinedAt()), MI(MI),
|
|
|
|
UVS(MI.getDebugLoc(), LS) {
|
|
|
|
assert(MI.isDebugValue() && "not a DBG_VALUE");
|
|
|
|
assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE");
|
|
|
|
Kind = SpillLocKind;
|
|
|
|
Loc.SpillLocation = {SpillBase, SpillOffset};
|
|
|
|
}
|
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
/// If this variable is described by a register, return it,
|
|
|
|
/// otherwise return 0.
|
|
|
|
unsigned isDescribedByReg() const {
|
|
|
|
if (Kind == RegisterKind)
|
2017-07-29 07:25:51 +08:00
|
|
|
return Loc.RegNo;
|
2016-05-26 06:21:12 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-09-29 01:51:14 +08:00
|
|
|
/// Determine whether the lexical scope of this value's debug location
|
|
|
|
/// dominates MBB.
|
|
|
|
bool dominates(MachineBasicBlock &MBB) const { return UVS.dominates(&MBB); }
|
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2017-01-28 14:53:55 +08:00
|
|
|
LLVM_DUMP_METHOD void dump() const { MI.dump(); }
|
|
|
|
#endif
|
2016-05-26 06:21:12 +08:00
|
|
|
|
|
|
|
bool operator==(const VarLoc &Other) const {
|
|
|
|
return Var == Other.Var && Loc.Hash == Other.Loc.Hash;
|
|
|
|
}
|
|
|
|
|
2016-05-27 05:42:47 +08:00
|
|
|
/// This operator guarantees that VarLocs are sorted by Variable first.
|
2016-05-26 06:21:12 +08:00
|
|
|
bool operator<(const VarLoc &Other) const {
|
|
|
|
if (Var == Other.Var)
|
|
|
|
return Loc.Hash < Other.Loc.Hash;
|
|
|
|
return Var < Other.Var;
|
|
|
|
}
|
2015-12-16 19:09:48 +08:00
|
|
|
};
|
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
using VarLocMap = UniqueVector<VarLoc>;
|
|
|
|
using VarLocSet = SparseBitVector<>;
|
|
|
|
using VarLocInMBB = SmallDenseMap<const MachineBasicBlock *, VarLocSet>;
|
2018-07-13 16:24:26 +08:00
|
|
|
struct TransferDebugPair {
|
|
|
|
MachineInstr *TransferInst;
|
2017-02-15 03:08:45 +08:00
|
|
|
MachineInstr *DebugInst;
|
|
|
|
};
|
2018-07-13 16:24:26 +08:00
|
|
|
using TransferMap = SmallVector<TransferDebugPair, 4>;
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-27 05:42:47 +08:00
|
|
|
/// This holds the working set of currently open ranges. For fast
|
|
|
|
/// access, this is done both as a set of VarLocIDs, and a map of
|
|
|
|
/// DebugVariable to recent VarLocID. Note that a DBG_VALUE ends all
|
|
|
|
/// previous open ranges for the same variable.
|
|
|
|
class OpenRangesSet {
|
|
|
|
VarLocSet VarLocs;
|
|
|
|
SmallDenseMap<DebugVariableBase, unsigned, 8> Vars;
|
|
|
|
|
|
|
|
public:
|
|
|
|
const VarLocSet &getVarLocs() const { return VarLocs; }
|
|
|
|
|
|
|
|
/// Terminate all open ranges for Var by removing it from the set.
|
|
|
|
void erase(DebugVariable Var) {
|
|
|
|
auto It = Vars.find(Var);
|
|
|
|
if (It != Vars.end()) {
|
|
|
|
unsigned ID = It->second;
|
|
|
|
VarLocs.reset(ID);
|
|
|
|
Vars.erase(It);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Terminate all open ranges listed in \c KillSet by removing
|
|
|
|
/// them from the set.
|
|
|
|
void erase(const VarLocSet &KillSet, const VarLocMap &VarLocIDs) {
|
|
|
|
VarLocs.intersectWithComplement(KillSet);
|
|
|
|
for (unsigned ID : KillSet)
|
|
|
|
Vars.erase(VarLocIDs[ID].Var);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Insert a new range into the set.
|
|
|
|
void insert(unsigned VarLocID, DebugVariableBase Var) {
|
|
|
|
VarLocs.set(VarLocID);
|
|
|
|
Vars.insert({Var, VarLocID});
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Empty the set.
|
|
|
|
void clear() {
|
|
|
|
VarLocs.clear();
|
|
|
|
Vars.clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Return whether the set is empty or not.
|
|
|
|
bool empty() const {
|
|
|
|
assert(Vars.empty() == VarLocs.empty() && "open ranges are inconsistent");
|
|
|
|
return VarLocs.empty();
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2017-02-15 03:08:45 +08:00
|
|
|
bool isSpillInstruction(const MachineInstr &MI, MachineFunction *MF,
|
|
|
|
unsigned &Reg);
|
2019-01-31 02:34:07 +08:00
|
|
|
/// If a given instruction is identified as a spill, return the spill location
|
|
|
|
/// and set \p Reg to the spilled register.
|
|
|
|
Optional<VarLoc::SpillLoc> isRestoreInstruction(const MachineInstr &MI,
|
|
|
|
MachineFunction *MF,
|
|
|
|
unsigned &Reg);
|
|
|
|
/// Given a spill instruction, extract the register and offset used to
|
|
|
|
/// address the spill location in a target independent way.
|
|
|
|
VarLoc::SpillLoc extractSpillBaseRegAndOffset(const MachineInstr &MI);
|
2018-07-13 16:24:26 +08:00
|
|
|
void insertTransferDebugPair(MachineInstr &MI, OpenRangesSet &OpenRanges,
|
|
|
|
TransferMap &Transfers, VarLocMap &VarLocIDs,
|
2019-01-31 02:34:07 +08:00
|
|
|
unsigned OldVarID, TransferKind Kind,
|
|
|
|
unsigned NewReg = 0);
|
2017-02-15 03:08:45 +08:00
|
|
|
|
2016-05-27 05:42:47 +08:00
|
|
|
void transferDebugValue(const MachineInstr &MI, OpenRangesSet &OpenRanges,
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocMap &VarLocIDs);
|
2019-01-31 02:34:07 +08:00
|
|
|
void transferSpillOrRestoreInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
|
|
|
|
VarLocMap &VarLocIDs, TransferMap &Transfers);
|
2018-07-13 16:24:26 +08:00
|
|
|
void transferRegisterCopy(MachineInstr &MI, OpenRangesSet &OpenRanges,
|
|
|
|
VarLocMap &VarLocIDs, TransferMap &Transfers);
|
2016-05-27 05:42:47 +08:00
|
|
|
void transferRegisterDef(MachineInstr &MI, OpenRangesSet &OpenRanges,
|
2016-05-26 06:21:12 +08:00
|
|
|
const VarLocMap &VarLocIDs);
|
2016-05-27 05:42:47 +08:00
|
|
|
bool transferTerminatorInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocInMBB &OutLocs, const VarLocMap &VarLocIDs);
|
2018-07-13 16:24:26 +08:00
|
|
|
bool process(MachineInstr &MI, OpenRangesSet &OpenRanges,
|
|
|
|
VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
|
|
|
|
TransferMap &Transfers, bool transferChanges);
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
bool join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
|
2016-09-28 00:46:07 +08:00
|
|
|
const VarLocMap &VarLocIDs,
|
2018-10-06 05:44:15 +08:00
|
|
|
SmallPtrSet<const MachineBasicBlock *, 16> &Visited,
|
|
|
|
SmallPtrSetImpl<const MachineBasicBlock *> &ArtificialBlocks);
|
2015-12-16 19:09:48 +08:00
|
|
|
|
|
|
|
bool ExtendRanges(MachineFunction &MF);
|
|
|
|
|
|
|
|
public:
|
|
|
|
static char ID;
|
|
|
|
|
|
|
|
/// Default construct and initialize the pass.
|
|
|
|
LiveDebugValues();
|
|
|
|
|
|
|
|
/// Tell the pass manager which passes we depend on and what
|
|
|
|
/// information we preserve.
|
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
|
|
|
|
2016-03-29 01:05:30 +08:00
|
|
|
MachineFunctionProperties getRequiredProperties() const override {
|
|
|
|
return MachineFunctionProperties().set(
|
2016-08-25 09:27:13 +08:00
|
|
|
MachineFunctionProperties::Property::NoVRegs);
|
2016-03-29 01:05:30 +08:00
|
|
|
}
|
|
|
|
|
2015-12-16 19:09:48 +08:00
|
|
|
/// Print to ostream with a message.
|
2016-05-26 06:21:12 +08:00
|
|
|
void printVarLocInMBB(const MachineFunction &MF, const VarLocInMBB &V,
|
|
|
|
const VarLocMap &VarLocIDs, const char *msg,
|
2015-12-16 19:09:48 +08:00
|
|
|
raw_ostream &Out) const;
|
|
|
|
|
|
|
|
/// Calculate the liveness information for the given machine function.
|
|
|
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
|
|
|
};
|
2016-09-29 01:51:14 +08:00
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
} // end anonymous namespace
|
2015-12-16 19:09:48 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
char LiveDebugValues::ID = 0;
|
2017-08-25 05:21:39 +08:00
|
|
|
|
2015-12-16 19:09:48 +08:00
|
|
|
char &llvm::LiveDebugValuesID = LiveDebugValues::ID;
|
2017-08-25 05:21:39 +08:00
|
|
|
|
2017-05-26 05:26:32 +08:00
|
|
|
INITIALIZE_PASS(LiveDebugValues, DEBUG_TYPE, "Live DEBUG_VALUE analysis",
|
2015-12-16 19:09:48 +08:00
|
|
|
false, false)
|
|
|
|
|
|
|
|
/// Default construct and initialize the pass.
|
|
|
|
LiveDebugValues::LiveDebugValues() : MachineFunctionPass(ID) {
|
|
|
|
initializeLiveDebugValuesPass(*PassRegistry::getPassRegistry());
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Tell the pass manager which passes we depend on and what information we
|
|
|
|
/// preserve.
|
|
|
|
void LiveDebugValues::getAnalysisUsage(AnalysisUsage &AU) const {
|
2016-06-08 13:18:01 +08:00
|
|
|
AU.setPreservesCFG();
|
2015-12-16 19:09:48 +08:00
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Debug Range Extension Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2017-01-28 14:53:55 +08:00
|
|
|
#ifndef NDEBUG
|
2016-05-26 06:21:12 +08:00
|
|
|
void LiveDebugValues::printVarLocInMBB(const MachineFunction &MF,
|
|
|
|
const VarLocInMBB &V,
|
|
|
|
const VarLocMap &VarLocIDs,
|
|
|
|
const char *msg,
|
2015-12-16 19:09:48 +08:00
|
|
|
raw_ostream &Out) const {
|
2016-09-21 00:04:31 +08:00
|
|
|
Out << '\n' << msg << '\n';
|
2016-05-26 06:21:12 +08:00
|
|
|
for (const MachineBasicBlock &BB : MF) {
|
2018-10-06 05:44:00 +08:00
|
|
|
const VarLocSet &L = V.lookup(&BB);
|
|
|
|
if (L.empty())
|
|
|
|
continue;
|
|
|
|
Out << "MBB: " << BB.getNumber() << ":\n";
|
2016-05-26 06:21:12 +08:00
|
|
|
for (unsigned VLL : L) {
|
|
|
|
const VarLoc &VL = VarLocIDs[VLL];
|
2016-05-27 05:42:47 +08:00
|
|
|
Out << " Var: " << VL.Var.getVar()->getName();
|
2015-12-16 19:09:48 +08:00
|
|
|
Out << " MI: ";
|
2016-05-26 06:21:12 +08:00
|
|
|
VL.dump();
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
Out << "\n";
|
|
|
|
}
|
2017-01-28 14:53:55 +08:00
|
|
|
#endif
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2019-01-31 02:34:07 +08:00
|
|
|
LiveDebugValues::VarLoc::SpillLoc
|
|
|
|
LiveDebugValues::extractSpillBaseRegAndOffset(const MachineInstr &MI) {
|
2018-07-31 03:41:25 +08:00
|
|
|
assert(MI.hasOneMemOperand() &&
|
2017-02-15 03:08:45 +08:00
|
|
|
"Spill instruction does not have exactly one memory operand?");
|
|
|
|
auto MMOI = MI.memoperands_begin();
|
|
|
|
const PseudoSourceValue *PVal = (*MMOI)->getPseudoValue();
|
|
|
|
assert(PVal->kind() == PseudoSourceValue::FixedStack &&
|
|
|
|
"Inconsistent memory operand in spill instruction");
|
|
|
|
int FI = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
|
|
|
|
const MachineBasicBlock *MBB = MI.getParent();
|
2019-01-31 02:34:07 +08:00
|
|
|
unsigned Reg;
|
|
|
|
int Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg);
|
|
|
|
return {Reg, Offset};
|
2017-02-15 03:08:45 +08:00
|
|
|
}
|
|
|
|
|
2015-12-16 19:09:48 +08:00
|
|
|
/// End all previous ranges related to @MI and start a new range from @MI
|
|
|
|
/// if it is a DBG_VALUE instr.
|
2016-05-26 06:21:12 +08:00
|
|
|
void LiveDebugValues::transferDebugValue(const MachineInstr &MI,
|
2016-05-27 05:42:47 +08:00
|
|
|
OpenRangesSet &OpenRanges,
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocMap &VarLocIDs) {
|
2015-12-16 19:09:48 +08:00
|
|
|
if (!MI.isDebugValue())
|
|
|
|
return;
|
2016-05-26 06:21:12 +08:00
|
|
|
const DILocalVariable *Var = MI.getDebugVariable();
|
|
|
|
const DILocation *DebugLoc = MI.getDebugLoc();
|
|
|
|
const DILocation *InlinedAt = DebugLoc->getInlinedAt();
|
|
|
|
assert(Var->isValidLocationForIntrinsic(DebugLoc) &&
|
2015-12-16 19:09:48 +08:00
|
|
|
"Expected inlined-at fields to agree");
|
|
|
|
|
|
|
|
// End all previous ranges of Var.
|
2016-05-27 05:42:47 +08:00
|
|
|
DebugVariable V(Var, InlinedAt);
|
|
|
|
OpenRanges.erase(V);
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
// Add the VarLoc to OpenRanges from this DBG_VALUE.
|
2015-12-16 19:09:48 +08:00
|
|
|
// TODO: Currently handles DBG_VALUE which has only reg as location.
|
2016-05-27 05:42:47 +08:00
|
|
|
if (isDbgValueDescribedByReg(MI)) {
|
2016-09-29 01:51:14 +08:00
|
|
|
VarLoc VL(MI, LS);
|
2016-05-27 05:42:47 +08:00
|
|
|
unsigned ID = VarLocIDs.insert(VL);
|
|
|
|
OpenRanges.insert(ID, VL.Var);
|
|
|
|
}
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
2018-07-13 16:24:26 +08:00
|
|
|
/// Create new TransferDebugPair and insert it in \p Transfers. The VarLoc
|
|
|
|
/// with \p OldVarID should be deleted form \p OpenRanges and replaced with
|
|
|
|
/// new VarLoc. If \p NewReg is different than default zero value then the
|
|
|
|
/// new location will be register location created by the copy like instruction,
|
|
|
|
/// otherwise it is variable's location on the stack.
|
|
|
|
void LiveDebugValues::insertTransferDebugPair(
|
|
|
|
MachineInstr &MI, OpenRangesSet &OpenRanges, TransferMap &Transfers,
|
2019-01-31 02:34:07 +08:00
|
|
|
VarLocMap &VarLocIDs, unsigned OldVarID, TransferKind Kind,
|
|
|
|
unsigned NewReg) {
|
2018-07-13 16:24:26 +08:00
|
|
|
const MachineInstr *DMI = &VarLocIDs[OldVarID].MI;
|
|
|
|
MachineFunction *MF = MI.getParent()->getParent();
|
|
|
|
MachineInstr *NewDMI;
|
2019-01-31 02:34:07 +08:00
|
|
|
|
|
|
|
auto ProcessVarLoc = [&MI, &OpenRanges, &Transfers,
|
|
|
|
&VarLocIDs](VarLoc &VL, MachineInstr *NewDMI) {
|
|
|
|
unsigned LocId = VarLocIDs.insert(VL);
|
|
|
|
OpenRanges.insert(LocId, VL.Var);
|
|
|
|
// The newly created DBG_VALUE instruction NewDMI must be inserted after
|
|
|
|
// MI. Keep track of the pairing.
|
|
|
|
TransferDebugPair MIP = {&MI, NewDMI};
|
|
|
|
Transfers.push_back(MIP);
|
|
|
|
};
|
|
|
|
|
|
|
|
// End all previous ranges of Var.
|
|
|
|
OpenRanges.erase(VarLocIDs[OldVarID].Var);
|
|
|
|
switch (Kind) {
|
|
|
|
case TransferKind::TransferCopy: {
|
|
|
|
assert(NewReg &&
|
|
|
|
"No register supplied when handling a copy of a debug value");
|
2018-07-13 16:24:26 +08:00
|
|
|
// Create a DBG_VALUE instruction to describe the Var in its new
|
|
|
|
// register location.
|
|
|
|
NewDMI = BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(),
|
|
|
|
DMI->isIndirectDebugValue(), NewReg,
|
|
|
|
DMI->getDebugVariable(), DMI->getDebugExpression());
|
|
|
|
if (DMI->isIndirectDebugValue())
|
|
|
|
NewDMI->getOperand(1).setImm(DMI->getOperand(1).getImm());
|
2019-01-31 02:34:07 +08:00
|
|
|
VarLoc VL(*NewDMI, LS);
|
|
|
|
ProcessVarLoc(VL, NewDMI);
|
2018-07-13 16:24:26 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for register copy: ";
|
|
|
|
NewDMI->print(dbgs(), false, false, false, TII));
|
2019-01-31 02:34:07 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
case TransferKind::TransferSpill: {
|
2018-07-13 16:24:26 +08:00
|
|
|
// Create a DBG_VALUE instruction to describe the Var in its spilled
|
|
|
|
// location.
|
2019-01-31 02:34:07 +08:00
|
|
|
VarLoc::SpillLoc SpillLocation = extractSpillBaseRegAndOffset(MI);
|
|
|
|
auto *SpillExpr =
|
|
|
|
DIExpression::prepend(DMI->getDebugExpression(), DIExpression::NoDeref,
|
|
|
|
SpillLocation.SpillOffset);
|
|
|
|
NewDMI =
|
|
|
|
BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(), true,
|
|
|
|
SpillLocation.SpillBase, DMI->getDebugVariable(), SpillExpr);
|
|
|
|
VarLoc VL(*NewDMI, SpillLocation.SpillBase, SpillLocation.SpillOffset, LS);
|
|
|
|
ProcessVarLoc(VL, NewDMI);
|
2018-07-13 16:24:26 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: ";
|
|
|
|
NewDMI->print(dbgs(), false, false, false, TII));
|
2019-01-31 02:34:07 +08:00
|
|
|
return;
|
2018-07-13 16:24:26 +08:00
|
|
|
}
|
2019-01-31 02:34:07 +08:00
|
|
|
case TransferKind::TransferRestore: {
|
|
|
|
assert(NewReg &&
|
|
|
|
"No register supplied when handling a restore of a debug value");
|
|
|
|
MachineFunction *MF = MI.getMF();
|
|
|
|
DIBuilder DIB(*const_cast<Function &>(MF->getFunction()).getParent());
|
|
|
|
NewDMI = BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(), false, NewReg,
|
|
|
|
DMI->getDebugVariable(), DIB.createExpression());
|
|
|
|
VarLoc VL(*NewDMI, LS);
|
|
|
|
ProcessVarLoc(VL, NewDMI);
|
|
|
|
LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for register restore: ";
|
|
|
|
NewDMI->print(dbgs(), false, false, false, TII));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
llvm_unreachable("Invalid transfer kind");
|
2018-07-13 16:24:26 +08:00
|
|
|
}
|
|
|
|
|
2015-12-16 19:09:48 +08:00
|
|
|
/// A definition of a register may mark the end of a range.
|
|
|
|
void LiveDebugValues::transferRegisterDef(MachineInstr &MI,
|
2016-05-27 05:42:47 +08:00
|
|
|
OpenRangesSet &OpenRanges,
|
2016-05-26 06:21:12 +08:00
|
|
|
const VarLocMap &VarLocIDs) {
|
2017-10-11 07:50:49 +08:00
|
|
|
MachineFunction *MF = MI.getMF();
|
2016-03-26 01:54:46 +08:00
|
|
|
const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
|
|
|
|
unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
|
2016-05-26 06:21:12 +08:00
|
|
|
SparseBitVector<> KillSet;
|
2015-12-16 19:09:48 +08:00
|
|
|
for (const MachineOperand &MO : MI.operands()) {
|
2017-03-03 09:08:25 +08:00
|
|
|
// Determine whether the operand is a register def. Assume that call
|
|
|
|
// instructions never clobber SP, because some backends (e.g., AArch64)
|
|
|
|
// never list SP in the regmask.
|
2016-03-26 01:54:46 +08:00
|
|
|
if (MO.isReg() && MO.isDef() && MO.getReg() &&
|
2017-03-03 09:08:25 +08:00
|
|
|
TRI->isPhysicalRegister(MO.getReg()) &&
|
|
|
|
!(MI.isCall() && MO.getReg() == SP)) {
|
2016-03-26 01:54:46 +08:00
|
|
|
// Remove ranges of all aliased registers.
|
|
|
|
for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
|
2016-05-27 05:42:47 +08:00
|
|
|
for (unsigned ID : OpenRanges.getVarLocs())
|
2016-05-26 06:21:12 +08:00
|
|
|
if (VarLocIDs[ID].isDescribedByReg() == *RAI)
|
|
|
|
KillSet.set(ID);
|
2016-03-26 01:54:46 +08:00
|
|
|
} else if (MO.isRegMask()) {
|
|
|
|
// Remove ranges of all clobbered registers. Register masks don't usually
|
|
|
|
// list SP as preserved. While the debug info may be off for an
|
|
|
|
// instruction or two around callee-cleanup calls, transferring the
|
|
|
|
// DEBUG_VALUE across the call is still a better user experience.
|
2016-05-27 05:42:47 +08:00
|
|
|
for (unsigned ID : OpenRanges.getVarLocs()) {
|
2016-05-26 06:21:12 +08:00
|
|
|
unsigned Reg = VarLocIDs[ID].isDescribedByReg();
|
|
|
|
if (Reg && Reg != SP && MO.clobbersPhysReg(Reg))
|
|
|
|
KillSet.set(ID);
|
|
|
|
}
|
2016-03-26 01:54:46 +08:00
|
|
|
}
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
2016-05-27 05:42:47 +08:00
|
|
|
OpenRanges.erase(KillSet, VarLocIDs);
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
2017-02-15 03:08:45 +08:00
|
|
|
/// Decide if @MI is a spill instruction and return true if it is. We use 2
|
|
|
|
/// criteria to make this decision:
|
|
|
|
/// - Is this instruction a store to a spill slot?
|
|
|
|
/// - Is there a register operand that is both used and killed?
|
|
|
|
/// TODO: Store optimization can fold spills into other stores (including
|
|
|
|
/// other spills). We do not handle this yet (more than one memory operand).
|
|
|
|
bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
|
|
|
|
MachineFunction *MF, unsigned &Reg) {
|
2018-09-05 16:59:50 +08:00
|
|
|
SmallVector<const MachineMemOperand*, 1> Accesses;
|
2017-02-15 03:08:45 +08:00
|
|
|
|
2018-07-31 03:41:25 +08:00
|
|
|
// TODO: Handle multiple stores folded into one.
|
2017-02-15 03:08:45 +08:00
|
|
|
if (!MI.hasOneMemOperand())
|
|
|
|
return false;
|
|
|
|
|
2019-01-31 02:34:07 +08:00
|
|
|
if (!MI.getSpillSize(TII) && !MI.getFoldedSpillSize(TII))
|
|
|
|
return false; // This is not a spill instruction, since no valid size was
|
|
|
|
// returned from either function.
|
2017-02-15 03:08:45 +08:00
|
|
|
|
2018-01-16 22:46:05 +08:00
|
|
|
auto isKilledReg = [&](const MachineOperand MO, unsigned &Reg) {
|
|
|
|
if (!MO.isReg() || !MO.isUse()) {
|
|
|
|
Reg = 0;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
Reg = MO.getReg();
|
|
|
|
return MO.isKill();
|
|
|
|
};
|
|
|
|
|
2017-02-15 03:08:45 +08:00
|
|
|
for (const MachineOperand &MO : MI.operands()) {
|
2018-01-16 22:46:05 +08:00
|
|
|
// In a spill instruction generated by the InlineSpiller the spilled
|
|
|
|
// register has its kill flag set.
|
|
|
|
if (isKilledReg(MO, Reg))
|
|
|
|
return true;
|
|
|
|
if (Reg != 0) {
|
|
|
|
// Check whether next instruction kills the spilled register.
|
|
|
|
// FIXME: Current solution does not cover search for killed register in
|
|
|
|
// bundles and instructions further down the chain.
|
|
|
|
auto NextI = std::next(MI.getIterator());
|
|
|
|
// Skip next instruction that points to basic block end iterator.
|
|
|
|
if (MI.getParent()->end() == NextI)
|
|
|
|
continue;
|
|
|
|
unsigned RegNext;
|
|
|
|
for (const MachineOperand &MONext : NextI->operands()) {
|
|
|
|
// Return true if we came across the register from the
|
|
|
|
// previous spill instruction that is killed in NextI.
|
|
|
|
if (isKilledReg(MONext, RegNext) && RegNext == Reg)
|
|
|
|
return true;
|
|
|
|
}
|
2017-02-15 03:08:45 +08:00
|
|
|
}
|
|
|
|
}
|
2018-01-16 22:46:05 +08:00
|
|
|
// Return false if we didn't find spilled register.
|
|
|
|
return false;
|
2017-02-15 03:08:45 +08:00
|
|
|
}
|
|
|
|
|
2019-01-31 02:34:07 +08:00
|
|
|
Optional<LiveDebugValues::VarLoc::SpillLoc>
|
|
|
|
LiveDebugValues::isRestoreInstruction(const MachineInstr &MI,
|
|
|
|
MachineFunction *MF, unsigned &Reg) {
|
|
|
|
if (!MI.hasOneMemOperand())
|
|
|
|
return None;
|
|
|
|
|
|
|
|
// FIXME: Handle folded restore instructions with more than one memory
|
|
|
|
// operand.
|
|
|
|
if (MI.getRestoreSize(TII)) {
|
|
|
|
Reg = MI.getOperand(0).getReg();
|
|
|
|
return extractSpillBaseRegAndOffset(MI);
|
|
|
|
}
|
|
|
|
return None;
|
|
|
|
}
|
|
|
|
|
2017-02-15 03:08:45 +08:00
|
|
|
/// A spilled register may indicate that we have to end the current range of
|
|
|
|
/// a variable and create a new one for the spill location.
|
2019-01-31 02:34:07 +08:00
|
|
|
/// A restored register may indicate the reverse situation.
|
2018-07-13 16:24:26 +08:00
|
|
|
/// We don't want to insert any instructions in process(), so we just create
|
|
|
|
/// the DBG_VALUE without inserting it and keep track of it in \p Transfers.
|
2017-02-15 03:08:45 +08:00
|
|
|
/// It will be inserted into the BB when we're done iterating over the
|
|
|
|
/// instructions.
|
2019-01-31 02:34:07 +08:00
|
|
|
void LiveDebugValues::transferSpillOrRestoreInst(MachineInstr &MI,
|
|
|
|
OpenRangesSet &OpenRanges,
|
|
|
|
VarLocMap &VarLocIDs,
|
|
|
|
TransferMap &Transfers) {
|
2017-10-11 07:50:49 +08:00
|
|
|
MachineFunction *MF = MI.getMF();
|
2019-01-31 02:34:07 +08:00
|
|
|
TransferKind TKind;
|
|
|
|
unsigned Reg;
|
|
|
|
Optional<VarLoc::SpillLoc> Loc;
|
2017-02-15 03:08:45 +08:00
|
|
|
|
2019-01-31 02:34:07 +08:00
|
|
|
if (isSpillInstruction(MI, MF, Reg)) {
|
|
|
|
TKind = TransferKind::TransferSpill;
|
|
|
|
LLVM_DEBUG(dbgs() << "Recognized as spill: "; MI.dump(););
|
|
|
|
LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
|
|
|
|
<< "\n");
|
|
|
|
} else {
|
|
|
|
if (!(Loc = isRestoreInstruction(MI, MF, Reg)))
|
|
|
|
return;
|
|
|
|
TKind = TransferKind::TransferRestore;
|
|
|
|
LLVM_DEBUG(dbgs() << "Recognized as restore: "; MI.dump(););
|
|
|
|
LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
|
|
|
|
<< "\n");
|
|
|
|
}
|
|
|
|
// Check if the register or spill location is the location of a debug value.
|
2017-02-15 03:08:45 +08:00
|
|
|
for (unsigned ID : OpenRanges.getVarLocs()) {
|
2019-01-31 02:34:07 +08:00
|
|
|
if (TKind == TransferKind::TransferSpill &&
|
|
|
|
VarLocIDs[ID].isDescribedByReg() == Reg) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
|
|
|
|
<< VarLocIDs[ID].Var.getVar()->getName() << ")\n");
|
2019-01-31 02:34:07 +08:00
|
|
|
} else if (TKind == TransferKind::TransferRestore &&
|
|
|
|
VarLocIDs[ID].Loc.SpillLocation == *Loc) {
|
|
|
|
LLVM_DEBUG(dbgs() << "Restoring Register " << printReg(Reg, TRI) << '('
|
|
|
|
<< VarLocIDs[ID].Var.getVar()->getName() << ")\n");
|
|
|
|
} else
|
|
|
|
continue;
|
|
|
|
insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID, TKind,
|
|
|
|
Reg);
|
2018-07-13 16:24:26 +08:00
|
|
|
}
|
|
|
|
}
|
2017-02-15 03:08:45 +08:00
|
|
|
|
2018-07-13 16:24:26 +08:00
|
|
|
/// If \p MI is a register copy instruction, that copies a previously tracked
|
|
|
|
/// value from one register to another register that is callee saved, we
|
|
|
|
/// create new DBG_VALUE instruction described with copy destination register.
|
|
|
|
void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
|
|
|
|
OpenRangesSet &OpenRanges,
|
|
|
|
VarLocMap &VarLocIDs,
|
|
|
|
TransferMap &Transfers) {
|
|
|
|
const MachineOperand *SrcRegOp, *DestRegOp;
|
|
|
|
|
|
|
|
if (!TII->isCopyInstr(MI, SrcRegOp, DestRegOp) || !SrcRegOp->isKill() ||
|
|
|
|
!DestRegOp->isDef())
|
|
|
|
return;
|
|
|
|
|
|
|
|
auto isCalleSavedReg = [&](unsigned Reg) {
|
|
|
|
for (MCRegAliasIterator RAI(Reg, TRI, true); RAI.isValid(); ++RAI)
|
|
|
|
if (CalleeSavedRegs.test(*RAI))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
};
|
|
|
|
|
|
|
|
unsigned SrcReg = SrcRegOp->getReg();
|
|
|
|
unsigned DestReg = DestRegOp->getReg();
|
|
|
|
|
|
|
|
// We want to recognize instructions where destination register is callee
|
|
|
|
// saved register. If register that could be clobbered by the call is
|
|
|
|
// included, there would be a great chance that it is going to be clobbered
|
|
|
|
// soon. It is more likely that previous register location, which is callee
|
|
|
|
// saved, is going to stay unclobbered longer, even if it is killed.
|
|
|
|
if (!isCalleSavedReg(DestReg))
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (unsigned ID : OpenRanges.getVarLocs()) {
|
|
|
|
if (VarLocIDs[ID].isDescribedByReg() == SrcReg) {
|
|
|
|
insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID,
|
2019-01-31 02:34:07 +08:00
|
|
|
TransferKind::TransferCopy, DestReg);
|
2017-02-15 03:08:45 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-16 19:09:48 +08:00
|
|
|
/// Terminate all open ranges at the end of the current basic block.
|
2016-01-10 11:25:42 +08:00
|
|
|
bool LiveDebugValues::transferTerminatorInst(MachineInstr &MI,
|
2016-05-27 05:42:47 +08:00
|
|
|
OpenRangesSet &OpenRanges,
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocInMBB &OutLocs,
|
|
|
|
const VarLocMap &VarLocIDs) {
|
2016-01-10 11:25:42 +08:00
|
|
|
bool Changed = false;
|
2015-12-16 19:09:48 +08:00
|
|
|
const MachineBasicBlock *CurMBB = MI.getParent();
|
2018-01-09 02:21:15 +08:00
|
|
|
if (!(MI.isTerminator() || (&MI == &CurMBB->back())))
|
2016-01-10 11:25:42 +08:00
|
|
|
return false;
|
2015-12-16 19:09:48 +08:00
|
|
|
|
|
|
|
if (OpenRanges.empty())
|
2016-01-10 11:25:42 +08:00
|
|
|
return false;
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(for (unsigned ID
|
|
|
|
: OpenRanges.getVarLocs()) {
|
|
|
|
// Copy OpenRanges to OutLocs, if not already present.
|
2018-10-06 05:44:00 +08:00
|
|
|
dbgs() << "Add to OutLocs in MBB #" << CurMBB->getNumber() << ": ";
|
2018-05-14 20:53:11 +08:00
|
|
|
VarLocIDs[ID].dump();
|
|
|
|
});
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocSet &VLS = OutLocs[CurMBB];
|
2016-05-27 05:42:47 +08:00
|
|
|
Changed = VLS |= OpenRanges.getVarLocs();
|
2015-12-16 19:09:48 +08:00
|
|
|
OpenRanges.clear();
|
2016-01-10 11:25:42 +08:00
|
|
|
return Changed;
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// This routine creates OpenRanges and OutLocs.
|
2018-07-13 16:24:26 +08:00
|
|
|
bool LiveDebugValues::process(MachineInstr &MI, OpenRangesSet &OpenRanges,
|
|
|
|
VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
|
|
|
|
TransferMap &Transfers, bool transferChanges) {
|
2016-01-10 11:25:42 +08:00
|
|
|
bool Changed = false;
|
2016-05-26 06:21:12 +08:00
|
|
|
transferDebugValue(MI, OpenRanges, VarLocIDs);
|
|
|
|
transferRegisterDef(MI, OpenRanges, VarLocIDs);
|
2018-07-13 16:24:26 +08:00
|
|
|
if (transferChanges) {
|
|
|
|
transferRegisterCopy(MI, OpenRanges, VarLocIDs, Transfers);
|
2019-01-31 02:34:07 +08:00
|
|
|
transferSpillOrRestoreInst(MI, OpenRanges, VarLocIDs, Transfers);
|
2018-07-13 16:24:26 +08:00
|
|
|
}
|
2016-05-26 06:21:12 +08:00
|
|
|
Changed = transferTerminatorInst(MI, OpenRanges, OutLocs, VarLocIDs);
|
2016-01-10 11:25:42 +08:00
|
|
|
return Changed;
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// This routine joins the analysis results of all incoming edges in @MBB by
|
|
|
|
/// inserting a new DBG_VALUE instruction at the start of the @MBB - if the same
|
|
|
|
/// source variable in all the predecessors of @MBB reside in the same location.
|
2018-10-06 05:44:15 +08:00
|
|
|
bool LiveDebugValues::join(
|
|
|
|
MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
|
|
|
|
const VarLocMap &VarLocIDs,
|
|
|
|
SmallPtrSet<const MachineBasicBlock *, 16> &Visited,
|
|
|
|
SmallPtrSetImpl<const MachineBasicBlock *> &ArtificialBlocks) {
|
2018-10-06 05:44:00 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "join MBB: " << MBB.getNumber() << "\n");
|
2016-01-10 11:25:42 +08:00
|
|
|
bool Changed = false;
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocSet InLocsT; // Temporary incoming locations.
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
// For all predecessors of this MBB, find the set of VarLocs that
|
|
|
|
// can be joined.
|
2016-09-28 00:46:07 +08:00
|
|
|
int NumVisited = 0;
|
2015-12-16 19:09:48 +08:00
|
|
|
for (auto p : MBB.predecessors()) {
|
2016-09-28 00:46:07 +08:00
|
|
|
// Ignore unvisited predecessor blocks. As we are processing
|
|
|
|
// the blocks in reverse post-order any unvisited block can
|
|
|
|
// be considered to not remove any incoming values.
|
2018-10-06 05:44:00 +08:00
|
|
|
if (!Visited.count(p)) {
|
|
|
|
LLVM_DEBUG(dbgs() << " ignoring unvisited pred MBB: " << p->getNumber()
|
|
|
|
<< "\n");
|
2016-09-28 00:46:07 +08:00
|
|
|
continue;
|
2018-10-06 05:44:00 +08:00
|
|
|
}
|
2015-12-16 19:09:48 +08:00
|
|
|
auto OL = OutLocs.find(p);
|
|
|
|
// Join is null in case of empty OutLocs from any of the pred.
|
|
|
|
if (OL == OutLocs.end())
|
2016-01-10 11:25:42 +08:00
|
|
|
return false;
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-09-28 00:46:07 +08:00
|
|
|
// Just copy over the Out locs to incoming locs for the first visited
|
|
|
|
// predecessor, and for all other predecessors join the Out locs.
|
|
|
|
if (!NumVisited)
|
2015-12-16 19:09:48 +08:00
|
|
|
InLocsT = OL->second;
|
2016-09-28 00:46:07 +08:00
|
|
|
else
|
|
|
|
InLocsT &= OL->second;
|
2018-10-06 05:44:00 +08:00
|
|
|
|
|
|
|
LLVM_DEBUG({
|
|
|
|
if (!InLocsT.empty()) {
|
|
|
|
for (auto ID : InLocsT)
|
|
|
|
dbgs() << " gathered candidate incoming var: "
|
|
|
|
<< VarLocIDs[ID].Var.getVar()->getName() << "\n";
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
2016-09-28 00:46:07 +08:00
|
|
|
NumVisited++;
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
2016-09-29 01:51:14 +08:00
|
|
|
// Filter out DBG_VALUES that are out of scope.
|
|
|
|
VarLocSet KillSet;
|
2018-10-06 05:44:15 +08:00
|
|
|
bool IsArtificial = ArtificialBlocks.count(&MBB);
|
|
|
|
if (!IsArtificial) {
|
|
|
|
for (auto ID : InLocsT) {
|
|
|
|
if (!VarLocIDs[ID].dominates(MBB)) {
|
|
|
|
KillSet.set(ID);
|
|
|
|
LLVM_DEBUG({
|
|
|
|
auto Name = VarLocIDs[ID].Var.getVar()->getName();
|
|
|
|
dbgs() << " killing " << Name << ", it doesn't dominate MBB\n";
|
|
|
|
});
|
|
|
|
}
|
2018-10-06 05:44:00 +08:00
|
|
|
}
|
|
|
|
}
|
2016-09-29 01:51:14 +08:00
|
|
|
InLocsT.intersectWithComplement(KillSet);
|
|
|
|
|
2016-09-28 00:46:07 +08:00
|
|
|
// As we are processing blocks in reverse post-order we
|
|
|
|
// should have processed at least one predecessor, unless it
|
|
|
|
// is the entry block which has no predecessor.
|
|
|
|
assert((NumVisited || MBB.pred_empty()) &&
|
|
|
|
"Should have processed at least one predecessor");
|
2015-12-16 19:09:48 +08:00
|
|
|
if (InLocsT.empty())
|
2016-01-10 11:25:42 +08:00
|
|
|
return false;
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocSet &ILS = InLocs[&MBB];
|
2015-12-16 19:09:48 +08:00
|
|
|
|
|
|
|
// Insert DBG_VALUE instructions, if not already inserted.
|
2016-05-26 06:21:12 +08:00
|
|
|
VarLocSet Diff = InLocsT;
|
|
|
|
Diff.intersectWithComplement(ILS);
|
|
|
|
for (auto ID : Diff) {
|
|
|
|
// This VarLoc is not found in InLocs i.e. it is not yet inserted. So, a
|
|
|
|
// new range is started for the var from the mbb's beginning by inserting
|
2018-07-13 16:24:26 +08:00
|
|
|
// a new DBG_VALUE. process() will end this range however appropriate.
|
2016-05-26 06:21:12 +08:00
|
|
|
const VarLoc &DiffIt = VarLocIDs[ID];
|
|
|
|
const MachineInstr *DMI = &DiffIt.MI;
|
|
|
|
MachineInstr *MI =
|
|
|
|
BuildMI(MBB, MBB.instr_begin(), DMI->getDebugLoc(), DMI->getDesc(),
|
2017-07-29 07:00:45 +08:00
|
|
|
DMI->isIndirectDebugValue(), DMI->getOperand(0).getReg(),
|
2016-05-26 06:21:12 +08:00
|
|
|
DMI->getDebugVariable(), DMI->getDebugExpression());
|
|
|
|
if (DMI->isIndirectDebugValue())
|
|
|
|
MI->getOperand(1).setImm(DMI->getOperand(1).getImm());
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Inserted: "; MI->dump(););
|
2016-05-26 06:21:12 +08:00
|
|
|
ILS.set(ID);
|
|
|
|
++NumInserted;
|
|
|
|
Changed = true;
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
2016-01-10 11:25:42 +08:00
|
|
|
return Changed;
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Calculate the liveness information for the given machine function and
|
|
|
|
/// extend ranges across basic blocks.
|
|
|
|
bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\nDebug Range Extension\n");
|
2015-12-16 19:09:48 +08:00
|
|
|
|
|
|
|
bool Changed = false;
|
2016-01-10 11:25:42 +08:00
|
|
|
bool OLChanged = false;
|
|
|
|
bool MBBJoined = false;
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2017-02-15 03:08:45 +08:00
|
|
|
VarLocMap VarLocIDs; // Map VarLoc<>unique ID for use in bitvectors.
|
2016-05-27 05:42:47 +08:00
|
|
|
OpenRangesSet OpenRanges; // Ranges that are open until end of bb.
|
2017-02-15 03:08:45 +08:00
|
|
|
VarLocInMBB OutLocs; // Ranges that exist beyond bb.
|
|
|
|
VarLocInMBB InLocs; // Ranges that are incoming after joining.
|
2018-07-13 16:24:26 +08:00
|
|
|
TransferMap Transfers; // DBG_VALUEs associated with spills.
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2018-10-06 05:44:15 +08:00
|
|
|
// Blocks which are artificial, i.e. blocks which exclusively contain
|
|
|
|
// instructions without locations, or with line 0 locations.
|
|
|
|
SmallPtrSet<const MachineBasicBlock *, 16> ArtificialBlocks;
|
|
|
|
|
2016-01-11 02:08:32 +08:00
|
|
|
DenseMap<unsigned int, MachineBasicBlock *> OrderToBB;
|
|
|
|
DenseMap<MachineBasicBlock *, unsigned int> BBToOrder;
|
|
|
|
std::priority_queue<unsigned int, std::vector<unsigned int>,
|
2016-05-26 06:21:12 +08:00
|
|
|
std::greater<unsigned int>>
|
|
|
|
Worklist;
|
2016-01-11 02:08:32 +08:00
|
|
|
std::priority_queue<unsigned int, std::vector<unsigned int>,
|
2016-05-26 06:21:12 +08:00
|
|
|
std::greater<unsigned int>>
|
|
|
|
Pending;
|
|
|
|
|
2018-07-13 16:24:26 +08:00
|
|
|
enum : bool { dontTransferChanges = false, transferChanges = true };
|
|
|
|
|
2015-12-16 19:09:48 +08:00
|
|
|
// Initialize every mbb with OutLocs.
|
2017-02-15 03:08:45 +08:00
|
|
|
// We are not looking at any spill instructions during the initial pass
|
|
|
|
// over the BBs. The LiveDebugVariables pass has already created DBG_VALUE
|
|
|
|
// instructions for spills of registers that are known to be user variables
|
|
|
|
// within the BB in which the spill occurs.
|
2015-12-16 19:09:48 +08:00
|
|
|
for (auto &MBB : MF)
|
|
|
|
for (auto &MI : MBB)
|
2018-07-13 16:24:26 +08:00
|
|
|
process(MI, OpenRanges, OutLocs, VarLocIDs, Transfers,
|
|
|
|
dontTransferChanges);
|
2016-05-26 06:21:12 +08:00
|
|
|
|
2018-10-06 05:44:15 +08:00
|
|
|
auto hasNonArtificialLocation = [](const MachineInstr &MI) -> bool {
|
|
|
|
if (const DebugLoc &DL = MI.getDebugLoc())
|
|
|
|
return DL.getLine() != 0;
|
|
|
|
return false;
|
|
|
|
};
|
|
|
|
for (auto &MBB : MF)
|
|
|
|
if (none_of(MBB.instrs(), hasNonArtificialLocation))
|
|
|
|
ArtificialBlocks.insert(&MBB);
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
|
|
|
|
"OutLocs after initialization", dbgs()));
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-01-11 02:08:32 +08:00
|
|
|
ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
|
|
|
|
unsigned int RPONumber = 0;
|
|
|
|
for (auto RI = RPOT.begin(), RE = RPOT.end(); RI != RE; ++RI) {
|
|
|
|
OrderToBB[RPONumber] = *RI;
|
|
|
|
BBToOrder[*RI] = RPONumber;
|
|
|
|
Worklist.push(RPONumber);
|
|
|
|
++RPONumber;
|
|
|
|
}
|
|
|
|
// This is a standard "union of predecessor outs" dataflow problem.
|
2018-07-13 16:24:26 +08:00
|
|
|
// To solve it, we perform join() and process() using the two worklist method
|
2016-01-11 02:08:32 +08:00
|
|
|
// until the ranges converge.
|
|
|
|
// Ranges have converged when both worklists are empty.
|
2016-09-28 00:46:07 +08:00
|
|
|
SmallPtrSet<const MachineBasicBlock *, 16> Visited;
|
2016-01-11 02:08:32 +08:00
|
|
|
while (!Worklist.empty() || !Pending.empty()) {
|
|
|
|
// We track what is on the pending worklist to avoid inserting the same
|
|
|
|
// thing twice. We could avoid this with a custom priority queue, but this
|
|
|
|
// is probably not worth it.
|
|
|
|
SmallPtrSet<MachineBasicBlock *, 16> OnPending;
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Processing Worklist\n");
|
2016-01-11 02:08:32 +08:00
|
|
|
while (!Worklist.empty()) {
|
|
|
|
MachineBasicBlock *MBB = OrderToBB[Worklist.top()];
|
|
|
|
Worklist.pop();
|
2018-10-06 05:44:15 +08:00
|
|
|
MBBJoined =
|
|
|
|
join(*MBB, OutLocs, InLocs, VarLocIDs, Visited, ArtificialBlocks);
|
2016-09-28 00:46:07 +08:00
|
|
|
Visited.insert(MBB);
|
2016-01-11 02:08:32 +08:00
|
|
|
if (MBBJoined) {
|
|
|
|
MBBJoined = false;
|
|
|
|
Changed = true;
|
2017-02-15 03:08:45 +08:00
|
|
|
// Now that we have started to extend ranges across BBs we need to
|
|
|
|
// examine spill instructions to see whether they spill registers that
|
|
|
|
// correspond to user variables.
|
2016-01-11 02:08:32 +08:00
|
|
|
for (auto &MI : *MBB)
|
2018-07-13 16:24:26 +08:00
|
|
|
OLChanged |= process(MI, OpenRanges, OutLocs, VarLocIDs, Transfers,
|
|
|
|
transferChanges);
|
2017-02-15 03:08:45 +08:00
|
|
|
|
|
|
|
// Add any DBG_VALUE instructions necessitated by spills.
|
2018-07-13 16:24:26 +08:00
|
|
|
for (auto &TR : Transfers)
|
|
|
|
MBB->insertAfter(MachineBasicBlock::iterator(*TR.TransferInst),
|
|
|
|
TR.DebugInst);
|
|
|
|
Transfers.clear();
|
2016-05-26 06:21:12 +08:00
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
|
|
|
|
"OutLocs after propagating", dbgs()));
|
|
|
|
LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs,
|
|
|
|
"InLocs after propagating", dbgs()));
|
2016-01-11 02:08:32 +08:00
|
|
|
|
|
|
|
if (OLChanged) {
|
|
|
|
OLChanged = false;
|
|
|
|
for (auto s : MBB->successors())
|
2016-06-18 02:59:41 +08:00
|
|
|
if (OnPending.insert(s).second) {
|
2016-01-11 02:08:32 +08:00
|
|
|
Pending.push(BBToOrder[s]);
|
|
|
|
}
|
|
|
|
}
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
|
|
|
}
|
2016-01-11 02:08:32 +08:00
|
|
|
Worklist.swap(Pending);
|
|
|
|
// At this point, pending must be empty, since it was just the empty
|
|
|
|
// worklist
|
|
|
|
assert(Pending.empty() && "Pending should be empty");
|
2015-12-16 19:09:48 +08:00
|
|
|
}
|
2016-01-11 02:08:32 +08:00
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs()));
|
|
|
|
LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs()));
|
2015-12-16 19:09:48 +08:00
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) {
|
2017-12-16 06:22:58 +08:00
|
|
|
if (!MF.getFunction().getSubprogram())
|
2016-09-29 01:51:14 +08:00
|
|
|
// LiveDebugValues will already have removed all DBG_VALUEs.
|
|
|
|
return false;
|
|
|
|
|
2017-07-20 03:36:40 +08:00
|
|
|
// Skip functions from NoDebug compilation units.
|
2017-12-16 06:22:58 +08:00
|
|
|
if (MF.getFunction().getSubprogram()->getUnit()->getEmissionKind() ==
|
2017-07-20 03:36:40 +08:00
|
|
|
DICompileUnit::NoDebug)
|
|
|
|
return false;
|
|
|
|
|
2015-12-16 19:09:48 +08:00
|
|
|
TRI = MF.getSubtarget().getRegisterInfo();
|
|
|
|
TII = MF.getSubtarget().getInstrInfo();
|
2017-02-15 03:08:45 +08:00
|
|
|
TFI = MF.getSubtarget().getFrameLowering();
|
2018-07-13 16:24:26 +08:00
|
|
|
TFI->determineCalleeSaves(MF, CalleeSavedRegs,
|
|
|
|
make_unique<RegScavenger>().get());
|
2016-09-29 01:51:14 +08:00
|
|
|
LS.initialize(MF);
|
2015-12-16 19:09:48 +08:00
|
|
|
|
2016-09-29 01:51:14 +08:00
|
|
|
bool Changed = ExtendRanges(MF);
|
2015-12-16 19:09:48 +08:00
|
|
|
return Changed;
|
|
|
|
}
|