2012-12-12 05:25:42 +08:00
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//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "SIMachineFunctionInfo.h"
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2014-05-02 23:41:42 +08:00
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#include "SIInstrInfo.h"
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2013-11-28 05:23:35 +08:00
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#include "SIRegisterInfo.h"
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2014-08-22 04:40:54 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2013-11-28 05:23:35 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2014-05-02 23:41:42 +08:00
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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2013-11-28 05:23:35 +08:00
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#define MAX_LANES 64
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2012-12-12 05:25:42 +08:00
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using namespace llvm;
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2013-11-19 08:57:56 +08:00
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// Pin the vtable to this file.
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void SIMachineFunctionInfo::anchor() {}
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2012-12-12 05:25:42 +08:00
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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2013-04-02 05:47:53 +08:00
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: AMDGPUMachineFunction(MF),
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2013-11-28 05:23:35 +08:00
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PSInputAddr(0),
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2014-07-21 23:45:01 +08:00
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NumUserSGPRs(0) { }
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2013-11-28 05:23:35 +08:00
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2014-08-22 04:40:54 +08:00
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/// \brief Returns a register that is not used at any point in the function.
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/// If all registers are used, then this function will return
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// AMDGPU::NoRegister.
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static unsigned findUnusedVGPR(const MachineRegisterInfo &MRI) {
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2013-11-28 05:23:35 +08:00
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2014-08-22 04:40:54 +08:00
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const TargetRegisterClass *RC = &AMDGPU::VGPR_32RegClass;
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
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I != E; ++I) {
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if (!MRI.isPhysRegUsed(*I))
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return *I;
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}
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return AMDGPU::NoRegister;
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}
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SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
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MachineFunction *MF,
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unsigned FrameIndex,
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unsigned SubIdx) {
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const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
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Offset += SubIdx * 4;
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unsigned LaneVGPRIdx = Offset / (64 * 4);
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unsigned Lane = (Offset / 4) % 64;
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struct SpilledReg Spill;
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if (!LaneVGPRs.count(LaneVGPRIdx)) {
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unsigned LaneVGPR = findUnusedVGPR(MRI);
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LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
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MRI.setPhysRegUsed(LaneVGPR);
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
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BI != BE; ++BI) {
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BI->addLiveIn(LaneVGPR);
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}
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}
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Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
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Spill.Lane = Lane;
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return Spill;
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2013-11-28 05:23:35 +08:00
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}
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