2017-08-25 05:21:39 +08:00
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//===- LiveInterval.cpp - Live Interval Representation --------------------===//
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2004-07-24 01:49:16 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2004-07-24 01:49:16 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2013-10-11 05:28:47 +08:00
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// This file implements the LiveRange and LiveInterval classes. Given some
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2004-07-24 01:49:16 +08:00
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// numbering of each the machine instructions an interval [i, j) is said to be a
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2013-10-11 05:28:47 +08:00
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// live range for register v if there is no instruction with number j' >= j
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2010-01-13 06:18:56 +08:00
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// such that v is live at j' and there is no instruction with number i' < i such
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2013-10-11 05:28:47 +08:00
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// that v is live at i'. In this implementation ranges can have holes,
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// i.e. a range might look like [1,20), [50,65), [1000,1001). Each
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// individual segment is represented as an instance of LiveRange::Segment,
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// and the whole range is represented as an instance of LiveRange.
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2004-07-24 01:49:16 +08:00
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//
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//===----------------------------------------------------------------------===//
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2006-11-28 10:08:17 +08:00
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#include "llvm/CodeGen/LiveInterval.h"
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2016-06-01 06:38:06 +08:00
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#include "LiveRangeUtils.h"
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2012-12-04 00:50:05 +08:00
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#include "RegisterCoalescer.h"
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2017-08-25 05:21:39 +08:00
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#include "llvm/ADT/ArrayRef.h"
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2006-11-28 11:31:29 +08:00
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#include "llvm/ADT/STLExtras.h"
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2017-08-25 05:21:39 +08:00
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/iterator_range.h"
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2017-12-13 10:51:04 +08:00
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#include "llvm/CodeGen/LiveIntervals.h"
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2017-08-25 05:21:39 +08:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2017-08-25 05:21:39 +08:00
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#include "llvm/CodeGen/SlotIndexes.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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2018-04-30 22:59:11 +08:00
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#include "llvm/Config/llvm-config.h"
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2017-08-25 05:21:39 +08:00
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/Support/Compiler.h"
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2010-01-05 06:41:43 +08:00
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#include "llvm/Support/Debug.h"
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2009-07-24 18:47:20 +08:00
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#include "llvm/Support/raw_ostream.h"
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2004-09-28 10:38:58 +08:00
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#include <algorithm>
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2017-08-25 05:21:39 +08:00
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#include <cassert>
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#include <cstddef>
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#include <iterator>
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#include <utility>
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2004-07-24 01:49:16 +08:00
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using namespace llvm;
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2015-03-23 20:30:58 +08:00
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namespace {
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2017-08-25 05:21:39 +08:00
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2015-02-07 02:42:41 +08:00
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//===----------------------------------------------------------------------===//
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// Implementation of various methods necessary for calculation of live ranges.
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// The implementation of the methods abstracts from the concrete type of the
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// segment collection.
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//
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// Implementation of the class follows the Template design pattern. The base
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// class contains generic algorithms that call collection-specific methods,
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// which are provided in concrete subclasses. In order to avoid virtual calls
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// these methods are provided by means of C++ template instantiation.
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// The base class calls the methods of the subclass through method impl(),
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// which casts 'this' pointer to the type of the subclass.
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//
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//===----------------------------------------------------------------------===//
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template <typename ImplT, typename IteratorT, typename CollectionT>
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class CalcLiveRangeUtilBase {
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protected:
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LiveRange *LR;
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protected:
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CalcLiveRangeUtilBase(LiveRange *LR) : LR(LR) {}
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public:
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2017-08-25 05:21:39 +08:00
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using Segment = LiveRange::Segment;
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using iterator = IteratorT;
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2015-02-07 02:42:41 +08:00
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2016-08-24 21:37:55 +08:00
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/// A counterpart of LiveRange::createDeadDef: Make sure the range has a
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/// value defined at @p Def.
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/// If @p ForVNI is null, and there is no value defined at @p Def, a new
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/// value will be allocated using @p VNInfoAllocator.
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/// If @p ForVNI is null, the return value is the value defined at @p Def,
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/// either a pre-existing one, or the one newly created.
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/// If @p ForVNI is not null, then @p Def should be the location where
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/// @p ForVNI is defined. If the range does not have a value defined at
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/// @p Def, the value @p ForVNI will be used instead of allocating a new
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/// one. If the range already has a value defined at @p Def, it must be
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/// same as @p ForVNI. In either case, @p ForVNI will be the return value.
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VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator *VNInfoAllocator,
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VNInfo *ForVNI) {
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2015-02-07 02:42:41 +08:00
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assert(!Def.isDead() && "Cannot define a value at the dead slot");
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2016-08-24 21:37:55 +08:00
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assert((!ForVNI || ForVNI->def == Def) &&
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"If ForVNI is specified, it must match Def");
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2015-02-07 02:42:41 +08:00
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iterator I = impl().find(Def);
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if (I == segments().end()) {
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2016-08-24 21:37:55 +08:00
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VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator);
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2015-02-07 02:42:41 +08:00
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impl().insertAtEnd(Segment(Def, Def.getDeadSlot(), VNI));
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return VNI;
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}
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Segment *S = segmentAt(I);
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if (SlotIndex::isSameInstr(Def, S->start)) {
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2016-08-24 21:37:55 +08:00
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assert((!ForVNI || ForVNI == S->valno) && "Value number mismatch");
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2015-02-07 02:42:41 +08:00
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assert(S->valno->def == S->start && "Inconsistent existing value def");
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// It is possible to have both normal and early-clobber defs of the same
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// register on an instruction. It doesn't make a lot of sense, but it is
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// possible to specify in inline assembly.
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//
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// Just convert everything to early-clobber.
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Def = std::min(Def, S->start);
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if (Def != S->start)
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S->start = S->valno->def = Def;
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return S->valno;
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}
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assert(SlotIndex::isEarlierInstr(Def, S->start) && "Already live at def");
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2016-08-24 21:37:55 +08:00
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VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator);
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2015-02-07 02:42:41 +08:00
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segments().insert(I, Segment(Def, Def.getDeadSlot(), VNI));
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return VNI;
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}
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2015-02-18 09:50:52 +08:00
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VNInfo *extendInBlock(SlotIndex StartIdx, SlotIndex Use) {
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2015-02-07 02:42:41 +08:00
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if (segments().empty())
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return nullptr;
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iterator I =
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2016-08-24 21:37:55 +08:00
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impl().findInsertPos(Segment(Use.getPrevSlot(), Use, nullptr));
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2015-02-07 02:42:41 +08:00
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if (I == segments().begin())
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return nullptr;
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--I;
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if (I->end <= StartIdx)
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return nullptr;
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2015-02-18 09:50:52 +08:00
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if (I->end < Use)
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extendSegmentEndTo(I, Use);
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2015-02-07 02:42:41 +08:00
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return I->valno;
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}
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2016-08-24 21:37:55 +08:00
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std::pair<VNInfo*,bool> extendInBlock(ArrayRef<SlotIndex> Undefs,
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SlotIndex StartIdx, SlotIndex Use) {
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if (segments().empty())
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return std::make_pair(nullptr, false);
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SlotIndex BeforeUse = Use.getPrevSlot();
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iterator I = impl().findInsertPos(Segment(BeforeUse, Use, nullptr));
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if (I == segments().begin())
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return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse));
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--I;
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if (I->end <= StartIdx)
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return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse));
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if (I->end < Use) {
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if (LR->isUndefIn(Undefs, I->end, BeforeUse))
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return std::make_pair(nullptr, true);
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extendSegmentEndTo(I, Use);
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}
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return std::make_pair(I->valno, false);
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}
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2015-02-07 02:42:41 +08:00
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/// This method is used when we want to extend the segment specified
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/// by I to end at the specified endpoint. To do this, we should
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/// merge and eliminate all segments that this will overlap
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/// with. The iterator is not invalidated.
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void extendSegmentEndTo(iterator I, SlotIndex NewEnd) {
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assert(I != segments().end() && "Not a valid segment!");
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Segment *S = segmentAt(I);
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VNInfo *ValNo = I->valno;
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// Search for the first segment that we can't merge with.
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iterator MergeTo = std::next(I);
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for (; MergeTo != segments().end() && NewEnd >= MergeTo->end; ++MergeTo)
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assert(MergeTo->valno == ValNo && "Cannot merge with differing values!");
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// If NewEnd was in the middle of a segment, make sure to get its endpoint.
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S->end = std::max(NewEnd, std::prev(MergeTo)->end);
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// If the newly formed segment now touches the segment after it and if they
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// have the same value number, merge the two segments into one segment.
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if (MergeTo != segments().end() && MergeTo->start <= I->end &&
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MergeTo->valno == ValNo) {
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S->end = MergeTo->end;
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++MergeTo;
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}
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// Erase any dead segments.
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segments().erase(std::next(I), MergeTo);
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}
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/// This method is used when we want to extend the segment specified
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/// by I to start at the specified endpoint. To do this, we should
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/// merge and eliminate all segments that this will overlap with.
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iterator extendSegmentStartTo(iterator I, SlotIndex NewStart) {
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assert(I != segments().end() && "Not a valid segment!");
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Segment *S = segmentAt(I);
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VNInfo *ValNo = I->valno;
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// Search for the first segment that we can't merge with.
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iterator MergeTo = I;
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do {
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if (MergeTo == segments().begin()) {
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S->start = NewStart;
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segments().erase(MergeTo, I);
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return I;
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}
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assert(MergeTo->valno == ValNo && "Cannot merge with differing values!");
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--MergeTo;
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} while (NewStart <= MergeTo->start);
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// If we start in the middle of another segment, just delete a range and
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// extend that segment.
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if (MergeTo->end >= NewStart && MergeTo->valno == ValNo) {
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segmentAt(MergeTo)->end = S->end;
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} else {
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// Otherwise, extend the segment right after.
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++MergeTo;
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Segment *MergeToSeg = segmentAt(MergeTo);
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MergeToSeg->start = NewStart;
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MergeToSeg->end = S->end;
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}
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segments().erase(std::next(MergeTo), std::next(I));
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return MergeTo;
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}
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iterator addSegment(Segment S) {
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SlotIndex Start = S.start, End = S.end;
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iterator I = impl().findInsertPos(S);
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// If the inserted segment starts in the middle or right at the end of
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// another segment, just extend that segment to contain the segment of S.
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if (I != segments().begin()) {
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iterator B = std::prev(I);
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if (S.valno == B->valno) {
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if (B->start <= Start && B->end >= Start) {
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extendSegmentEndTo(B, End);
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return B;
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}
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} else {
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// Check to make sure that we are not overlapping two live segments with
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// different valno's.
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assert(B->end <= Start &&
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"Cannot overlap two segments with differing ValID's"
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" (did you def the same reg twice in a MachineInstr?)");
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}
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}
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// Otherwise, if this segment ends in the middle of, or right next
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// to, another segment, merge it into that segment.
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if (I != segments().end()) {
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if (S.valno == I->valno) {
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if (I->start <= End) {
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I = extendSegmentStartTo(I, Start);
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// If S is a complete superset of a segment, we may need to grow its
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// endpoint as well.
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if (End > I->end)
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extendSegmentEndTo(I, End);
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return I;
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}
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} else {
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// Check to make sure that we are not overlapping two live segments with
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// different valno's.
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assert(I->start >= End &&
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"Cannot overlap two segments with differing ValID's");
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}
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}
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// Otherwise, this is just a new segment that doesn't interact with
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// anything.
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// Insert it.
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return segments().insert(I, S);
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}
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private:
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ImplT &impl() { return *static_cast<ImplT *>(this); }
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CollectionT &segments() { return impl().segmentsColl(); }
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Segment *segmentAt(iterator I) { return const_cast<Segment *>(&(*I)); }
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};
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//===----------------------------------------------------------------------===//
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// Instantiation of the methods for calculation of live ranges
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// based on a segment vector.
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//===----------------------------------------------------------------------===//
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class CalcLiveRangeUtilVector;
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2017-08-25 05:21:39 +08:00
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using CalcLiveRangeUtilVectorBase =
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CalcLiveRangeUtilBase<CalcLiveRangeUtilVector, LiveRange::iterator,
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LiveRange::Segments>;
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2015-02-07 02:42:41 +08:00
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class CalcLiveRangeUtilVector : public CalcLiveRangeUtilVectorBase {
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public:
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CalcLiveRangeUtilVector(LiveRange *LR) : CalcLiveRangeUtilVectorBase(LR) {}
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private:
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friend CalcLiveRangeUtilVectorBase;
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LiveRange::Segments &segmentsColl() { return LR->segments; }
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void insertAtEnd(const Segment &S) { LR->segments.push_back(S); }
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iterator find(SlotIndex Pos) { return LR->find(Pos); }
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2019-04-12 19:31:16 +08:00
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iterator findInsertPos(Segment S) { return llvm::upper_bound(*LR, S.start); }
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2015-02-07 02:42:41 +08:00
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};
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//===----------------------------------------------------------------------===//
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// Instantiation of the methods for calculation of live ranges
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// based on a segment set.
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//===----------------------------------------------------------------------===//
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class CalcLiveRangeUtilSet;
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2017-08-25 05:21:39 +08:00
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using CalcLiveRangeUtilSetBase =
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CalcLiveRangeUtilBase<CalcLiveRangeUtilSet, LiveRange::SegmentSet::iterator,
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LiveRange::SegmentSet>;
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2015-02-07 02:42:41 +08:00
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class CalcLiveRangeUtilSet : public CalcLiveRangeUtilSetBase {
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public:
|
|
|
|
CalcLiveRangeUtilSet(LiveRange *LR) : CalcLiveRangeUtilSetBase(LR) {}
|
|
|
|
|
|
|
|
private:
|
|
|
|
friend CalcLiveRangeUtilSetBase;
|
|
|
|
|
|
|
|
LiveRange::SegmentSet &segmentsColl() { return *LR->segmentSet; }
|
|
|
|
|
|
|
|
void insertAtEnd(const Segment &S) {
|
|
|
|
LR->segmentSet->insert(LR->segmentSet->end(), S);
|
|
|
|
}
|
|
|
|
|
|
|
|
iterator find(SlotIndex Pos) {
|
|
|
|
iterator I =
|
|
|
|
LR->segmentSet->upper_bound(Segment(Pos, Pos.getNextSlot(), nullptr));
|
|
|
|
if (I == LR->segmentSet->begin())
|
|
|
|
return I;
|
|
|
|
iterator PrevI = std::prev(I);
|
|
|
|
if (Pos < (*PrevI).end)
|
|
|
|
return PrevI;
|
|
|
|
return I;
|
|
|
|
}
|
|
|
|
|
|
|
|
iterator findInsertPos(Segment S) {
|
|
|
|
iterator I = LR->segmentSet->upper_bound(S);
|
|
|
|
if (I != LR->segmentSet->end() && !(S.start < *I))
|
|
|
|
++I;
|
|
|
|
return I;
|
|
|
|
}
|
|
|
|
};
|
2017-08-25 05:21:39 +08:00
|
|
|
|
|
|
|
} // end anonymous namespace
|
2015-02-07 02:42:41 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// LiveRange methods
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
LiveRange::iterator LiveRange::find(SlotIndex Pos) {
|
2011-03-12 09:50:35 +08:00
|
|
|
// This algorithm is basically std::upper_bound.
|
|
|
|
// Unfortunately, std::upper_bound cannot be used with mixed types until we
|
|
|
|
// adopt C++0x. Many libraries can do it, but not all.
|
|
|
|
if (empty() || Pos >= endIndex())
|
|
|
|
return end();
|
|
|
|
iterator I = begin();
|
2013-09-07 00:44:32 +08:00
|
|
|
size_t Len = size();
|
2011-03-12 09:50:35 +08:00
|
|
|
do {
|
|
|
|
size_t Mid = Len >> 1;
|
2016-02-19 06:09:30 +08:00
|
|
|
if (Pos < I[Mid].end) {
|
2011-03-12 09:50:35 +08:00
|
|
|
Len = Mid;
|
2016-02-19 06:09:30 +08:00
|
|
|
} else {
|
|
|
|
I += Mid + 1;
|
|
|
|
Len -= Mid + 1;
|
|
|
|
}
|
2011-03-12 09:50:35 +08:00
|
|
|
} while (Len);
|
|
|
|
return I;
|
2010-06-26 06:53:05 +08:00
|
|
|
}
|
|
|
|
|
2016-08-24 21:37:55 +08:00
|
|
|
VNInfo *LiveRange::createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc) {
|
|
|
|
// Use the segment set, if it is available.
|
|
|
|
if (segmentSet != nullptr)
|
|
|
|
return CalcLiveRangeUtilSet(this).createDeadDef(Def, &VNIAlloc, nullptr);
|
|
|
|
// Otherwise use the segment vector.
|
|
|
|
return CalcLiveRangeUtilVector(this).createDeadDef(Def, &VNIAlloc, nullptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
VNInfo *LiveRange::createDeadDef(VNInfo *VNI) {
|
2015-02-07 02:42:41 +08:00
|
|
|
// Use the segment set, if it is available.
|
|
|
|
if (segmentSet != nullptr)
|
2016-08-24 21:37:55 +08:00
|
|
|
return CalcLiveRangeUtilSet(this).createDeadDef(VNI->def, nullptr, VNI);
|
2015-02-07 02:42:41 +08:00
|
|
|
// Otherwise use the segment vector.
|
2016-08-24 21:37:55 +08:00
|
|
|
return CalcLiveRangeUtilVector(this).createDeadDef(VNI->def, nullptr, VNI);
|
2012-06-06 05:54:09 +08:00
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
// overlaps - Return true if the intersection of the two live ranges is
|
2004-11-18 11:47:34 +08:00
|
|
|
// not empty.
|
|
|
|
//
|
2004-07-24 01:49:16 +08:00
|
|
|
// An example for overlaps():
|
|
|
|
//
|
|
|
|
// 0: A = ...
|
|
|
|
// 4: B = ...
|
|
|
|
// 8: C = A + B ;; last use of A
|
|
|
|
//
|
2013-10-11 05:28:47 +08:00
|
|
|
// The live ranges should look like:
|
2004-07-24 01:49:16 +08:00
|
|
|
//
|
|
|
|
// A = [3, 11)
|
|
|
|
// B = [7, x)
|
|
|
|
// C = [11, y)
|
|
|
|
//
|
|
|
|
// A->overlaps(C) should return false since we want to be able to join
|
|
|
|
// A and C.
|
2004-11-18 11:47:34 +08:00
|
|
|
//
|
2013-10-11 05:28:47 +08:00
|
|
|
bool LiveRange::overlapsFrom(const LiveRange& other,
|
|
|
|
const_iterator StartPos) const {
|
|
|
|
assert(!empty() && "empty range");
|
2004-11-18 11:47:34 +08:00
|
|
|
const_iterator i = begin();
|
|
|
|
const_iterator ie = end();
|
|
|
|
const_iterator j = StartPos;
|
|
|
|
const_iterator je = other.end();
|
|
|
|
|
|
|
|
assert((StartPos->start <= i->start || StartPos == other.begin()) &&
|
2004-11-18 12:02:11 +08:00
|
|
|
StartPos != other.end() && "Bogus start position hint!");
|
This patch makes use of the infrastructure implemented before to safely and
aggressively coallesce live ranges even if they overlap. Consider this LLVM
code for example:
int %test(int %X) {
%Y = mul int %X, 1 ;; Codegens to Y = X
%Z = add int %X, %Y
ret int %Z
}
The mul is just there to get a copy into the code stream. This produces
this machine code:
(0x869e5a8, LLVM BB @0x869b9a0):
%reg1024 = mov <fi#-2>, 1, %NOREG, 0 ;; "X"
%reg1025 = mov %reg1024 ;; "Y" (subsumed by X)
%reg1026 = add %reg1024, %reg1025
%EAX = mov %reg1026
ret
Note that the life times of reg1024 and reg1025 overlap, even though they
contain the same value. This results in this machine code:
test:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
add %EAX, %ECX
ret
Another, worse case involves loops and PHI nodes. Consider this trivial loop:
testcase:
int %test2(int %X) {
entry:
br label %Loop
Loop:
%Y = phi int [%X, %entry], [%Z, %Loop]
%Z = add int %Y, 1
%cond = seteq int %Z, 100
br bool %cond, label %Out, label %Loop
Out:
ret int %Z
}
Because of interactions between the PHI elimination pass and the register
allocator, this got compiled to this code:
test2:
mov %ECX, DWORD PTR [%ESP + 4]
.LBBtest2_1:
*** mov %EAX, %ECX
inc %EAX
cmp %EAX, 100
*** mov %ECX, %EAX
jne .LBBtest2_1
ret
Or on powerpc, this code:
_test2:
mflr r0
stw r0, 8(r1)
stwu r1, -60(r1)
.LBB_test2_1:
addi r2, r3, 1
cmpwi cr0, r2, 100
*** or r3, r2, r2
bne cr0, .LBB_test2_1
*** or r3, r2, r2
lwz r0, 68(r1)
mtlr r0
addi r1, r1, 60
blr 0
With this improvement in place, we now generate this code for these two
testcases, which is what we want:
test:
mov %EAX, DWORD PTR [%ESP + 4]
add %EAX, %EAX
ret
test2:
mov %EAX, DWORD PTR [%ESP + 4]
.LBBtest2_1:
inc %EAX
cmp %EAX, 100
jne .LBBtest2_1 # Loop
ret
Or on PPC:
_test2:
mflr r0
stw r0, 8(r1)
stwu r1, -60(r1)
.LBB_test2_1:
addi r3, r3, 1
cmpwi cr0, r3, 100
bne cr0, .LBB_test2_1
lwz r0, 68(r1)
mtlr r0
addi r1, r1, 60
blr 0
Static numbers for spill code loads/stores/reg-reg copies (smaller is better):
em3d: before: 47/25/26 after: 44/22/24
164.gzip: before: 433/245/310 after: 403/231/278
175.vpr: before: 3721/2189/1581 after: 4144/2081/1423
176.gcc: before: 26195/8866/9235 after: 25942/8082/8275
186.crafty: before: 4295/2587/3079 after: 4119/2519/2916
252.eon: before: 12754/7585/5803 after: 12508/7425/5643
256.bzip2: before: 463/226/315 after: 482:241/309
Runtime perf number samples on X86:
gzip: before: 41.09 after: 39.86
bzip2: runtime: before: 56.71s after: 57.07s
gcc: before: 6.16 after: 6.12
eon: before: 2.03s after: 2.00s
llvm-svn: 15194
2004-07-25 15:11:19 +08:00
|
|
|
|
2004-07-24 01:49:16 +08:00
|
|
|
if (i->start < j->start) {
|
2004-07-24 02:40:00 +08:00
|
|
|
i = std::upper_bound(i, ie, j->start);
|
2013-09-07 00:44:32 +08:00
|
|
|
if (i != begin()) --i;
|
2004-07-24 02:40:00 +08:00
|
|
|
} else if (j->start < i->start) {
|
2004-12-04 09:22:09 +08:00
|
|
|
++StartPos;
|
|
|
|
if (StartPos != other.end() && StartPos->start <= i->start) {
|
|
|
|
assert(StartPos < other.end() && i < end());
|
2004-11-18 12:02:11 +08:00
|
|
|
j = std::upper_bound(j, je, i->start);
|
2013-09-07 00:44:32 +08:00
|
|
|
if (j != other.begin()) --j;
|
2004-11-18 12:02:11 +08:00
|
|
|
}
|
2004-07-24 02:40:00 +08:00
|
|
|
} else {
|
|
|
|
return true;
|
2004-07-24 01:49:16 +08:00
|
|
|
}
|
|
|
|
|
2004-11-18 13:28:21 +08:00
|
|
|
if (j == je) return false;
|
|
|
|
|
|
|
|
while (i != ie) {
|
2004-07-24 01:49:16 +08:00
|
|
|
if (i->start > j->start) {
|
2004-07-24 19:44:15 +08:00
|
|
|
std::swap(i, j);
|
|
|
|
std::swap(ie, je);
|
2004-07-24 01:49:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (i->end > j->start)
|
|
|
|
return true;
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
bool LiveRange::overlaps(const LiveRange &Other, const CoalescerPair &CP,
|
|
|
|
const SlotIndexes &Indexes) const {
|
|
|
|
assert(!empty() && "empty range");
|
2012-09-07 02:15:23 +08:00
|
|
|
if (Other.empty())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Use binary searches to find initial positions.
|
|
|
|
const_iterator I = find(Other.beginIndex());
|
|
|
|
const_iterator IE = end();
|
|
|
|
if (I == IE)
|
|
|
|
return false;
|
|
|
|
const_iterator J = Other.find(I->start);
|
|
|
|
const_iterator JE = Other.end();
|
|
|
|
if (J == JE)
|
|
|
|
return false;
|
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
while (true) {
|
2012-09-07 02:15:23 +08:00
|
|
|
// J has just been advanced to satisfy:
|
|
|
|
assert(J->end >= I->start);
|
|
|
|
// Check for an overlap.
|
|
|
|
if (J->start < I->end) {
|
|
|
|
// I and J are overlapping. Find the later start.
|
|
|
|
SlotIndex Def = std::max(I->start, J->start);
|
|
|
|
// Allow the overlap if Def is a coalescable copy.
|
|
|
|
if (Def.isBlock() ||
|
|
|
|
!CP.isCoalescable(Indexes.getInstructionFromIndex(Def)))
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
// Advance the iterator that ends first to check for more overlaps.
|
|
|
|
if (J->end > I->end) {
|
|
|
|
std::swap(I, J);
|
|
|
|
std::swap(IE, JE);
|
|
|
|
}
|
|
|
|
// Advance J until J->end >= I->start.
|
|
|
|
do
|
|
|
|
if (++J == JE)
|
|
|
|
return false;
|
|
|
|
while (J->end < I->start);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
/// overlaps - Return true if the live range overlaps an interval specified
|
2009-04-18 16:52:15 +08:00
|
|
|
/// by [Start, End).
|
2013-10-11 05:28:47 +08:00
|
|
|
bool LiveRange::overlaps(SlotIndex Start, SlotIndex End) const {
|
2009-04-18 16:52:15 +08:00
|
|
|
assert(Start < End && "Invalid range");
|
2021-01-30 15:23:35 +08:00
|
|
|
const_iterator I = lower_bound(*this, End);
|
2010-07-14 03:42:20 +08:00
|
|
|
return I != begin() && (--I)->end > Start;
|
2009-04-18 16:52:15 +08:00
|
|
|
}
|
|
|
|
|
2014-12-10 09:12:06 +08:00
|
|
|
bool LiveRange::covers(const LiveRange &Other) const {
|
|
|
|
if (empty())
|
|
|
|
return Other.empty();
|
|
|
|
|
|
|
|
const_iterator I = begin();
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const Segment &O : Other.segments) {
|
|
|
|
I = advanceTo(I, O.start);
|
|
|
|
if (I == end() || I->start > O.start)
|
2014-12-10 09:12:06 +08:00
|
|
|
return false;
|
|
|
|
|
2014-12-11 07:07:54 +08:00
|
|
|
// Check adjacent live segments and see if we can get behind O.end.
|
|
|
|
while (I->end < O.end) {
|
2014-12-10 09:12:06 +08:00
|
|
|
const_iterator Last = I;
|
|
|
|
// Get next segment and abort if it was not adjacent.
|
|
|
|
++I;
|
|
|
|
if (I == end() || Last->end != I->start)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
2010-07-26 09:49:41 +08:00
|
|
|
|
|
|
|
/// ValNo is dead, remove it. If it is the largest value number, just nuke it
|
|
|
|
/// (and any other deleted values neighboring it), otherwise mark it as ~1U so
|
|
|
|
/// it can be nuked later.
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::markValNoForDeletion(VNInfo *ValNo) {
|
2010-07-26 09:49:41 +08:00
|
|
|
if (ValNo->id == getNumValNums()-1) {
|
|
|
|
do {
|
|
|
|
valnos.pop_back();
|
|
|
|
} while (!valnos.empty() && valnos.back()->isUnused());
|
|
|
|
} else {
|
2012-08-04 04:59:32 +08:00
|
|
|
ValNo->markUnused();
|
2010-07-26 09:49:41 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-08-07 02:46:59 +08:00
|
|
|
/// RenumberValues - Renumber all values in order of appearance and delete the
|
|
|
|
/// remaining unused values.
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::RenumberValues() {
|
2010-08-07 02:46:59 +08:00
|
|
|
SmallPtrSet<VNInfo*, 8> Seen;
|
|
|
|
valnos.clear();
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const Segment &S : segments) {
|
|
|
|
VNInfo *VNI = S.valno;
|
2014-11-19 15:49:26 +08:00
|
|
|
if (!Seen.insert(VNI).second)
|
2010-08-07 02:46:59 +08:00
|
|
|
continue;
|
2013-10-11 05:28:43 +08:00
|
|
|
assert(!VNI->isUnused() && "Unused valno used by live segment");
|
2010-08-07 02:46:59 +08:00
|
|
|
VNI->id = (unsigned)valnos.size();
|
|
|
|
valnos.push_back(VNI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-02-07 02:42:41 +08:00
|
|
|
void LiveRange::addSegmentToSet(Segment S) {
|
|
|
|
CalcLiveRangeUtilSet(this).addSegment(S);
|
2004-07-24 01:49:16 +08:00
|
|
|
}
|
|
|
|
|
2015-02-07 02:42:41 +08:00
|
|
|
LiveRange::iterator LiveRange::addSegment(Segment S) {
|
|
|
|
// Use the segment set, if it is available.
|
|
|
|
if (segmentSet != nullptr) {
|
|
|
|
addSegmentToSet(S);
|
|
|
|
return end();
|
2004-07-24 01:49:16 +08:00
|
|
|
}
|
2015-02-07 02:42:41 +08:00
|
|
|
// Otherwise use the segment vector.
|
|
|
|
return CalcLiveRangeUtilVector(this).addSegment(S);
|
2004-07-24 01:49:16 +08:00
|
|
|
}
|
|
|
|
|
2014-12-24 10:11:51 +08:00
|
|
|
void LiveRange::append(const Segment S) {
|
|
|
|
// Check that the segment belongs to the back of the list.
|
|
|
|
assert(segments.empty() || segments.back().end <= S.start);
|
|
|
|
segments.push_back(S);
|
|
|
|
}
|
|
|
|
|
2016-08-24 21:37:55 +08:00
|
|
|
std::pair<VNInfo*,bool> LiveRange::extendInBlock(ArrayRef<SlotIndex> Undefs,
|
|
|
|
SlotIndex StartIdx, SlotIndex Kill) {
|
|
|
|
// Use the segment set, if it is available.
|
|
|
|
if (segmentSet != nullptr)
|
|
|
|
return CalcLiveRangeUtilSet(this).extendInBlock(Undefs, StartIdx, Kill);
|
|
|
|
// Otherwise use the segment vector.
|
|
|
|
return CalcLiveRangeUtilVector(this).extendInBlock(Undefs, StartIdx, Kill);
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
VNInfo *LiveRange::extendInBlock(SlotIndex StartIdx, SlotIndex Kill) {
|
2015-02-07 02:42:41 +08:00
|
|
|
// Use the segment set, if it is available.
|
|
|
|
if (segmentSet != nullptr)
|
|
|
|
return CalcLiveRangeUtilSet(this).extendInBlock(StartIdx, Kill);
|
|
|
|
// Otherwise use the segment vector.
|
|
|
|
return CalcLiveRangeUtilVector(this).extendInBlock(StartIdx, Kill);
|
2011-03-02 08:06:15 +08:00
|
|
|
}
|
2004-07-24 10:52:23 +08:00
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
/// Remove the specified segment from this range. Note that the segment must
|
2013-10-11 05:28:43 +08:00
|
|
|
/// be in a single Segment in its entirety.
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::removeSegment(SlotIndex Start, SlotIndex End,
|
|
|
|
bool RemoveDeadValNo) {
|
2013-10-11 05:28:43 +08:00
|
|
|
// Find the Segment containing this span.
|
2013-09-07 00:44:32 +08:00
|
|
|
iterator I = find(Start);
|
2013-10-11 05:28:47 +08:00
|
|
|
assert(I != end() && "Segment is not in range!");
|
2013-10-11 05:28:43 +08:00
|
|
|
assert(I->containsInterval(Start, End)
|
2013-10-11 05:28:47 +08:00
|
|
|
&& "Segment is not entirely in range!");
|
2004-07-24 10:52:23 +08:00
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
// If the span we are removing is at the start of the Segment, adjust it.
|
2008-02-13 10:48:26 +08:00
|
|
|
VNInfo *ValNo = I->valno;
|
2004-07-24 10:52:23 +08:00
|
|
|
if (I->start == Start) {
|
2007-08-11 08:59:19 +08:00
|
|
|
if (I->end == End) {
|
2013-10-11 05:28:43 +08:00
|
|
|
segments.erase(I); // Removed the whole Segment.
|
2021-09-27 23:05:54 +08:00
|
|
|
|
|
|
|
if (RemoveDeadValNo)
|
|
|
|
removeValNoIfDead(ValNo);
|
2007-08-11 08:59:19 +08:00
|
|
|
} else
|
2004-07-24 10:52:23 +08:00
|
|
|
I->start = End;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
// Otherwise if the span we are removing is at the end of the Segment,
|
2004-07-24 10:52:23 +08:00
|
|
|
// adjust the other way.
|
|
|
|
if (I->end == End) {
|
2004-07-25 13:43:53 +08:00
|
|
|
I->end = Start;
|
2004-07-24 10:52:23 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
// Otherwise, we are splitting the Segment into two pieces.
|
2009-11-04 07:52:08 +08:00
|
|
|
SlotIndex OldEnd = I->end;
|
2013-10-11 05:28:47 +08:00
|
|
|
I->end = Start; // Trim the old segment.
|
2004-07-24 10:52:23 +08:00
|
|
|
|
|
|
|
// Insert the new one.
|
2014-03-02 20:27:27 +08:00
|
|
|
segments.insert(std::next(I), Segment(End, OldEnd, ValNo));
|
2004-07-24 10:52:23 +08:00
|
|
|
}
|
|
|
|
|
2021-09-27 23:05:54 +08:00
|
|
|
LiveRange::iterator LiveRange::removeSegment(iterator I, bool RemoveDeadValNo) {
|
|
|
|
VNInfo *ValNo = I->valno;
|
|
|
|
I = segments.erase(I);
|
|
|
|
if (RemoveDeadValNo)
|
|
|
|
removeValNoIfDead(ValNo);
|
|
|
|
return I;
|
|
|
|
}
|
|
|
|
|
|
|
|
void LiveRange::removeValNoIfDead(VNInfo *ValNo) {
|
|
|
|
if (none_of(*this, [=](const Segment &S) { return S.valno == ValNo; }))
|
|
|
|
markValNoForDeletion(ValNo);
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
/// removeValNo - Remove all the segments defined by the specified value#.
|
2008-02-13 10:48:26 +08:00
|
|
|
/// Also remove the value# from value# list.
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::removeValNo(VNInfo *ValNo) {
|
2008-02-13 10:48:26 +08:00
|
|
|
if (empty()) return;
|
2021-10-19 00:33:42 +08:00
|
|
|
llvm::erase_if(segments,
|
|
|
|
[ValNo](const Segment &S) { return S.valno == ValNo; });
|
2010-07-26 09:49:41 +08:00
|
|
|
// Now that ValNo is dead, remove it.
|
|
|
|
markValNoForDeletion(ValNo);
|
2008-02-13 10:48:26 +08:00
|
|
|
}
|
2009-09-05 04:41:11 +08:00
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::join(LiveRange &Other,
|
|
|
|
const int *LHSValNoAssignments,
|
|
|
|
const int *RHSValNoAssignments,
|
|
|
|
SmallVectorImpl<VNInfo *> &NewVNInfo) {
|
2012-07-10 13:06:03 +08:00
|
|
|
verify();
|
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
// Determine if any of our values are mapped. This is uncommon, so we want
|
2013-10-11 05:28:47 +08:00
|
|
|
// to avoid the range scan if not.
|
2006-08-30 07:18:15 +08:00
|
|
|
bool MustMapCurValNos = false;
|
2007-09-01 10:03:17 +08:00
|
|
|
unsigned NumVals = getNumValNums();
|
|
|
|
unsigned NumNewVals = NewVNInfo.size();
|
|
|
|
for (unsigned i = 0; i != NumVals; ++i) {
|
|
|
|
unsigned LHSValID = LHSValNoAssignments[i];
|
|
|
|
if (i != LHSValID ||
|
2012-02-02 14:55:45 +08:00
|
|
|
(NewVNInfo[LHSValID] && NewVNInfo[LHSValID] != getValNumInfo(i))) {
|
2006-08-30 07:18:15 +08:00
|
|
|
MustMapCurValNos = true;
|
2012-02-02 14:55:45 +08:00
|
|
|
break;
|
|
|
|
}
|
2006-08-30 07:18:15 +08:00
|
|
|
}
|
2007-08-30 04:45:00 +08:00
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
// If we have to apply a mapping to our base range assignment, rewrite it now.
|
2012-09-28 05:05:59 +08:00
|
|
|
if (MustMapCurValNos && !empty()) {
|
2006-08-30 07:18:15 +08:00
|
|
|
// Map the first live range.
|
2012-02-02 13:37:34 +08:00
|
|
|
|
2006-08-30 07:18:15 +08:00
|
|
|
iterator OutIt = begin();
|
2007-08-30 04:45:00 +08:00
|
|
|
OutIt->valno = NewVNInfo[LHSValNoAssignments[OutIt->valno->id]];
|
2014-03-02 20:27:27 +08:00
|
|
|
for (iterator I = std::next(OutIt), E = end(); I != E; ++I) {
|
2012-02-02 13:37:34 +08:00
|
|
|
VNInfo* nextValNo = NewVNInfo[LHSValNoAssignments[I->valno->id]];
|
2014-04-14 08:51:57 +08:00
|
|
|
assert(nextValNo && "Huh?");
|
2010-08-13 04:01:23 +08:00
|
|
|
|
2006-08-30 07:18:15 +08:00
|
|
|
// If this live range has the same value # as its immediate predecessor,
|
2013-10-11 05:28:43 +08:00
|
|
|
// and if they are neighbors, remove one Segment. This happens when we
|
2012-02-02 13:37:34 +08:00
|
|
|
// have [0,4:0)[4,7:1) and map 0/1 onto the same value #.
|
|
|
|
if (OutIt->valno == nextValNo && OutIt->end == I->start) {
|
|
|
|
OutIt->end = I->end;
|
2006-08-30 07:18:15 +08:00
|
|
|
} else {
|
2013-10-11 05:28:47 +08:00
|
|
|
// Didn't merge. Move OutIt to the next segment,
|
2012-02-02 13:37:34 +08:00
|
|
|
++OutIt;
|
|
|
|
OutIt->valno = nextValNo;
|
|
|
|
if (OutIt != I) {
|
2006-08-30 07:18:15 +08:00
|
|
|
OutIt->start = I->start;
|
|
|
|
OutIt->end = I->end;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2013-10-11 05:28:43 +08:00
|
|
|
// If we merge some segments, chop off the end.
|
2012-02-02 13:37:34 +08:00
|
|
|
++OutIt;
|
2013-10-11 05:28:43 +08:00
|
|
|
segments.erase(OutIt, end());
|
2004-07-24 11:41:50 +08:00
|
|
|
}
|
2007-08-11 08:59:19 +08:00
|
|
|
|
2013-02-21 07:51:10 +08:00
|
|
|
// Rewrite Other values before changing the VNInfo ids.
|
|
|
|
// This can leave Other in an invalid state because we're not coalescing
|
|
|
|
// touching segments that now have identical values. That's OK since Other is
|
|
|
|
// not supposed to be valid after calling join();
|
2014-12-11 07:07:54 +08:00
|
|
|
for (Segment &S : Other.segments)
|
|
|
|
S.valno = NewVNInfo[RHSValNoAssignments[S.valno->id]];
|
2007-08-30 04:45:00 +08:00
|
|
|
|
|
|
|
// Update val# info. Renumber them and make sure they all belong to this
|
2013-10-11 05:28:47 +08:00
|
|
|
// LiveRange now. Also remove dead val#'s.
|
2007-09-06 05:46:51 +08:00
|
|
|
unsigned NumValNos = 0;
|
|
|
|
for (unsigned i = 0; i < NumNewVals; ++i) {
|
2007-09-01 10:03:17 +08:00
|
|
|
VNInfo *VNI = NewVNInfo[i];
|
2007-09-06 05:46:51 +08:00
|
|
|
if (VNI) {
|
2009-04-28 14:24:09 +08:00
|
|
|
if (NumValNos >= NumVals)
|
2007-09-06 05:46:51 +08:00
|
|
|
valnos.push_back(VNI);
|
2010-08-13 04:01:23 +08:00
|
|
|
else
|
2007-09-06 05:46:51 +08:00
|
|
|
valnos[NumValNos] = VNI;
|
|
|
|
VNI->id = NumValNos++; // Renumber val#.
|
2007-09-01 10:03:17 +08:00
|
|
|
}
|
2007-08-30 04:45:00 +08:00
|
|
|
}
|
2007-09-01 10:03:17 +08:00
|
|
|
if (NumNewVals < NumVals)
|
|
|
|
valnos.resize(NumNewVals); // shrinkify
|
2007-08-11 08:59:19 +08:00
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
// Okay, now insert the RHS live segments into the LHS.
|
2013-02-21 02:18:15 +08:00
|
|
|
LiveRangeUpdater Updater(this);
|
2014-12-11 07:07:54 +08:00
|
|
|
for (Segment &S : Other.segments)
|
|
|
|
Updater.add(S);
|
2006-09-02 13:26:59 +08:00
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
/// Merge all of the segments in RHS into this live range as the specified
|
2013-10-11 05:28:43 +08:00
|
|
|
/// value number. The segments in RHS are allowed to overlap with segments in
|
2013-10-11 05:28:47 +08:00
|
|
|
/// the current range, but only if the overlapping segments have the
|
2013-10-11 05:28:43 +08:00
|
|
|
/// specified value number.
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::MergeSegmentsInAsValue(const LiveRange &RHS,
|
|
|
|
VNInfo *LHSValNo) {
|
2013-02-21 02:18:15 +08:00
|
|
|
LiveRangeUpdater Updater(this);
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const Segment &S : RHS.segments)
|
|
|
|
Updater.add(S.start, S.end, LHSValNo);
|
2012-07-10 13:16:17 +08:00
|
|
|
}
|
2006-09-02 13:26:59 +08:00
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
/// MergeValueInAsValue - Merge all of the live segments of a specific val#
|
2013-10-11 05:28:47 +08:00
|
|
|
/// in RHS into this live range as the specified value number.
|
2013-10-11 05:28:43 +08:00
|
|
|
/// The segments in RHS are allowed to overlap with segments in the
|
2013-10-11 05:28:47 +08:00
|
|
|
/// current range, it will replace the value numbers of the overlaped
|
2013-10-11 05:28:43 +08:00
|
|
|
/// segments with the specified value number.
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::MergeValueInAsValue(const LiveRange &RHS,
|
|
|
|
const VNInfo *RHSValNo,
|
|
|
|
VNInfo *LHSValNo) {
|
2013-02-21 02:18:15 +08:00
|
|
|
LiveRangeUpdater Updater(this);
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const Segment &S : RHS.segments)
|
|
|
|
if (S.valno == RHSValNo)
|
|
|
|
Updater.add(S.start, S.end, LHSValNo);
|
2007-10-12 16:50:34 +08:00
|
|
|
}
|
|
|
|
|
2006-08-25 06:43:55 +08:00
|
|
|
/// MergeValueNumberInto - This method is called when two value nubmers
|
|
|
|
/// are found to be equivalent. This eliminates V1, replacing all
|
2013-10-11 05:28:43 +08:00
|
|
|
/// segments with the V1 value number with the V2 value number. This can
|
2006-08-25 06:43:55 +08:00
|
|
|
/// cause merging of V1/V2 values numbers and compaction of the value space.
|
2013-10-11 05:28:47 +08:00
|
|
|
VNInfo *LiveRange::MergeValueNumberInto(VNInfo *V1, VNInfo *V2) {
|
2006-08-25 06:43:55 +08:00
|
|
|
assert(V1 != V2 && "Identical value#'s are always equivalent!");
|
|
|
|
|
|
|
|
// This code actually merges the (numerically) larger value number into the
|
|
|
|
// smaller value number, which is likely to allow us to compactify the value
|
|
|
|
// space. The only thing we have to be careful of is to preserve the
|
|
|
|
// instruction that defines the result value.
|
|
|
|
|
|
|
|
// Make sure V2 is smaller than V1.
|
2007-08-30 04:45:00 +08:00
|
|
|
if (V1->id < V2->id) {
|
2009-08-11 07:43:28 +08:00
|
|
|
V1->copyFrom(*V2);
|
2006-08-25 06:43:55 +08:00
|
|
|
std::swap(V1, V2);
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
// Merge V1 segments into V2.
|
2006-08-25 06:43:55 +08:00
|
|
|
for (iterator I = begin(); I != end(); ) {
|
2013-10-11 05:28:43 +08:00
|
|
|
iterator S = I++;
|
|
|
|
if (S->valno != V1) continue; // Not a V1 Segment.
|
2010-08-13 04:01:23 +08:00
|
|
|
|
2006-08-25 06:43:55 +08:00
|
|
|
// Okay, we found a V1 live range. If it had a previous, touching, V2 live
|
|
|
|
// range, extend it.
|
2013-10-11 05:28:43 +08:00
|
|
|
if (S != begin()) {
|
|
|
|
iterator Prev = S-1;
|
|
|
|
if (Prev->valno == V2 && Prev->end == S->start) {
|
|
|
|
Prev->end = S->end;
|
2006-08-25 06:43:55 +08:00
|
|
|
|
|
|
|
// Erase this live-range.
|
2013-10-11 05:28:43 +08:00
|
|
|
segments.erase(S);
|
2006-08-25 06:43:55 +08:00
|
|
|
I = Prev+1;
|
2013-10-11 05:28:43 +08:00
|
|
|
S = Prev;
|
2006-08-25 06:43:55 +08:00
|
|
|
}
|
|
|
|
}
|
2010-08-13 04:01:23 +08:00
|
|
|
|
2006-08-25 06:43:55 +08:00
|
|
|
// Okay, now we have a V1 or V2 live range that is maximally merged forward.
|
|
|
|
// Ensure that it is a V2 live-range.
|
2013-10-11 05:28:43 +08:00
|
|
|
S->valno = V2;
|
2010-08-13 04:01:23 +08:00
|
|
|
|
2013-10-11 05:28:43 +08:00
|
|
|
// If we can merge it into later V2 segments, do so now. We ignore any
|
|
|
|
// following V1 segments, as they will be merged in subsequent iterations
|
2006-08-25 06:43:55 +08:00
|
|
|
// of the loop.
|
|
|
|
if (I != end()) {
|
2013-10-11 05:28:43 +08:00
|
|
|
if (I->start == S->end && I->valno == V2) {
|
|
|
|
S->end = I->end;
|
|
|
|
segments.erase(I);
|
|
|
|
I = S+1;
|
2006-08-25 06:43:55 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-08-13 04:01:23 +08:00
|
|
|
|
2010-07-26 09:49:41 +08:00
|
|
|
// Now that V1 is dead, remove it.
|
|
|
|
markValNoForDeletion(V1);
|
2010-08-13 04:01:23 +08:00
|
|
|
|
2009-02-03 06:42:01 +08:00
|
|
|
return V2;
|
2006-08-25 06:43:55 +08:00
|
|
|
}
|
|
|
|
|
2015-02-07 02:42:41 +08:00
|
|
|
void LiveRange::flushSegmentSet() {
|
|
|
|
assert(segmentSet != nullptr && "segment set must have been created");
|
|
|
|
assert(
|
|
|
|
segments.empty() &&
|
|
|
|
"segment set can be used only initially before switching to the array");
|
|
|
|
segments.append(segmentSet->begin(), segmentSet->end());
|
|
|
|
segmentSet = nullptr;
|
|
|
|
verify();
|
|
|
|
}
|
|
|
|
|
2016-02-09 06:52:51 +08:00
|
|
|
bool LiveRange::isLiveAtIndexes(ArrayRef<SlotIndex> Slots) const {
|
|
|
|
ArrayRef<SlotIndex>::iterator SlotI = Slots.begin();
|
|
|
|
ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
|
|
|
|
|
|
|
|
// If there are no regmask slots, we have nothing to search.
|
|
|
|
if (SlotI == SlotE)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Start our search at the first segment that ends after the first slot.
|
|
|
|
const_iterator SegmentI = find(*SlotI);
|
|
|
|
const_iterator SegmentE = end();
|
|
|
|
|
|
|
|
// If there are no segments that end after the first slot, we're done.
|
|
|
|
if (SegmentI == SegmentE)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Look for each slot in the live range.
|
|
|
|
for ( ; SlotI != SlotE; ++SlotI) {
|
|
|
|
// Go to the next segment that ends after the current slot.
|
|
|
|
// The slot may be within a hole in the range.
|
|
|
|
SegmentI = advanceTo(SegmentI, *SlotI);
|
|
|
|
if (SegmentI == SegmentE)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If this segment contains the slot, we're done.
|
|
|
|
if (SegmentI->contains(*SlotI))
|
|
|
|
return true;
|
|
|
|
// Otherwise, look for the next slot.
|
|
|
|
}
|
|
|
|
|
|
|
|
// We didn't find a segment containing any of the slots.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-02-07 01:28:47 +08:00
|
|
|
void LiveInterval::freeSubRange(SubRange *S) {
|
|
|
|
S->~SubRange();
|
|
|
|
// Memory was allocated with BumpPtr allocator and is not freed here.
|
|
|
|
}
|
|
|
|
|
2014-12-10 09:12:40 +08:00
|
|
|
void LiveInterval::removeEmptySubRanges() {
|
|
|
|
SubRange **NextPtr = &SubRanges;
|
|
|
|
SubRange *I = *NextPtr;
|
|
|
|
while (I != nullptr) {
|
|
|
|
if (!I->empty()) {
|
|
|
|
NextPtr = &I->Next;
|
|
|
|
I = *NextPtr;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Skip empty subranges until we find the first nonempty one.
|
|
|
|
do {
|
2015-02-07 01:28:47 +08:00
|
|
|
SubRange *Next = I->Next;
|
|
|
|
freeSubRange(I);
|
|
|
|
I = Next;
|
2014-12-10 09:12:40 +08:00
|
|
|
} while (I != nullptr && I->empty());
|
|
|
|
*NextPtr = I;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-02-07 01:28:47 +08:00
|
|
|
void LiveInterval::clearSubRanges() {
|
|
|
|
for (SubRange *I = SubRanges, *Next; I != nullptr; I = Next) {
|
|
|
|
Next = I->Next;
|
|
|
|
freeSubRange(I);
|
|
|
|
}
|
|
|
|
SubRanges = nullptr;
|
|
|
|
}
|
|
|
|
|
2019-03-27 05:27:15 +08:00
|
|
|
/// For each VNI in \p SR, check whether or not that value defines part
|
|
|
|
/// of the mask describe by \p LaneMask and if not, remove that value
|
|
|
|
/// from \p SR.
|
|
|
|
static void stripValuesNotDefiningMask(unsigned Reg, LiveInterval::SubRange &SR,
|
|
|
|
LaneBitmask LaneMask,
|
|
|
|
const SlotIndexes &Indexes,
|
[LiveInterval] Allow updating subranges with slightly out-dated IR
During register coalescing, we update the live-intervals on-the-fly.
To do that we are in this strange mode where the live-intervals can
be slightly out-of-sync (more precisely they are forward looking)
compared to what the IR actually represents.
This happens because the register coalescer only updates the IR when
it is done with updating the live-intervals and it has to do it this
way because updating the IR on-the-fly would actually clobber some
information on how the live-ranges that are being updated look like.
This is problematic for updates that rely on the IR to accurately
represents the state of the live-ranges. Right now, we have only
one of those: stripValuesNotDefiningMask.
To reconcile this need of out-of-sync IR, this patch introduces a
new argument to LiveInterval::refineSubRanges that allows the code
doing the live range updates to reason about how the code should
look like after the coalescer will have rewritten the registers.
Essentially this captures how a subregister index with be offseted
to match its position in a new register class.
E.g., let say we want to merge:
V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>
We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
overlap, i.e., by choosing a class where we can find "offset + 1 == 3".
Put differently we align V2's sub3 with V1's sub1:
V2: sub0 sub1 sub2 sub3
V1: <offset> sub0 sub1
This offset will look like a composed subregidx in the the class:
V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
=> V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
Now if we didn't rewrite the uses and def of V1, all the checks for V1
need to account for this offset to match what the live intervals intend
to capture.
Prior to this patch, we would fail to recognize the uses and def of V1
and would end up with machine verifier errors: No live segment at def.
This could lead to miscompile as we would drop some live-ranges and
thus, miss some interferences.
For this problem to trigger, we need to reach stripValuesNotDefiningMask
while having a mismatch between the IR and the live-ranges (i.e.,
we have to apply a subreg offset to the IR.)
This requires the following three conditions:
1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1>
2. An update with Tuple registers with a possibility to coalesce the
subreg index: e.g., v1.dsub_1 == v2.dsub_3
3. Subreg liveness enabled.
looking at the IR to decide what is alive and what is not, i.e., calling
stripValuesNotDefiningMask.
coalescer maintains for the live-ranges information.
None of the targets that currently use subreg liveness (i.e., the targets
that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and
and #2, so this patch also artificial enables subreg liveness for ARM,
so that a nice test case can be attached.
2019-11-13 08:32:12 +08:00
|
|
|
const TargetRegisterInfo &TRI,
|
|
|
|
unsigned ComposeSubRegIdx) {
|
2019-03-27 05:27:15 +08:00
|
|
|
// Phys reg should not be tracked at subreg level.
|
|
|
|
// Same for noreg (Reg == 0).
|
2019-08-02 07:27:28 +08:00
|
|
|
if (!Register::isVirtualRegister(Reg) || !Reg)
|
2019-03-27 05:27:15 +08:00
|
|
|
return;
|
|
|
|
// Remove the values that don't define those lanes.
|
|
|
|
SmallVector<VNInfo *, 8> ToBeRemoved;
|
|
|
|
for (VNInfo *VNI : SR.valnos) {
|
|
|
|
if (VNI->isUnused())
|
|
|
|
continue;
|
|
|
|
// PHI definitions don't have MI attached, so there is nothing
|
|
|
|
// we can use to strip the VNI.
|
|
|
|
if (VNI->isPHIDef())
|
|
|
|
continue;
|
|
|
|
const MachineInstr *MI = Indexes.getInstructionFromIndex(VNI->def);
|
|
|
|
assert(MI && "Cannot find the definition of a value");
|
|
|
|
bool hasDef = false;
|
|
|
|
for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
|
|
|
|
if (!MOI->isReg() || !MOI->isDef())
|
|
|
|
continue;
|
|
|
|
if (MOI->getReg() != Reg)
|
|
|
|
continue;
|
[LiveInterval] Allow updating subranges with slightly out-dated IR
During register coalescing, we update the live-intervals on-the-fly.
To do that we are in this strange mode where the live-intervals can
be slightly out-of-sync (more precisely they are forward looking)
compared to what the IR actually represents.
This happens because the register coalescer only updates the IR when
it is done with updating the live-intervals and it has to do it this
way because updating the IR on-the-fly would actually clobber some
information on how the live-ranges that are being updated look like.
This is problematic for updates that rely on the IR to accurately
represents the state of the live-ranges. Right now, we have only
one of those: stripValuesNotDefiningMask.
To reconcile this need of out-of-sync IR, this patch introduces a
new argument to LiveInterval::refineSubRanges that allows the code
doing the live range updates to reason about how the code should
look like after the coalescer will have rewritten the registers.
Essentially this captures how a subregister index with be offseted
to match its position in a new register class.
E.g., let say we want to merge:
V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>
We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
overlap, i.e., by choosing a class where we can find "offset + 1 == 3".
Put differently we align V2's sub3 with V1's sub1:
V2: sub0 sub1 sub2 sub3
V1: <offset> sub0 sub1
This offset will look like a composed subregidx in the the class:
V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
=> V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
Now if we didn't rewrite the uses and def of V1, all the checks for V1
need to account for this offset to match what the live intervals intend
to capture.
Prior to this patch, we would fail to recognize the uses and def of V1
and would end up with machine verifier errors: No live segment at def.
This could lead to miscompile as we would drop some live-ranges and
thus, miss some interferences.
For this problem to trigger, we need to reach stripValuesNotDefiningMask
while having a mismatch between the IR and the live-ranges (i.e.,
we have to apply a subreg offset to the IR.)
This requires the following three conditions:
1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1>
2. An update with Tuple registers with a possibility to coalesce the
subreg index: e.g., v1.dsub_1 == v2.dsub_3
3. Subreg liveness enabled.
looking at the IR to decide what is alive and what is not, i.e., calling
stripValuesNotDefiningMask.
coalescer maintains for the live-ranges information.
None of the targets that currently use subreg liveness (i.e., the targets
that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and
and #2, so this patch also artificial enables subreg liveness for ARM,
so that a nice test case can be attached.
2019-11-13 08:32:12 +08:00
|
|
|
LaneBitmask OrigMask = TRI.getSubRegIndexLaneMask(MOI->getSubReg());
|
|
|
|
LaneBitmask ExpectedDefMask =
|
|
|
|
ComposeSubRegIdx
|
|
|
|
? TRI.composeSubRegIndexLaneMask(ComposeSubRegIdx, OrigMask)
|
|
|
|
: OrigMask;
|
|
|
|
if ((ExpectedDefMask & LaneMask).none())
|
2019-03-27 05:27:15 +08:00
|
|
|
continue;
|
|
|
|
hasDef = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!hasDef)
|
|
|
|
ToBeRemoved.push_back(VNI);
|
|
|
|
}
|
|
|
|
for (VNInfo *VNI : ToBeRemoved)
|
|
|
|
SR.removeValNo(VNI);
|
|
|
|
|
2019-09-13 07:46:51 +08:00
|
|
|
// If the subrange is empty at this point, the MIR is invalid. Do not assert
|
|
|
|
// and let the verifier catch this case.
|
2019-03-27 05:27:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void LiveInterval::refineSubRanges(
|
|
|
|
BumpPtrAllocator &Allocator, LaneBitmask LaneMask,
|
|
|
|
std::function<void(LiveInterval::SubRange &)> Apply,
|
[LiveInterval] Allow updating subranges with slightly out-dated IR
During register coalescing, we update the live-intervals on-the-fly.
To do that we are in this strange mode where the live-intervals can
be slightly out-of-sync (more precisely they are forward looking)
compared to what the IR actually represents.
This happens because the register coalescer only updates the IR when
it is done with updating the live-intervals and it has to do it this
way because updating the IR on-the-fly would actually clobber some
information on how the live-ranges that are being updated look like.
This is problematic for updates that rely on the IR to accurately
represents the state of the live-ranges. Right now, we have only
one of those: stripValuesNotDefiningMask.
To reconcile this need of out-of-sync IR, this patch introduces a
new argument to LiveInterval::refineSubRanges that allows the code
doing the live range updates to reason about how the code should
look like after the coalescer will have rewritten the registers.
Essentially this captures how a subregister index with be offseted
to match its position in a new register class.
E.g., let say we want to merge:
V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>
We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
overlap, i.e., by choosing a class where we can find "offset + 1 == 3".
Put differently we align V2's sub3 with V1's sub1:
V2: sub0 sub1 sub2 sub3
V1: <offset> sub0 sub1
This offset will look like a composed subregidx in the the class:
V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
=> V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
Now if we didn't rewrite the uses and def of V1, all the checks for V1
need to account for this offset to match what the live intervals intend
to capture.
Prior to this patch, we would fail to recognize the uses and def of V1
and would end up with machine verifier errors: No live segment at def.
This could lead to miscompile as we would drop some live-ranges and
thus, miss some interferences.
For this problem to trigger, we need to reach stripValuesNotDefiningMask
while having a mismatch between the IR and the live-ranges (i.e.,
we have to apply a subreg offset to the IR.)
This requires the following three conditions:
1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1>
2. An update with Tuple registers with a possibility to coalesce the
subreg index: e.g., v1.dsub_1 == v2.dsub_3
3. Subreg liveness enabled.
looking at the IR to decide what is alive and what is not, i.e., calling
stripValuesNotDefiningMask.
coalescer maintains for the live-ranges information.
None of the targets that currently use subreg liveness (i.e., the targets
that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and
and #2, so this patch also artificial enables subreg liveness for ARM,
so that a nice test case can be attached.
2019-11-13 08:32:12 +08:00
|
|
|
const SlotIndexes &Indexes, const TargetRegisterInfo &TRI,
|
|
|
|
unsigned ComposeSubRegIdx) {
|
2017-03-04 03:05:34 +08:00
|
|
|
LaneBitmask ToApply = LaneMask;
|
|
|
|
for (SubRange &SR : subranges()) {
|
|
|
|
LaneBitmask SRMask = SR.LaneMask;
|
|
|
|
LaneBitmask Matching = SRMask & LaneMask;
|
|
|
|
if (Matching.none())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
SubRange *MatchingRange;
|
|
|
|
if (SRMask == Matching) {
|
|
|
|
// The subrange fits (it does not cover bits outside \p LaneMask).
|
|
|
|
MatchingRange = &SR;
|
|
|
|
} else {
|
|
|
|
// We have to split the subrange into a matching and non-matching part.
|
|
|
|
// Reduce lanemask of existing lane to non-matching part.
|
|
|
|
SR.LaneMask = SRMask & ~Matching;
|
|
|
|
// Create a new subrange for the matching part
|
|
|
|
MatchingRange = createSubRangeFrom(Allocator, Matching, SR);
|
2019-03-27 05:27:15 +08:00
|
|
|
// Now that the subrange is split in half, make sure we
|
|
|
|
// only keep in the subranges the VNIs that touch the related half.
|
2020-09-16 05:54:38 +08:00
|
|
|
stripValuesNotDefiningMask(reg(), *MatchingRange, Matching, Indexes, TRI,
|
[LiveInterval] Allow updating subranges with slightly out-dated IR
During register coalescing, we update the live-intervals on-the-fly.
To do that we are in this strange mode where the live-intervals can
be slightly out-of-sync (more precisely they are forward looking)
compared to what the IR actually represents.
This happens because the register coalescer only updates the IR when
it is done with updating the live-intervals and it has to do it this
way because updating the IR on-the-fly would actually clobber some
information on how the live-ranges that are being updated look like.
This is problematic for updates that rely on the IR to accurately
represents the state of the live-ranges. Right now, we have only
one of those: stripValuesNotDefiningMask.
To reconcile this need of out-of-sync IR, this patch introduces a
new argument to LiveInterval::refineSubRanges that allows the code
doing the live range updates to reason about how the code should
look like after the coalescer will have rewritten the registers.
Essentially this captures how a subregister index with be offseted
to match its position in a new register class.
E.g., let say we want to merge:
V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>
We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
overlap, i.e., by choosing a class where we can find "offset + 1 == 3".
Put differently we align V2's sub3 with V1's sub1:
V2: sub0 sub1 sub2 sub3
V1: <offset> sub0 sub1
This offset will look like a composed subregidx in the the class:
V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
=> V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
Now if we didn't rewrite the uses and def of V1, all the checks for V1
need to account for this offset to match what the live intervals intend
to capture.
Prior to this patch, we would fail to recognize the uses and def of V1
and would end up with machine verifier errors: No live segment at def.
This could lead to miscompile as we would drop some live-ranges and
thus, miss some interferences.
For this problem to trigger, we need to reach stripValuesNotDefiningMask
while having a mismatch between the IR and the live-ranges (i.e.,
we have to apply a subreg offset to the IR.)
This requires the following three conditions:
1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1>
2. An update with Tuple registers with a possibility to coalesce the
subreg index: e.g., v1.dsub_1 == v2.dsub_3
3. Subreg liveness enabled.
looking at the IR to decide what is alive and what is not, i.e., calling
stripValuesNotDefiningMask.
coalescer maintains for the live-ranges information.
None of the targets that currently use subreg liveness (i.e., the targets
that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and
and #2, so this patch also artificial enables subreg liveness for ARM,
so that a nice test case can be attached.
2019-11-13 08:32:12 +08:00
|
|
|
ComposeSubRegIdx);
|
2020-09-16 05:54:38 +08:00
|
|
|
stripValuesNotDefiningMask(reg(), SR, SR.LaneMask, Indexes, TRI,
|
[LiveInterval] Allow updating subranges with slightly out-dated IR
During register coalescing, we update the live-intervals on-the-fly.
To do that we are in this strange mode where the live-intervals can
be slightly out-of-sync (more precisely they are forward looking)
compared to what the IR actually represents.
This happens because the register coalescer only updates the IR when
it is done with updating the live-intervals and it has to do it this
way because updating the IR on-the-fly would actually clobber some
information on how the live-ranges that are being updated look like.
This is problematic for updates that rely on the IR to accurately
represents the state of the live-ranges. Right now, we have only
one of those: stripValuesNotDefiningMask.
To reconcile this need of out-of-sync IR, this patch introduces a
new argument to LiveInterval::refineSubRanges that allows the code
doing the live range updates to reason about how the code should
look like after the coalescer will have rewritten the registers.
Essentially this captures how a subregister index with be offseted
to match its position in a new register class.
E.g., let say we want to merge:
V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>
We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
overlap, i.e., by choosing a class where we can find "offset + 1 == 3".
Put differently we align V2's sub3 with V1's sub1:
V2: sub0 sub1 sub2 sub3
V1: <offset> sub0 sub1
This offset will look like a composed subregidx in the the class:
V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
=> V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
Now if we didn't rewrite the uses and def of V1, all the checks for V1
need to account for this offset to match what the live intervals intend
to capture.
Prior to this patch, we would fail to recognize the uses and def of V1
and would end up with machine verifier errors: No live segment at def.
This could lead to miscompile as we would drop some live-ranges and
thus, miss some interferences.
For this problem to trigger, we need to reach stripValuesNotDefiningMask
while having a mismatch between the IR and the live-ranges (i.e.,
we have to apply a subreg offset to the IR.)
This requires the following three conditions:
1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1>
2. An update with Tuple registers with a possibility to coalesce the
subreg index: e.g., v1.dsub_1 == v2.dsub_3
3. Subreg liveness enabled.
looking at the IR to decide what is alive and what is not, i.e., calling
stripValuesNotDefiningMask.
coalescer maintains for the live-ranges information.
None of the targets that currently use subreg liveness (i.e., the targets
that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and
and #2, so this patch also artificial enables subreg liveness for ARM,
so that a nice test case can be attached.
2019-11-13 08:32:12 +08:00
|
|
|
ComposeSubRegIdx);
|
2017-03-04 03:05:34 +08:00
|
|
|
}
|
|
|
|
Apply(*MatchingRange);
|
|
|
|
ToApply &= ~Matching;
|
|
|
|
}
|
|
|
|
// Create a new subrange if there are uncovered bits left.
|
|
|
|
if (ToApply.any()) {
|
|
|
|
SubRange *NewRange = createSubRange(Allocator, ToApply);
|
|
|
|
Apply(*NewRange);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-04-18 04:25:11 +08:00
|
|
|
unsigned LiveInterval::getSize() const {
|
|
|
|
unsigned Sum = 0;
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const Segment &S : segments)
|
|
|
|
Sum += S.start.distance(S.end);
|
2007-04-18 04:25:11 +08:00
|
|
|
return Sum;
|
|
|
|
}
|
|
|
|
|
2016-08-24 21:37:55 +08:00
|
|
|
void LiveInterval::computeSubRangeUndefs(SmallVectorImpl<SlotIndex> &Undefs,
|
|
|
|
LaneBitmask LaneMask,
|
|
|
|
const MachineRegisterInfo &MRI,
|
|
|
|
const SlotIndexes &Indexes) const {
|
2020-09-16 05:54:38 +08:00
|
|
|
assert(Register::isVirtualRegister(reg()));
|
|
|
|
LaneBitmask VRegMask = MRI.getMaxLaneMaskForVReg(reg());
|
2016-12-17 03:11:56 +08:00
|
|
|
assert((VRegMask & LaneMask).any());
|
2016-08-24 21:37:55 +08:00
|
|
|
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
|
2020-09-16 05:54:38 +08:00
|
|
|
for (const MachineOperand &MO : MRI.def_operands(reg())) {
|
2016-08-24 21:37:55 +08:00
|
|
|
if (!MO.isUndef())
|
|
|
|
continue;
|
|
|
|
unsigned SubReg = MO.getSubReg();
|
|
|
|
assert(SubReg != 0 && "Undef should only be set on subreg defs");
|
|
|
|
LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg);
|
|
|
|
LaneBitmask UndefMask = VRegMask & ~DefMask;
|
2016-12-17 03:11:56 +08:00
|
|
|
if ((UndefMask & LaneMask).any()) {
|
2016-08-24 21:37:55 +08:00
|
|
|
const MachineInstr &MI = *MO.getParent();
|
|
|
|
bool EarlyClobber = MO.isEarlyClobber();
|
|
|
|
SlotIndex Pos = Indexes.getInstructionIndex(MI).getRegSlot(EarlyClobber);
|
|
|
|
Undefs.push_back(Pos);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-08-25 05:21:39 +08:00
|
|
|
raw_ostream& llvm::operator<<(raw_ostream& OS, const LiveRange::Segment &S) {
|
|
|
|
return OS << '[' << S.start << ',' << S.end << ':' << S.valno->id << ')';
|
2009-07-24 18:36:58 +08:00
|
|
|
}
|
2004-07-24 10:52:23 +08:00
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2016-01-30 04:50:44 +08:00
|
|
|
LLVM_DUMP_METHOD void LiveRange::Segment::dump() const {
|
2016-07-13 01:37:44 +08:00
|
|
|
dbgs() << *this << '\n';
|
2004-07-24 01:49:16 +08:00
|
|
|
}
|
2012-09-07 03:06:06 +08:00
|
|
|
#endif
|
2004-07-24 01:49:16 +08:00
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::print(raw_ostream &OS) const {
|
2005-05-14 13:34:15 +08:00
|
|
|
if (empty())
|
2012-06-06 06:51:54 +08:00
|
|
|
OS << "EMPTY";
|
2005-05-14 13:34:15 +08:00
|
|
|
else {
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const Segment &S : segments) {
|
|
|
|
OS << S;
|
|
|
|
assert(S.valno == getValNumInfo(S.valno->id) && "Bad VNInfo");
|
2010-06-23 23:34:36 +08:00
|
|
|
}
|
2005-05-14 13:34:15 +08:00
|
|
|
}
|
2010-06-26 06:53:05 +08:00
|
|
|
|
2006-08-23 02:19:46 +08:00
|
|
|
// Print value number info.
|
2006-08-30 07:18:15 +08:00
|
|
|
if (getNumValNums()) {
|
2006-08-23 02:19:46 +08:00
|
|
|
OS << " ";
|
2007-08-28 16:28:51 +08:00
|
|
|
unsigned vnum = 0;
|
|
|
|
for (const_vni_iterator i = vni_begin(), e = vni_end(); i != e;
|
|
|
|
++i, ++vnum) {
|
2007-08-30 04:45:00 +08:00
|
|
|
const VNInfo *vni = *i;
|
2016-07-13 01:37:44 +08:00
|
|
|
if (vnum) OS << ' ';
|
|
|
|
OS << vnum << '@';
|
2009-06-18 05:01:20 +08:00
|
|
|
if (vni->isUnused()) {
|
2016-07-13 01:37:44 +08:00
|
|
|
OS << 'x';
|
2006-08-23 02:19:46 +08:00
|
|
|
} else {
|
2010-09-25 20:04:16 +08:00
|
|
|
OS << vni->def;
|
2010-10-06 02:48:57 +08:00
|
|
|
if (vni->isPHIDef())
|
2012-08-04 04:19:44 +08:00
|
|
|
OS << "-phi";
|
2007-08-08 07:49:57 +08:00
|
|
|
}
|
2006-08-23 02:19:46 +08:00
|
|
|
}
|
|
|
|
}
|
2004-07-24 01:49:16 +08:00
|
|
|
}
|
2004-07-24 10:52:23 +08:00
|
|
|
|
2016-07-13 01:37:44 +08:00
|
|
|
void LiveInterval::SubRange::print(raw_ostream &OS) const {
|
|
|
|
OS << " L" << PrintLaneMask(LaneMask) << ' '
|
|
|
|
<< static_cast<const LiveRange&>(*this);
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:29:05 +08:00
|
|
|
void LiveInterval::print(raw_ostream &OS) const {
|
2020-09-16 05:54:38 +08:00
|
|
|
OS << printReg(reg()) << ' ';
|
2013-10-11 05:29:05 +08:00
|
|
|
super::print(OS);
|
2014-12-10 09:12:10 +08:00
|
|
|
// Print subranges
|
2016-07-13 01:37:44 +08:00
|
|
|
for (const SubRange &SR : subranges())
|
|
|
|
OS << SR;
|
2020-09-16 05:54:38 +08:00
|
|
|
OS << " weight:" << Weight;
|
2013-10-11 05:29:05 +08:00
|
|
|
}
|
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2016-01-30 04:50:44 +08:00
|
|
|
LLVM_DUMP_METHOD void LiveRange::dump() const {
|
2016-07-13 01:37:44 +08:00
|
|
|
dbgs() << *this << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
LLVM_DUMP_METHOD void LiveInterval::SubRange::dump() const {
|
|
|
|
dbgs() << *this << '\n';
|
2004-07-24 10:52:23 +08:00
|
|
|
}
|
2013-10-11 05:29:05 +08:00
|
|
|
|
2016-01-30 04:50:44 +08:00
|
|
|
LLVM_DUMP_METHOD void LiveInterval::dump() const {
|
2016-07-13 01:37:44 +08:00
|
|
|
dbgs() << *this << '\n';
|
2013-10-11 05:29:05 +08:00
|
|
|
}
|
2012-09-07 03:06:06 +08:00
|
|
|
#endif
|
2006-12-16 06:57:14 +08:00
|
|
|
|
2012-07-10 13:06:03 +08:00
|
|
|
#ifndef NDEBUG
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRange::verify() const {
|
2012-07-10 13:06:03 +08:00
|
|
|
for (const_iterator I = begin(), E = end(); I != E; ++I) {
|
|
|
|
assert(I->start.isValid());
|
|
|
|
assert(I->end.isValid());
|
|
|
|
assert(I->start < I->end);
|
2014-04-14 08:51:57 +08:00
|
|
|
assert(I->valno != nullptr);
|
2013-10-11 05:28:47 +08:00
|
|
|
assert(I->valno->id < valnos.size());
|
2012-07-10 13:06:03 +08:00
|
|
|
assert(I->valno == valnos[I->valno->id]);
|
2014-03-02 20:27:27 +08:00
|
|
|
if (std::next(I) != E) {
|
|
|
|
assert(I->end <= std::next(I)->start);
|
|
|
|
if (I->end == std::next(I)->start)
|
|
|
|
assert(I->valno != std::next(I)->valno);
|
2012-07-10 13:06:03 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2014-12-10 09:12:10 +08:00
|
|
|
|
|
|
|
void LiveInterval::verify(const MachineRegisterInfo *MRI) const {
|
|
|
|
super::verify();
|
|
|
|
|
|
|
|
// Make sure SubRanges are fine and LaneMasks are disjunct.
|
2016-12-15 22:36:06 +08:00
|
|
|
LaneBitmask Mask;
|
2020-09-16 05:54:38 +08:00
|
|
|
LaneBitmask MaxMask = MRI != nullptr ? MRI->getMaxLaneMaskForVReg(reg())
|
2016-12-15 22:36:06 +08:00
|
|
|
: LaneBitmask::getAll();
|
2014-12-11 08:59:06 +08:00
|
|
|
for (const SubRange &SR : subranges()) {
|
2014-12-10 09:12:10 +08:00
|
|
|
// Subrange lanemask should be disjunct to any previous subrange masks.
|
2016-12-15 22:36:06 +08:00
|
|
|
assert((Mask & SR.LaneMask).none());
|
2014-12-11 08:59:06 +08:00
|
|
|
Mask |= SR.LaneMask;
|
2014-12-10 09:12:10 +08:00
|
|
|
|
|
|
|
// subrange mask should not contained in maximum lane mask for the vreg.
|
2016-12-15 22:36:06 +08:00
|
|
|
assert((Mask & ~MaxMask).none());
|
2015-07-17 02:55:35 +08:00
|
|
|
// empty subranges must be removed.
|
|
|
|
assert(!SR.empty());
|
2014-12-10 09:12:10 +08:00
|
|
|
|
2014-12-11 08:59:06 +08:00
|
|
|
SR.verify();
|
2014-12-10 09:12:10 +08:00
|
|
|
// Main liverange should cover subrange.
|
2014-12-11 08:59:06 +08:00
|
|
|
assert(covers(SR));
|
2014-12-10 09:12:10 +08:00
|
|
|
}
|
|
|
|
}
|
2012-07-10 13:06:03 +08:00
|
|
|
#endif
|
|
|
|
|
2013-02-21 02:18:12 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// LiveRangeUpdater class
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// The LiveRangeUpdater class always maintains these invariants:
|
|
|
|
//
|
|
|
|
// - When LastStart is invalid, Spills is empty and the iterators are invalid.
|
|
|
|
// This is the initial state, and the state created by flush().
|
|
|
|
// In this state, isDirty() returns false.
|
|
|
|
//
|
|
|
|
// Otherwise, segments are kept in three separate areas:
|
|
|
|
//
|
2013-10-11 05:28:47 +08:00
|
|
|
// 1. [begin; WriteI) at the front of LR.
|
|
|
|
// 2. [ReadI; end) at the back of LR.
|
2013-02-21 02:18:12 +08:00
|
|
|
// 3. Spills.
|
|
|
|
//
|
2013-10-11 05:28:47 +08:00
|
|
|
// - LR.begin() <= WriteI <= ReadI <= LR.end().
|
2013-02-21 02:18:12 +08:00
|
|
|
// - Segments in all three areas are fully ordered and coalesced.
|
|
|
|
// - Segments in area 1 precede and can't coalesce with segments in area 2.
|
|
|
|
// - Segments in Spills precede and can't coalesce with segments in area 2.
|
|
|
|
// - No coalescing is possible between segments in Spills and segments in area
|
|
|
|
// 1, and there are no overlapping segments.
|
|
|
|
//
|
|
|
|
// The segments in Spills are not ordered with respect to the segments in area
|
|
|
|
// 1. They need to be merged.
|
|
|
|
//
|
|
|
|
// When they exist, Spills.back().start <= LastStart,
|
|
|
|
// and WriteI[-1].start <= LastStart.
|
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2013-02-21 02:18:12 +08:00
|
|
|
void LiveRangeUpdater::print(raw_ostream &OS) const {
|
|
|
|
if (!isDirty()) {
|
2013-10-11 05:28:47 +08:00
|
|
|
if (LR)
|
|
|
|
OS << "Clean updater: " << *LR << '\n';
|
2013-02-21 02:18:12 +08:00
|
|
|
else
|
|
|
|
OS << "Null updater.\n";
|
|
|
|
return;
|
|
|
|
}
|
2013-10-11 05:28:47 +08:00
|
|
|
assert(LR && "Can't have null LR in dirty updater.");
|
|
|
|
OS << " updater with gap = " << (ReadI - WriteI)
|
2013-02-21 02:18:12 +08:00
|
|
|
<< ", last start = " << LastStart
|
|
|
|
<< ":\n Area 1:";
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const auto &S : make_range(LR->begin(), WriteI))
|
|
|
|
OS << ' ' << S;
|
2013-02-21 02:18:12 +08:00
|
|
|
OS << "\n Spills:";
|
|
|
|
for (unsigned I = 0, E = Spills.size(); I != E; ++I)
|
|
|
|
OS << ' ' << Spills[I];
|
|
|
|
OS << "\n Area 2:";
|
2014-12-11 07:07:54 +08:00
|
|
|
for (const auto &S : make_range(ReadI, LR->end()))
|
|
|
|
OS << ' ' << S;
|
2013-02-21 02:18:12 +08:00
|
|
|
OS << '\n';
|
|
|
|
}
|
|
|
|
|
2016-01-30 04:50:44 +08:00
|
|
|
LLVM_DUMP_METHOD void LiveRangeUpdater::dump() const {
|
2013-02-21 02:18:12 +08:00
|
|
|
print(errs());
|
|
|
|
}
|
2017-01-28 10:02:38 +08:00
|
|
|
#endif
|
2013-02-21 02:18:12 +08:00
|
|
|
|
|
|
|
// Determine if A and B should be coalesced.
|
2013-10-11 05:28:47 +08:00
|
|
|
static inline bool coalescable(const LiveRange::Segment &A,
|
|
|
|
const LiveRange::Segment &B) {
|
2013-10-11 05:28:43 +08:00
|
|
|
assert(A.start <= B.start && "Unordered live segments.");
|
2013-02-21 02:18:12 +08:00
|
|
|
if (A.end == B.start)
|
|
|
|
return A.valno == B.valno;
|
|
|
|
if (A.end < B.start)
|
|
|
|
return false;
|
|
|
|
assert(A.valno == B.valno && "Cannot overlap different values");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
void LiveRangeUpdater::add(LiveRange::Segment Seg) {
|
|
|
|
assert(LR && "Cannot add to a null destination");
|
2013-02-21 02:18:12 +08:00
|
|
|
|
2015-02-07 02:42:41 +08:00
|
|
|
// Fall back to the regular add method if the live range
|
|
|
|
// is using the segment set instead of the segment vector.
|
|
|
|
if (LR->segmentSet != nullptr) {
|
|
|
|
LR->addSegmentToSet(Seg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-02-21 02:18:12 +08:00
|
|
|
// Flush the state if Start moves backwards.
|
|
|
|
if (!LastStart.isValid() || LastStart > Seg.start) {
|
|
|
|
if (isDirty())
|
|
|
|
flush();
|
|
|
|
// This brings us to an uninitialized state. Reinitialize.
|
|
|
|
assert(Spills.empty() && "Leftover spilled segments");
|
2013-10-11 05:28:47 +08:00
|
|
|
WriteI = ReadI = LR->begin();
|
2013-02-21 02:18:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Remember start for next time.
|
|
|
|
LastStart = Seg.start;
|
|
|
|
|
|
|
|
// Advance ReadI until it ends after Seg.start.
|
2013-10-11 05:28:47 +08:00
|
|
|
LiveRange::iterator E = LR->end();
|
2013-02-21 02:18:12 +08:00
|
|
|
if (ReadI != E && ReadI->end <= Seg.start) {
|
|
|
|
// First try to close the gap between WriteI and ReadI with spills.
|
|
|
|
if (ReadI != WriteI)
|
|
|
|
mergeSpills();
|
|
|
|
// Then advance ReadI.
|
|
|
|
if (ReadI == WriteI)
|
2013-10-11 05:28:47 +08:00
|
|
|
ReadI = WriteI = LR->find(Seg.start);
|
2013-02-21 02:18:12 +08:00
|
|
|
else
|
|
|
|
while (ReadI != E && ReadI->end <= Seg.start)
|
|
|
|
*WriteI++ = *ReadI++;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(ReadI == E || ReadI->end > Seg.start);
|
|
|
|
|
|
|
|
// Check if the ReadI segment begins early.
|
|
|
|
if (ReadI != E && ReadI->start <= Seg.start) {
|
|
|
|
assert(ReadI->valno == Seg.valno && "Cannot overlap different values");
|
|
|
|
// Bail if Seg is completely contained in ReadI.
|
|
|
|
if (ReadI->end >= Seg.end)
|
|
|
|
return;
|
|
|
|
// Coalesce into Seg.
|
|
|
|
Seg.start = ReadI->start;
|
|
|
|
++ReadI;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Coalesce as much as possible from ReadI into Seg.
|
|
|
|
while (ReadI != E && coalescable(Seg, *ReadI)) {
|
|
|
|
Seg.end = std::max(Seg.end, ReadI->end);
|
|
|
|
++ReadI;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Try coalescing Spills.back() into Seg.
|
|
|
|
if (!Spills.empty() && coalescable(Spills.back(), Seg)) {
|
|
|
|
Seg.start = Spills.back().start;
|
|
|
|
Seg.end = std::max(Spills.back().end, Seg.end);
|
|
|
|
Spills.pop_back();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Try coalescing Seg into WriteI[-1].
|
2013-10-11 05:28:47 +08:00
|
|
|
if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) {
|
2013-02-21 02:18:12 +08:00
|
|
|
WriteI[-1].end = std::max(WriteI[-1].end, Seg.end);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Seg doesn't coalesce with anything, and needs to be inserted somewhere.
|
|
|
|
if (WriteI != ReadI) {
|
|
|
|
*WriteI++ = Seg;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
// Finally, append to LR or Spills.
|
2013-02-21 02:18:12 +08:00
|
|
|
if (WriteI == E) {
|
2013-10-11 05:28:47 +08:00
|
|
|
LR->segments.push_back(Seg);
|
|
|
|
WriteI = ReadI = LR->end();
|
2013-02-21 02:18:12 +08:00
|
|
|
} else
|
|
|
|
Spills.push_back(Seg);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Merge as many spilled segments as possible into the gap between WriteI
|
|
|
|
// and ReadI. Advance WriteI to reflect the inserted instructions.
|
|
|
|
void LiveRangeUpdater::mergeSpills() {
|
|
|
|
// Perform a backwards merge of Spills and [SpillI;WriteI).
|
|
|
|
size_t GapSize = ReadI - WriteI;
|
|
|
|
size_t NumMoved = std::min(Spills.size(), GapSize);
|
2013-10-11 05:28:47 +08:00
|
|
|
LiveRange::iterator Src = WriteI;
|
|
|
|
LiveRange::iterator Dst = Src + NumMoved;
|
|
|
|
LiveRange::iterator SpillSrc = Spills.end();
|
|
|
|
LiveRange::iterator B = LR->begin();
|
2013-02-21 02:18:12 +08:00
|
|
|
|
|
|
|
// This is the new WriteI position after merging spills.
|
|
|
|
WriteI = Dst;
|
|
|
|
|
|
|
|
// Now merge Src and Spills backwards.
|
|
|
|
while (Src != Dst) {
|
|
|
|
if (Src != B && Src[-1].start > SpillSrc[-1].start)
|
|
|
|
*--Dst = *--Src;
|
|
|
|
else
|
|
|
|
*--Dst = *--SpillSrc;
|
|
|
|
}
|
|
|
|
assert(NumMoved == size_t(Spills.end() - SpillSrc));
|
|
|
|
Spills.erase(SpillSrc, Spills.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
void LiveRangeUpdater::flush() {
|
|
|
|
if (!isDirty())
|
|
|
|
return;
|
|
|
|
// Clear the dirty state.
|
|
|
|
LastStart = SlotIndex();
|
|
|
|
|
2013-10-11 05:28:47 +08:00
|
|
|
assert(LR && "Cannot add to a null destination");
|
2013-02-21 02:18:12 +08:00
|
|
|
|
|
|
|
// Nothing to merge?
|
|
|
|
if (Spills.empty()) {
|
2013-10-11 05:28:47 +08:00
|
|
|
LR->segments.erase(WriteI, ReadI);
|
|
|
|
LR->verify();
|
2013-02-21 02:18:12 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Resize the WriteI - ReadI gap to match Spills.
|
|
|
|
size_t GapSize = ReadI - WriteI;
|
|
|
|
if (GapSize < Spills.size()) {
|
|
|
|
// The gap is too small. Make some room.
|
2013-10-11 05:28:47 +08:00
|
|
|
size_t WritePos = WriteI - LR->begin();
|
|
|
|
LR->segments.insert(ReadI, Spills.size() - GapSize, LiveRange::Segment());
|
2013-02-21 02:18:12 +08:00
|
|
|
// This also invalidated ReadI, but it is recomputed below.
|
2013-10-11 05:28:47 +08:00
|
|
|
WriteI = LR->begin() + WritePos;
|
2013-02-21 02:18:12 +08:00
|
|
|
} else {
|
|
|
|
// Shrink the gap if necessary.
|
2013-10-11 05:28:47 +08:00
|
|
|
LR->segments.erase(WriteI + Spills.size(), ReadI);
|
2013-02-21 02:18:12 +08:00
|
|
|
}
|
|
|
|
ReadI = WriteI + Spills.size();
|
|
|
|
mergeSpills();
|
2013-10-11 05:28:47 +08:00
|
|
|
LR->verify();
|
2013-02-21 02:18:12 +08:00
|
|
|
}
|
|
|
|
|
2016-01-08 09:16:35 +08:00
|
|
|
unsigned ConnectedVNInfoEqClasses::Classify(const LiveRange &LR) {
|
2010-10-09 05:19:28 +08:00
|
|
|
// Create initial equivalence classes.
|
2011-03-17 08:23:45 +08:00
|
|
|
EqClass.clear();
|
2016-01-08 09:16:35 +08:00
|
|
|
EqClass.grow(LR.getNumValNums());
|
2010-10-09 05:19:28 +08:00
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
const VNInfo *used = nullptr, *unused = nullptr;
|
2010-10-30 01:37:29 +08:00
|
|
|
|
2010-10-09 05:19:28 +08:00
|
|
|
// Determine connections.
|
2016-01-08 09:16:35 +08:00
|
|
|
for (const VNInfo *VNI : LR.valnos) {
|
2010-10-30 01:37:29 +08:00
|
|
|
// Group all unused values into one class.
|
|
|
|
if (VNI->isUnused()) {
|
|
|
|
if (unused)
|
2011-03-17 08:23:45 +08:00
|
|
|
EqClass.join(unused->id, VNI->id);
|
2010-10-30 01:37:29 +08:00
|
|
|
unused = VNI;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
used = VNI;
|
2010-10-08 07:34:34 +08:00
|
|
|
if (VNI->isPHIDef()) {
|
2011-03-17 08:23:45 +08:00
|
|
|
const MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
|
2010-10-08 07:34:34 +08:00
|
|
|
assert(MBB && "Phi-def has no defining MBB");
|
|
|
|
// Connect to values live out of predecessors.
|
2021-02-14 12:41:39 +08:00
|
|
|
for (MachineBasicBlock *Pred : MBB->predecessors())
|
|
|
|
if (const VNInfo *PVNI = LR.getVNInfoBefore(LIS.getMBBEndIdx(Pred)))
|
2011-03-17 08:23:45 +08:00
|
|
|
EqClass.join(VNI->id, PVNI->id);
|
2010-10-08 07:34:34 +08:00
|
|
|
} else {
|
|
|
|
// Normal value defined by an instruction. Check for two-addr redef.
|
|
|
|
// FIXME: This could be coincidental. Should we really check for a tied
|
|
|
|
// operand constraint?
|
2010-12-21 08:48:17 +08:00
|
|
|
// Note that VNI->def may be a use slot for an early clobber def.
|
2016-01-08 09:16:35 +08:00
|
|
|
if (const VNInfo *UVNI = LR.getVNInfoBefore(VNI->def))
|
2011-03-17 08:23:45 +08:00
|
|
|
EqClass.join(VNI->id, UVNI->id);
|
2010-10-08 07:34:34 +08:00
|
|
|
}
|
|
|
|
}
|
2010-10-30 01:37:29 +08:00
|
|
|
|
|
|
|
// Lump all the unused values in with the last used value.
|
|
|
|
if (used && unused)
|
2011-03-17 08:23:45 +08:00
|
|
|
EqClass.join(used->id, unused->id);
|
2010-10-30 01:37:29 +08:00
|
|
|
|
2011-03-17 08:23:45 +08:00
|
|
|
EqClass.compress();
|
|
|
|
return EqClass.getNumClasses();
|
2010-10-08 07:34:34 +08:00
|
|
|
}
|
|
|
|
|
2015-09-22 11:44:41 +08:00
|
|
|
void ConnectedVNInfoEqClasses::Distribute(LiveInterval &LI, LiveInterval *LIV[],
|
2011-03-17 08:23:45 +08:00
|
|
|
MachineRegisterInfo &MRI) {
|
|
|
|
// Rewrite instructions.
|
2021-02-22 11:58:07 +08:00
|
|
|
for (MachineOperand &MO :
|
|
|
|
llvm::make_early_inc_range(MRI.reg_operands(LI.reg()))) {
|
|
|
|
MachineInstr *MI = MO.getParent();
|
Update DBG_VALUE register operand during LiveInterval operations
Summary:
Handling of DBG_VALUE in ConnectedVNInfoEqClasses::Distribute() was fixed in
PR16110. However DBG_VALUE register operands are not getting updated. This
patch properly resolves the value location.
Reviewers: MatzeB, vsk
Reviewed By: MatzeB
Subscribers: kparzysz, thegameg, vsk, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D48994
llvm-svn: 340310
2018-08-22 01:48:28 +08:00
|
|
|
const VNInfo *VNI;
|
|
|
|
if (MI->isDebugValue()) {
|
|
|
|
// DBG_VALUE instructions don't have slot indexes, so get the index of
|
|
|
|
// the instruction before them. The value is defined there too.
|
|
|
|
SlotIndex Idx = LIS.getSlotIndexes()->getIndexBefore(*MI);
|
|
|
|
VNI = LI.Query(Idx).valueOut();
|
|
|
|
} else {
|
|
|
|
SlotIndex Idx = LIS.getInstructionIndex(*MI);
|
|
|
|
LiveQueryResult LRQ = LI.Query(Idx);
|
|
|
|
VNI = MO.readsReg() ? LRQ.valueIn() : LRQ.valueDefined();
|
|
|
|
}
|
2012-07-26 01:15:15 +08:00
|
|
|
// In the case of an <undef> use that isn't tied to any def, VNI will be
|
|
|
|
// NULL. If the use is tied to a def, VNI will be the defined value.
|
2012-05-19 13:25:50 +08:00
|
|
|
if (!VNI)
|
|
|
|
continue;
|
2015-09-22 11:44:41 +08:00
|
|
|
if (unsigned EqClass = getEqClass(VNI))
|
2020-09-16 05:54:38 +08:00
|
|
|
MO.setReg(LIV[EqClass - 1]->reg());
|
2011-03-17 08:23:45 +08:00
|
|
|
}
|
|
|
|
|
2015-09-23 06:37:42 +08:00
|
|
|
// Distribute subregister liveranges.
|
|
|
|
if (LI.hasSubRanges()) {
|
|
|
|
unsigned NumComponents = EqClass.getNumClasses();
|
|
|
|
SmallVector<unsigned, 8> VNIMapping;
|
|
|
|
SmallVector<LiveInterval::SubRange*, 8> SubRanges;
|
|
|
|
BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
|
|
|
|
for (LiveInterval::SubRange &SR : LI.subranges()) {
|
|
|
|
// Create new subranges in the split intervals and construct a mapping
|
|
|
|
// for the VNInfos in the subrange.
|
|
|
|
unsigned NumValNos = SR.valnos.size();
|
|
|
|
VNIMapping.clear();
|
|
|
|
VNIMapping.reserve(NumValNos);
|
|
|
|
SubRanges.clear();
|
|
|
|
SubRanges.resize(NumComponents-1, nullptr);
|
|
|
|
for (unsigned I = 0; I < NumValNos; ++I) {
|
|
|
|
const VNInfo &VNI = *SR.valnos[I];
|
2016-03-25 05:41:38 +08:00
|
|
|
unsigned ComponentNum;
|
|
|
|
if (VNI.isUnused()) {
|
|
|
|
ComponentNum = 0;
|
|
|
|
} else {
|
|
|
|
const VNInfo *MainRangeVNI = LI.getVNInfoAt(VNI.def);
|
|
|
|
assert(MainRangeVNI != nullptr
|
|
|
|
&& "SubRange def must have corresponding main range def");
|
|
|
|
ComponentNum = getEqClass(MainRangeVNI);
|
|
|
|
if (ComponentNum > 0 && SubRanges[ComponentNum-1] == nullptr) {
|
|
|
|
SubRanges[ComponentNum-1]
|
|
|
|
= LIV[ComponentNum-1]->createSubRange(Allocator, SR.LaneMask);
|
|
|
|
}
|
2015-09-23 06:37:42 +08:00
|
|
|
}
|
2016-03-25 05:41:38 +08:00
|
|
|
VNIMapping.push_back(ComponentNum);
|
2015-09-23 06:37:42 +08:00
|
|
|
}
|
|
|
|
DistributeRange(SR, SubRanges.data(), VNIMapping);
|
2010-10-08 07:34:34 +08:00
|
|
|
}
|
2015-09-23 06:37:42 +08:00
|
|
|
LI.removeEmptySubRanges();
|
2010-10-08 07:34:34 +08:00
|
|
|
}
|
2015-09-23 06:37:42 +08:00
|
|
|
|
|
|
|
// Distribute main liverange.
|
|
|
|
DistributeRange(LI, LIV, EqClass);
|
2010-10-08 07:34:34 +08:00
|
|
|
}
|