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llvm-project/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll

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Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
define void @coproc(i8* %i) nounwind {
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
entry:
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
%1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
[ARM] Add cdp intrinsic tests. - Renamed intrinsics.ll to intrinsics-coprocessor.ll as all the tests were testing coprocessor instructions, also made the test checks match the full instruction. Differential Revision: http://reviews.llvm.org/D20393 llvm-svn: 270057
2016-05-19 20:59:17 +08:00
; CHECK: cdp p7, #3, c1, c1, c1, #5
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
[ARM] Add cdp intrinsic tests. - Renamed intrinsics.ll to intrinsics-coprocessor.ll as all the tests were testing coprocessor instructions, also made the test checks match the full instruction. Differential Revision: http://reviews.llvm.org/D20393 llvm-svn: 270057
2016-05-19 20:59:17 +08:00
; CHECK: cdp2 p7, #3, c1, c1, c1, #5
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
; CHECK: ldc p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
; CHECK: stc p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
; CHECK: stcl p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
ret void
}
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 20:39:30 +08:00
declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
declare void @llvm.arm.stc(i32, i32, i8*) nounwind
declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-04 01:29:22 +08:00
declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind