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llvm-project/llvm/lib/CodeGen/RegAllocBasic.cpp

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This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
//===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the RABasic function pass, which provides a minimal
// implementation of the basic register allocator.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "regalloc"
Switch AllocationOrder to using RegisterClassInfo instead of a BitVector of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
2011-06-04 04:34:53 +08:00
#include "RegAllocBase.h"
Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy. llvm-svn: 128935
2011-04-06 05:40:37 +08:00
#include "LiveDebugVariables.h"
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
#include "LiveIntervalUnion.h"
Change the Spiller interface to take a LiveRangeEdit reference. This makes it possible to register delegates and get callbacks when the spiller edits live ranges. llvm-svn: 127389
2011-03-10 09:51:42 +08:00
#include "LiveRangeEdit.h"
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
#include "RenderMachineFunction.h"
#include "Spiller.h"
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
#include "VirtRegMap.h"
Switch LiveIntervalUnion from std::set to IntervalMap. This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes way faster. llvm-svn: 121201
2010-12-08 07:18:47 +08:00
#include "llvm/ADT/OwningPtr.h"
Add basic register allocator statistics. llvm-svn: 125789
2011-02-18 06:53:48 +08:00
#include "llvm/ADT/Statistic.h"
Check TRI->getReservedRegs because other allocators do it. Even though it makes no sense for allocation_order iterators to visit reserved regs. The inline spiller depends on AliasAnalysis. Manage the Query state to avoid uninitialized or stale results. llvm-svn: 118800
2010-11-12 01:46:29 +08:00
#include "llvm/Analysis/AliasAnalysis.h"
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
#include "llvm/Function.h"
#include "llvm/PassAnalysisSupport.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
#include "llvm/Target/TargetRegisterInfo.h"
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
#ifndef NDEBUG
#include "llvm/ADT/SparseBitVector.h"
#endif
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
#include "llvm/Support/Debug.h"
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
#include "llvm/Support/ErrorHandling.h"
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
#include "llvm/Support/raw_ostream.h"
Add named timer groups for the different stages of register allocation. llvm-svn: 121604
2010-12-11 08:19:56 +08:00
#include "llvm/Support/Timer.h"
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
Switch LiveIntervalUnion from std::set to IntervalMap. This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes way faster. llvm-svn: 121201
2010-12-08 07:18:47 +08:00
#include <cstdlib>
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
#include <queue>
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
using namespace llvm;
Add basic register allocator statistics. llvm-svn: 125789
2011-02-18 06:53:48 +08:00
STATISTIC(NumAssigned , "Number of registers assigned");
STATISTIC(NumUnassigned , "Number of registers unassigned");
STATISTIC(NumNewQueued , "Number of new live ranges queued");
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
createBasicRegisterAllocator);
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
// Temporary verification option until we can put verification inside
// MachineVerifier.
Make the -verify-regalloc command line option available to base classes as RegAllocBase::VerifyEnabled. Run the machine code verifier in a few interesting places during RegAllocGreedy. llvm-svn: 122107
2010-12-18 07:16:35 +08:00
static cl::opt<bool, true>
VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
cl::desc("Verify during register allocation"));
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
Add named timer groups for the different stages of register allocation. llvm-svn: 121604
2010-12-11 08:19:56 +08:00
const char *RegAllocBase::TimerGroupName = "Register Allocation";
Make the -verify-regalloc command line option available to base classes as RegAllocBase::VerifyEnabled. Run the machine code verifier in a few interesting places during RegAllocGreedy. llvm-svn: 122107
2010-12-18 07:16:35 +08:00
bool RegAllocBase::VerifyEnabled = false;
Add named timer groups for the different stages of register allocation. llvm-svn: 121604
2010-12-11 08:19:56 +08:00
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
namespace {
struct CompSpillWeight {
bool operator()(LiveInterval *A, LiveInterval *B) const {
return A->weight < B->weight;
}
};
}
Namespacify. llvm-svn: 120146
2010-11-26 00:42:51 +08:00
namespace {
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
/// RABasic provides a minimal implementation of the basic register allocation
/// algorithm. It prioritizes live virtual registers by spill weight and spills
/// whenever a register is unavailable. This is not practical in production but
/// provides a useful baseline both for measuring other allocators and comparing
/// the speed of the basic algorithm against other styles of allocators.
class RABasic : public MachineFunctionPass, public RegAllocBase
{
// context
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
MachineFunction *MF;
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
// analyses
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
LiveStacks *LS;
RenderMachineFunction *RMF;
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
// state
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
std::auto_ptr<Spiller> SpillerInstance;
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
CompSpillWeight> Queue;
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
public:
RABasic();
/// Return the pass name.
virtual const char* getPassName() const {
return "Basic Register Allocator";
}
/// RABasic analysis usage.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
virtual void releaseMemory();
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
virtual Spiller &spiller() { return *SpillerInstance; }
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
Store (priority,regnum) pairs in the priority queue instead of providing an abstract priority queue interface in subclasses that want to override the priority calculations. Subclasses must provide a getPriority() implementation instead. This approach requires less code as long as priorities are expressable as simple floats, and it avoids the dangers of defining potentially expensive priority comparison functions. It also should speed up priority_queue operations since they no longer have to chase pointers when comparing registers. This is not measurable, though. Preferably, we shouldn't use floats to guide code generation. The use of floats here is derived from the use of floats for spill weights. Spill weights have a dynamic range that doesn't lend itself easily to a fixpoint implementation. When someone invents a stable spill weight representation, it can be reused for allocation priorities. llvm-svn: 121294
2010-12-09 06:22:41 +08:00
virtual float getPriority(LiveInterval *LI) { return LI->weight; }
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
virtual void enqueue(LiveInterval *LI) {
Queue.push(LI);
}
virtual LiveInterval *dequeue() {
if (Queue.empty())
return 0;
LiveInterval *LI = Queue.top();
Queue.pop();
return LI;
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
virtual unsigned selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs);
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
/// Perform register allocation.
virtual bool runOnMachineFunction(MachineFunction &mf);
static char ID;
};
char RABasic::ID = 0;
} // end anonymous namespace
RABasic::RABasic(): MachineFunctionPass(ID) {
Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy. llvm-svn: 128935
2011-04-06 05:40:37 +08:00
initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
There is only one register coalescer. Merge it into the base class and remove the analysis group. llvm-svn: 133899
2011-06-27 06:34:10 +08:00
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
Let RegAllocBasic require MachineDominators - they are already available and splitting needs them. llvm-svn: 118194
2010-11-04 04:39:26 +08:00
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<AliasAnalysis>();
AU.addPreserved<AliasAnalysis>();
AU.addRequired<LiveIntervals>();
AU.addPreserved<SlotIndexes>();
Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy. llvm-svn: 128935
2011-04-06 05:40:37 +08:00
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
if (StrongPHIElim)
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
AU.addRequiredID(StrongPHIEliminationID);
Refer to the RegisterCoalescer pass by ID. A public interface is no longer needed since RegisterCoalescer is not an analysis any more. llvm-svn: 137082
2011-08-09 08:29:53 +08:00
AU.addRequiredTransitiveID(RegisterCoalescerPassID);
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
AU.addRequired<CalculateSpillWeights>();
AU.addRequired<LiveStacks>();
AU.addPreserved<LiveStacks>();
AU.addRequiredID(MachineDominatorsID);
AU.addPreservedID(MachineDominatorsID);
AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineLoopInfo>();
AU.addRequired<VirtRegMap>();
AU.addPreserved<VirtRegMap>();
DEBUG(AU.addRequired<RenderMachineFunction>());
MachineFunctionPass::getAnalysisUsage(AU);
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
void RABasic::releaseMemory() {
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
SpillerInstance.reset(0);
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
RegAllocBase::releaseMemory();
}
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
#ifndef NDEBUG
// Verify each LiveIntervalUnion.
void RegAllocBase::verify() {
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
LiveVirtRegBitSet VisitedVRegs;
OwningArrayPtr<LiveVirtRegBitSet>
unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
// Verify disjoint unions.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
Use TRI::printReg instead of AbstractRegisterDescription when printing LiveIntervalUnions. llvm-svn: 121781
2010-12-15 02:53:47 +08:00
DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
PhysReg2LiveUnion[PhysReg].verify(VRegs);
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
// Union + intersection test could be done efficiently in one pass, but
// don't add a method to SparseBitVector unless we really need it.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
VisitedVRegs |= VRegs;
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
// Verify vreg coverage.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
liItr != liEnd; ++liItr) {
unsigned reg = liItr->first;
if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
if (!VRM->hasPhys(reg)) continue; // spilled?
unsigned PhysReg = VRM->getPhys(reg);
if (!unionVRegs[PhysReg].test(reg)) {
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
dbgs() << "LiveVirtReg " << reg << " not in union " <<
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
TRI->getName(PhysReg) << "\n";
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
llvm_unreachable("unallocated live vreg");
}
}
// FIXME: I'm not sure how to verify spilled intervals.
}
#endif //!NDEBUG
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
//===----------------------------------------------------------------------===//
// RegAllocBase Implementation
//===----------------------------------------------------------------------===//
// Instantiate a LiveIntervalUnion for each physical register.
Switch LiveIntervalUnion from std::set to IntervalMap. This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes way faster. llvm-svn: 121201
2010-12-08 07:18:47 +08:00
void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
unsigned NRegs) {
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
NumRegs = NRegs;
Switch LiveIntervalUnion from std::set to IntervalMap. This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes way faster. llvm-svn: 121201
2010-12-08 07:18:47 +08:00
Array =
static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
for (unsigned r = 0; r != NRegs; ++r)
new(Array + r) LiveIntervalUnion(r, allocator);
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
Move MRI into RegAllocBase. Clean up debug output a bit. llvm-svn: 121599
2010-12-11 07:49:00 +08:00
void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
Add named timer groups for the different stages of register allocation. llvm-svn: 121604
2010-12-11 08:19:56 +08:00
NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
Move MRI into RegAllocBase. Clean up debug output a bit. llvm-svn: 121599
2010-12-11 07:49:00 +08:00
TRI = &vrm.getTargetRegInfo();
MRI = &vrm.getRegInfo();
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
VRM = &vrm;
LIS = &lis;
Switch AllocationOrder to using RegisterClassInfo instead of a BitVector of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
2011-06-04 04:34:53 +08:00
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
Reuse live interval union between functions. This saves a bit of compile time when compiling many small functions. llvm-svn: 129321
2011-04-12 07:57:14 +08:00
const unsigned NumRegs = TRI->getNumRegs();
if (NumRegs != PhysReg2LiveUnion.numRegs()) {
PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
// Cache an interferece query for each physical reg
Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
}
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
void RegAllocBase::LiveUnionArray::clear() {
Switch LiveIntervalUnion from std::set to IntervalMap. This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes way faster. llvm-svn: 121201
2010-12-08 07:18:47 +08:00
if (!Array)
return;
for (unsigned r = 0; r != NumRegs; ++r)
Array[r].~LiveIntervalUnion();
free(Array);
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
NumRegs = 0;
Switch LiveIntervalUnion from std::set to IntervalMap. This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes way faster. llvm-svn: 121201
2010-12-08 07:18:47 +08:00
Array = 0;
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
void RegAllocBase::releaseMemory() {
Reuse live interval union between functions. This saves a bit of compile time when compiling many small functions. llvm-svn: 129321
2011-04-12 07:57:14 +08:00
for (unsigned r = 0, e = PhysReg2LiveUnion.numRegs(); r != e; ++r)
PhysReg2LiveUnion[r].clear();
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
// Visit all the live registers. If they are already assigned to a physical
// register, unify them with the corresponding LiveIntervalUnion, otherwise push
// them on the priority queue for later assignment.
void RegAllocBase::seedLiveRegs() {
Time the initial seeding of live registers llvm-svn: 129276
2011-04-11 23:00:42 +08:00
NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
unsigned RegNum = I->first;
LiveInterval &VirtReg = *I->second;
Store (priority,regnum) pairs in the priority queue instead of providing an abstract priority queue interface in subclasses that want to override the priority calculations. Subclasses must provide a getPriority() implementation instead. This approach requires less code as long as priorities are expressable as simple floats, and it avoids the dangers of defining potentially expensive priority comparison functions. It also should speed up priority_queue operations since they no longer have to chase pointers when comparing registers. This is not measurable, though. Preferably, we shouldn't use floats to guide code generation. The use of floats here is derived from the use of floats for spill weights. Spill weights have a dynamic range that doesn't lend itself easily to a fixpoint implementation. When someone invents a stable spill weight representation, it can be reused for allocation priorities. llvm-svn: 121294
2010-12-09 06:22:41 +08:00
if (TargetRegisterInfo::isPhysicalRegister(RegNum))
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
PhysReg2LiveUnion[RegNum].unify(VirtReg);
Store (priority,regnum) pairs in the priority queue instead of providing an abstract priority queue interface in subclasses that want to override the priority calculations. Subclasses must provide a getPriority() implementation instead. This approach requires less code as long as priorities are expressable as simple floats, and it avoids the dangers of defining potentially expensive priority comparison functions. It also should speed up priority_queue operations since they no longer have to chase pointers when comparing registers. This is not measurable, though. Preferably, we shouldn't use floats to guide code generation. The use of floats here is derived from the use of floats for spill weights. Spill weights have a dynamic range that doesn't lend itself easily to a fixpoint implementation. When someone invents a stable spill weight representation, it can be reused for allocation priorities. llvm-svn: 121294
2010-12-09 06:22:41 +08:00
else
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
enqueue(&VirtReg);
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
}
}
Evict a lighter single interference before attempting to split a live range. Registers are not allocated strictly in spill weight order when live range splitting and spilling has created new shorter intervals with higher spill weights. When one of the new heavy intervals conflicts with a single lighter interval, simply evict the old interval instead of trying to split the heavy one. The lighter interval is a better candidate for splitting, it has a smaller use density. llvm-svn: 125151
2011-02-09 09:14:03 +08:00
void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
Trim debugging output. llvm-svn: 125802
2011-02-18 08:32:47 +08:00
DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
<< " to " << PrintReg(PhysReg, TRI) << '\n');
Evict a lighter single interference before attempting to split a live range. Registers are not allocated strictly in spill weight order when live range splitting and spilling has created new shorter intervals with higher spill weights. When one of the new heavy intervals conflicts with a single lighter interval, simply evict the old interval instead of trying to split the heavy one. The lighter interval is a better candidate for splitting, it has a smaller use density. llvm-svn: 125151
2011-02-09 09:14:03 +08:00
assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
Prefer cheap registers for busy live ranges. On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
2011-04-21 02:19:48 +08:00
MRI->setPhysRegUsed(PhysReg);
Evict a lighter single interference before attempting to split a live range. Registers are not allocated strictly in spill weight order when live range splitting and spilling has created new shorter intervals with higher spill weights. When one of the new heavy intervals conflicts with a single lighter interval, simply evict the old interval instead of trying to split the heavy one. The lighter interval is a better candidate for splitting, it has a smaller use density. llvm-svn: 125151
2011-02-09 09:14:03 +08:00
PhysReg2LiveUnion[PhysReg].unify(VirtReg);
Add basic register allocator statistics. llvm-svn: 125789
2011-02-18 06:53:48 +08:00
++NumAssigned;
Evict a lighter single interference before attempting to split a live range. Registers are not allocated strictly in spill weight order when live range splitting and spilling has created new shorter intervals with higher spill weights. When one of the new heavy intervals conflicts with a single lighter interval, simply evict the old interval instead of trying to split the heavy one. The lighter interval is a better candidate for splitting, it has a smaller use density. llvm-svn: 125151
2011-02-09 09:14:03 +08:00
}
void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
Trim debugging output. llvm-svn: 125802
2011-02-18 08:32:47 +08:00
DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
<< " from " << PrintReg(PhysReg, TRI) << '\n');
Evict a lighter single interference before attempting to split a live range. Registers are not allocated strictly in spill weight order when live range splitting and spilling has created new shorter intervals with higher spill weights. When one of the new heavy intervals conflicts with a single lighter interval, simply evict the old interval instead of trying to split the heavy one. The lighter interval is a better candidate for splitting, it has a smaller use density. llvm-svn: 125151
2011-02-09 09:14:03 +08:00
assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
PhysReg2LiveUnion[PhysReg].extract(VirtReg);
VRM->clearVirt(VirtReg.reg);
Add basic register allocator statistics. llvm-svn: 125789
2011-02-18 06:53:48 +08:00
++NumUnassigned;
Evict a lighter single interference before attempting to split a live range. Registers are not allocated strictly in spill weight order when live range splitting and spilling has created new shorter intervals with higher spill weights. When one of the new heavy intervals conflicts with a single lighter interval, simply evict the old interval instead of trying to split the heavy one. The lighter interval is a better candidate for splitting, it has a smaller use density. llvm-svn: 125151
2011-02-09 09:14:03 +08:00
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// Top-level driver to manage the queue of unassigned VirtRegs and call the
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
// selectOrSplit implementation.
void RegAllocBase::allocatePhysRegs() {
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
seedLiveRegs();
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// Continue assigning vregs one at a time to available physical registers.
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
while (LiveInterval *VirtReg = dequeue()) {
Allow the allocation of empty live ranges that have uses. Empty ranges may represent undef values. llvm-svn: 128144
2011-03-23 12:32:51 +08:00
assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
Spill multiple registers at once. Live range splitting can create a number of small live ranges containing only a single real use. Spill these small live ranges along with the large range they are connected to with copies. This enables memory operand folding and maximizes the spill to fill distance. Work in progress with known bugs. llvm-svn: 127529
2011-03-12 12:17:20 +08:00
// Unused registers can appear when the spiller coalesces snippets.
if (MRI->reg_nodbg_empty(VirtReg->reg)) {
DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
LIS->removeInterval(VirtReg->reg);
continue;
}
Tag cached interference with a user-provided tag instead of the virtual register number. The live range of a virtual register may change which invalidates the cached interference information. llvm-svn: 127772
2011-03-17 06:56:11 +08:00
// Invalidate all interference queries, live ranges could have changed.
Fix PR9883. Make sure all caches are invalidated when a live range is repaired. The previous invalidation missed the alias interference caches. Also add a stats counter for the number of repaired ranges. llvm-svn: 131133
2011-05-11 01:37:41 +08:00
invalidateVirtRegs();
Tag cached interference with a user-provided tag instead of the virtual register number. The live range of a virtual register may change which invalidates the cached interference information. llvm-svn: 127772
2011-03-17 06:56:11 +08:00
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// selectOrSplit requests the allocator to return an available physical
// register if possible and populate a list of new live intervals that
// result from splitting.
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
DEBUG(dbgs() << "\nselectOrSplit "
<< MRI->getRegClass(VirtReg->reg)->getName()
<< ':' << *VirtReg << '\n');
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
typedef SmallVector<LiveInterval*, 4> VirtRegVec;
VirtRegVec SplitVRegs;
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
Emit a proper error message when register allocators run out of registers. This can't be just an assertion, users can always write impossible inline assembly. Such an assembly statement should be included in the error message. llvm-svn: 131024
2011-05-07 05:58:30 +08:00
if (AvailablePhysReg == ~0u) {
// selectOrSplit failed to find a register!
Better diagnostics when inline asm fails to allocate. asm.c:2:7: error: ran out of registers during register allocation asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9)); ^ llvm-svn: 134310
2011-07-02 15:17:37 +08:00
const char *Msg = "ran out of registers during register allocation";
// Probably caused by an inline asm.
MachineInstr *MI;
Emit a proper error message when register allocators run out of registers. This can't be just an assertion, users can always write impossible inline assembly. Such an assembly statement should be included in the error message. llvm-svn: 131024
2011-05-07 05:58:30 +08:00
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
Better diagnostics when inline asm fails to allocate. asm.c:2:7: error: ran out of registers during register allocation asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9)); ^ llvm-svn: 134310
2011-07-02 15:17:37 +08:00
(MI = I.skipInstruction());)
if (MI->isInlineAsm())
break;
if (MI)
MI->emitError(Msg);
else
report_fatal_error(Msg);
// Keep going after reporting the error.
VRM->assignVirt2Phys(VirtReg->reg,
RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
continue;
Emit a proper error message when register allocators run out of registers. This can't be just an assertion, users can always write impossible inline assembly. Such an assembly statement should be included in the error message. llvm-svn: 131024
2011-05-07 05:58:30 +08:00
}
Trim debugging output. llvm-svn: 125802
2011-02-18 08:32:47 +08:00
if (AvailablePhysReg)
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
assign(*VirtReg, AvailablePhysReg);
Trim debugging output. llvm-svn: 125802
2011-02-18 08:32:47 +08:00
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
I != E; ++I) {
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
LiveInterval *SplitVirtReg = *I;
Allow the allocation of empty live ranges that have uses. Empty ranges may represent undef values. llvm-svn: 128144
2011-03-23 12:32:51 +08:00
assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
LIS->removeInterval(SplitVirtReg->reg);
continue;
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
"expect split value in virtual register");
Change the RAGreedy register assignment order so large live ranges are allocated first. This is based on the observation that long live ranges are more difficult to allocate, so there is a better chance of solving the puzzle by handling the big pieces first. The allocator will evict and split long alive ranges when they get in the way. RABasic is still using spill weights for its priority queue, so the interface to the queue has been virtualized. llvm-svn: 126259
2011-02-23 07:01:52 +08:00
enqueue(SplitVirtReg);
Add basic register allocator statistics. llvm-svn: 125789
2011-02-18 06:53:48 +08:00
++NumNewQueued;
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
}
}
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// Check if this live virtual register interferes with a physical register. If
// not, then check for interference on each register that aliases with the
// physical register. Return the interfering register.
unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
unsigned PhysReg) {
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet. llvm-svn: 121801
2010-12-15 07:10:48 +08:00
for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
if (query(VirtReg, *AliasI).checkInterference())
return *AliasI;
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
return 0;
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// Helper for spillInteferences() that spills all interfering vregs currently
// assigned to this physical register.
void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
assert(Q.seenAllInterferences() && "need collectInterferences()");
const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
E = PendingSpills.end(); I != E; ++I) {
LiveInterval &SpilledVReg = **I;
Check TRI->getReservedRegs because other allocators do it. Even though it makes no sense for allocation_order iterators to visit reserved regs. The inline spiller depends on AliasAnalysis. Manage the Query state to avoid uninitialized or stale results. llvm-svn: 118800
2010-11-12 01:46:29 +08:00
DEBUG(dbgs() << "extracting from " <<
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// Deallocate the interfering vreg by removing it from the union.
// A LiveInterval instance may not be in a union during modification!
Evict a lighter single interference before attempting to split a live range. Registers are not allocated strictly in spill weight order when live range splitting and spilling has created new shorter intervals with higher spill weights. When one of the new heavy intervals conflicts with a single lighter interval, simply evict the old interval instead of trying to split the heavy one. The lighter interval is a better candidate for splitting, it has a smaller use density. llvm-svn: 125151
2011-02-09 09:14:03 +08:00
unassign(SpilledVReg, PhysReg);
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// Spill the extracted interval.
Change the Spiller interface to take a LiveRangeEdit reference. This makes it possible to register delegates and get callbacks when the spiller edits live ranges. llvm-svn: 127389
2011-03-10 09:51:42 +08:00
LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
spiller().spill(LRE);
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
}
Check TRI->getReservedRegs because other allocators do it. Even though it makes no sense for allocation_order iterators to visit reserved regs. The inline spiller depends on AliasAnalysis. Manage the Query state to avoid uninitialized or stale results. llvm-svn: 118800
2010-11-12 01:46:29 +08:00
// After extracting segments, the query's results are invalid. But keep the
// contents valid until we're done accessing pendingSpills.
Q.clear();
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// Spill or split all live virtual registers currently unified under PhysReg
// that interfere with VirtReg. The newly spilled or split live intervals are
// returned by appending them to SplitVRegs.
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
bool
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// Record each interference and determine if all are spillable before mutating
// either the union or live intervals.
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet. llvm-svn: 121801
2010-12-15 07:10:48 +08:00
unsigned NumInterferences = 0;
Check TRI->getReservedRegs because other allocators do it. Even though it makes no sense for allocation_order iterators to visit reserved regs. The inline spiller depends on AliasAnalysis. Manage the Query state to avoid uninitialized or stale results. llvm-svn: 118800
2010-11-12 01:46:29 +08:00
// Collect interferences assigned to any alias of the physical register.
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet. llvm-svn: 121801
2010-12-15 07:10:48 +08:00
for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
NumInterferences += QAlias.collectInterferingVRegs();
Check TRI->getReservedRegs because other allocators do it. Even though it makes no sense for allocation_order iterators to visit reserved regs. The inline spiller depends on AliasAnalysis. Manage the Query state to avoid uninitialized or stale results. llvm-svn: 118800
2010-11-12 01:46:29 +08:00
if (QAlias.seenUnspillableVReg()) {
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
return false;
}
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
}
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
" interferences with " << VirtReg << "\n");
assert(NumInterferences > 0 && "expect interference");
// Spill each interfering vreg allocated to PhysReg or an alias.
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet. llvm-svn: 121801
2010-12-15 07:10:48 +08:00
for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
spillReg(VirtReg, *AliasI, SplitVRegs);
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
return true;
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
Move RABasic::addMBBLiveIns to the base class, it is generally useful. Minor optimization to the use of IntervalMap iterators. They are fairly heavyweight, so prefer SI.valid() over SI != end(). llvm-svn: 121217
2010-12-08 09:06:06 +08:00
// Add newly allocated physical registers to the MBB live in sets.
void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
Add named timer groups for the different stages of register allocation. llvm-svn: 121604
2010-12-11 08:19:56 +08:00
NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
Use a faster algorithm for computing MBB live-in registers after register allocation. LiveIntervals::findLiveInMBBs has to do a full binary search for each segment. llvm-svn: 129292
2011-04-12 04:01:41 +08:00
SlotIndexes *Indexes = LIS->getSlotIndexes();
if (MF->size() <= 1)
return;
Move RABasic::addMBBLiveIns to the base class, it is generally useful. Minor optimization to the use of IntervalMap iterators. They are fairly heavyweight, so prefer SI.valid() over SI != end(). llvm-svn: 121217
2010-12-08 09:06:06 +08:00
Use a faster algorithm for computing MBB live-in registers after register allocation. LiveIntervals::findLiveInMBBs has to do a full binary search for each segment. llvm-svn: 129292
2011-04-12 04:01:41 +08:00
LiveIntervalUnion::SegmentIter SI;
Move RABasic::addMBBLiveIns to the base class, it is generally useful. Minor optimization to the use of IntervalMap iterators. They are fairly heavyweight, so prefer SI.valid() over SI != end(). llvm-svn: 121217
2010-12-08 09:06:06 +08:00
for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
if (LiveUnion.empty())
continue;
Print out the MBB live-in registers. llvm-svn: 136178
2011-07-27 07:12:08 +08:00
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " live-in:");
Use a faster algorithm for computing MBB live-in registers after register allocation. LiveIntervals::findLiveInMBBs has to do a full binary search for each segment. llvm-svn: 129292
2011-04-12 04:01:41 +08:00
MachineFunction::iterator MBB = llvm::next(MF->begin());
MachineFunction::iterator MFE = MF->end();
SlotIndex Start, Stop;
tie(Start, Stop) = Indexes->getMBBRange(MBB);
SI.setMap(LiveUnion.getMap());
SI.find(Start);
while (SI.valid()) {
if (SI.start() <= Start) {
if (!MBB->isLiveIn(PhysReg))
MBB->addLiveIn(PhysReg);
Print out the MBB live-in registers. llvm-svn: 136178
2011-07-27 07:12:08 +08:00
DEBUG(dbgs() << "\tBB#" << MBB->getNumber() << ':'
<< PrintReg(SI.value()->reg, TRI));
Use a faster algorithm for computing MBB live-in registers after register allocation. LiveIntervals::findLiveInMBBs has to do a full binary search for each segment. llvm-svn: 129292
2011-04-12 04:01:41 +08:00
} else if (SI.start() > Stop)
Fix a bug in RegAllocBase::addMBBLiveIns() where a basic block could accidentally be skipped. llvm-svn: 129373
2011-04-13 02:11:28 +08:00
MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex());
Use a faster algorithm for computing MBB live-in registers after register allocation. LiveIntervals::findLiveInMBBs has to do a full binary search for each segment. llvm-svn: 129292
2011-04-12 04:01:41 +08:00
if (++MBB == MFE)
break;
tie(Start, Stop) = Indexes->getMBBRange(MBB);
SI.advanceTo(Start);
Move RABasic::addMBBLiveIns to the base class, it is generally useful. Minor optimization to the use of IntervalMap iterators. They are fairly heavyweight, so prefer SI.valid() over SI != end(). llvm-svn: 121217
2010-12-08 09:06:06 +08:00
}
Print out the MBB live-in registers. llvm-svn: 136178
2011-07-27 07:12:08 +08:00
DEBUG(dbgs() << '\n');
Move RABasic::addMBBLiveIns to the base class, it is generally useful. Minor optimization to the use of IntervalMap iterators. They are fairly heavyweight, so prefer SI.valid() over SI != end(). llvm-svn: 121217
2010-12-08 09:06:06 +08:00
}
}
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
//===----------------------------------------------------------------------===//
// RABasic Implementation
//===----------------------------------------------------------------------===//
// Driver for the register assignment and splitting heuristics.
// Manages iteration over the LiveIntervalUnions.
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
//
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// This is a minimal implementation of register assignment and splitting that
// spills whenever we run out of registers.
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
//
// selectOrSplit can only be called once per live virtual register. We then do a
// single interference test for each register the correct class until we find an
// available register. So, the number of interference tests in the worst case is
// |vregs| * |machineregs|. And since the number of interference tests is
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// minimal, there is no value in caching them outside the scope of
// selectOrSplit().
unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// Populate a list of physical register spill candidates.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
SmallVector<unsigned, 8> PhysRegSpillCands;
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
// Check for an available register in this class.
Switch AllocationOrder to using RegisterClassInfo instead of a BitVector of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
2011-06-04 04:34:53 +08:00
ArrayRef<unsigned> Order =
RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
++I) {
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
unsigned PhysReg = *I;
// Check interference and as a side effect, intialize queries for this
// VirtReg and its aliases.
unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
if (interfReg == 0) {
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// Found an available register.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
return PhysReg;
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
Privatize an unused part of the LiveIntervalUnion::Query interface. No clients are iterating over interference overlaps. llvm-svn: 137350
2011-08-12 05:00:42 +08:00
Queries[interfReg].collectInterferingVRegs(1);
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
LiveInterval *interferingVirtReg =
Privatize an unused part of the LiveIntervalUnion::Query interface. No clients are iterating over interference overlaps. llvm-svn: 137350
2011-08-12 05:00:42 +08:00
Queries[interfReg].interferingVRegs().front();
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
Added register reassignment prototype to RAGreedy. It's a simple heuristic to reshuffle register assignments when we can't find an available reg. llvm-svn: 121388
2010-12-10 02:15:21 +08:00
// The current VirtReg must either be spillable, or one of its interferences
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// must have less spill weight.
if (interferingVirtReg->weight < VirtReg.weight ) {
PhysRegSpillCands.push_back(PhysReg);
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
}
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
}
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// Try to spill another interfering reg with less spill weight.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
Simplify assertion. llvm-svn: 121162
2010-12-08 02:51:27 +08:00
assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
"Interference after spill.");
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// Tell the caller to allocate to this newly freed physical register.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
return *PhysRegI;
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
}
Emit a proper error message when register allocators run out of registers. This can't be just an assertion, users can always write impossible inline assembly. Such an assembly statement should be included in the error message. llvm-svn: 131024
2011-05-07 05:58:30 +08:00
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// No other spill candidates were found, so spill the current VirtReg.
DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
Emit a proper error message when register allocators run out of registers. This can't be just an assertion, users can always write impossible inline assembly. Such an assembly statement should be included in the error message. llvm-svn: 131024
2011-05-07 05:58:30 +08:00
if (!VirtReg.isSpillable())
return ~0u;
Change the Spiller interface to take a LiveRangeEdit reference. This makes it possible to register delegates and get callbacks when the spiller edits live ranges. llvm-svn: 127389
2011-03-10 09:51:42 +08:00
LiveRangeEdit LRE(VirtReg, SplitVRegs);
spiller().spill(LRE);
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. llvm-svn: 118701
2010-11-11 03:18:47 +08:00
// The live virtual register requesting allocation was spilled, so tell
// the caller not to allocate anything during this round.
return 0;
Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
2010-11-09 02:02:08 +08:00
}
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
<< "********** Function: "
<< ((Value*)mf.getFunction())->getName() << '\n');
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
MF = &mf;
DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
Check TRI->getReservedRegs because other allocators do it. Even though it makes no sense for allocation_order iterators to visit reserved regs. The inline spiller depends on AliasAnalysis. Manage the Query state to avoid uninitialized or stale results. llvm-svn: 118800
2010-11-12 01:46:29 +08:00
Move MRI into RegAllocBase. Clean up debug output a bit. llvm-svn: 121599
2010-12-11 07:49:00 +08:00
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
The basic register allocator must also use the inline spiller. It is using a trivial rewriter that doesn't know how to insert spill code requested by the standard spiller. llvm-svn: 128688
2011-04-01 07:02:17 +08:00
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
allocatePhysRegs();
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
Move RABasic::addMBBLiveIns to the base class, it is generally useful. Minor optimization to the use of IntervalMap iterators. They are fairly heavyweight, so prefer SI.valid() over SI != end(). llvm-svn: 121217
2010-12-08 09:06:06 +08:00
addMBBLiveIns(MF);
RABasic fix. Regalloc is responsible for updating block live ins. llvm-svn: 119896
2010-11-20 10:57:05 +08:00
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
// Diagnostic output before rewriting
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
// optional HTML output
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
// FIXME: Verification currently must run before VirtRegRewriter. We should
// make the rewriter a separate pass and override verifyAnalysis instead. When
// that happens, verification naturally falls under VerifyMachineCode.
#ifndef NDEBUG
Make the -verify-regalloc command line option available to base classes as RegAllocBase::VerifyEnabled. Run the machine code verifier in a few interesting places during RegAllocGreedy. llvm-svn: 122107
2010-12-18 07:16:35 +08:00
if (VerifyEnabled) {
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
// Verify accuracy of LiveIntervals. The standard machine code verifier
// ensures that each LiveIntervals covers all uses of the virtual reg.
Coding style. No significant functionality. Abandon linear scan style in favor of the widespread llvm style. Capitalize variables and add newlines for visual parsing. Rename variables for readability. And other cleanup. llvm-svn: 120490
2010-12-01 07:18:47 +08:00
// FIXME: MachineVerifier is badly broken when using the standard
// spiller. Always use -spiller=inline with -verify-regalloc. Even with the
// inline spiller, some tests fail to verify because the coalescer does not
// always generate verifiable code.
Pass a Banner argument to the machine code verifier both from createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. llvm-svn: 122113
2010-12-18 08:06:56 +08:00
MF->verify(this, "In RABasic::verify");
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
Adds RABasic verification and tracing. (retry now that the windows build is green) llvm-svn: 118630
2010-11-10 05:04:34 +08:00
// Verify that LiveIntervals are partitioned into unions and disjoint within
// the unions.
verify();
}
#endif // !NDEBUG
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
// Run rewriter
Add VirtRegMap::rewrite() and use it in the new register allocators. The rewriter works almost identically to -rewriter=trivial, except it also eliminates any identity copies. This makes the new register allocators independent of VirtRegRewriter.cpp which will be going away at the same time as RegAllocLinearScan. llvm-svn: 125967
2011-02-19 06:03:18 +08:00
VRM->rewrite(LIS->getSlotIndexes());
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy. llvm-svn: 128935
2011-04-06 05:40:37 +08:00
// Write out new DBG_VALUE instructions.
getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
Jakob's review of the basic register allocator. llvm-svn: 117384
2010-10-27 02:34:01 +08:00
// The pass output is in VirtRegMap. Release all the transient data.
releaseMemory();
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
return true;
}
Whitespace. llvm-svn: 119895
2010-11-20 10:43:55 +08:00
FunctionPass* llvm::createBasicRegisterAllocator()
This is a prototype of an experimental register allocation framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
2010-10-23 07:09:15 +08:00
{
return new RABasic();
}