forked from OSchip/llvm-project
28 lines
893 B
LLVM
28 lines
893 B
LLVM
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; RUN: llc -march=hexagon -O3 < %s
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; REQUIRES: asserts
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; Test that the compiler doesn't assert when attempting to
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; generate a store absolute set insturction where the base
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; register and destination register are same.
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target triple = "hexagon-unknown--elf"
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%s.0 = type { %s.1, %s.2 }
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%s.1 = type { %s.1*, %s.1* }
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%s.2 = type { %s.3 }
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%s.3 = type { %s.4 }
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%s.4 = type { %s.5, i32, i32, i8* }
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%s.5 = type { i32 }
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@g0 = external global %s.0, align 4
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; Function Attrs: nounwind
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define void @f0() #0 section ".init.text" {
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b0:
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store %s.1* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0), %s.1** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0, i32 0), align 4
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store %s.1* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0), %s.1** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0, i32 1), align 4
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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