forked from OSchip/llvm-project
75 lines
2.1 KiB
LLVM
75 lines
2.1 KiB
LLVM
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; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; This test checks if redundant conditional branches are removed.
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; CHECK: memub
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; CHECK: memub
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; CHECK: memub
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; CHECK-NOT: if{{.*}}jump .LBB
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; CHECK: cmp.eq
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target triple = "hexagon-unknown--elf"
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; Function Attrs: nounwind
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declare void @f0() #0
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; Function Attrs: nounwind
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define void @f1(i8* nocapture readonly %a0, i32 %a1) #0 {
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b0:
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br i1 undef, label %b8, label %b1
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b1: ; preds = %b0
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tail call void @f0() #0
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br i1 false, label %b8, label %b2
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b2: ; preds = %b1
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%v0 = getelementptr inbounds i8, i8* %a0, i32 undef
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%v1 = sub i32 0, %a1
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%v2 = icmp eq i32 undef, undef
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br label %b3
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b3: ; preds = %b6, %b2
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%v3 = phi i8* [ undef, %b2 ], [ %v17, %b6 ]
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%v4 = phi i8* [ %v0, %b2 ], [ null, %b6 ]
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%v5 = phi i32 [ 1, %b2 ], [ 0, %b6 ]
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br i1 %v2, label %b4, label %b5
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b4: ; preds = %b3
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%v6 = load i8, i8* %v3, align 1
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br label %b6
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b5: ; preds = %b3
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%v7 = load i8, i8* %v4, align 1
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%v8 = zext i8 %v7 to i32
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%v9 = getelementptr inbounds i8, i8* %v4, i32 %v1
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%v10 = load i8, i8* %v9, align 1
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%v11 = zext i8 %v10 to i32
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%v12 = sub nsw i32 %v8, %v11
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br label %b6
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b6: ; preds = %b5, %b4
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%v13 = phi i8 [ 0, %b5 ], [ %v6, %b4 ]
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%v14 = phi i32 [ %v12, %b5 ], [ 0, %b4 ]
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%v15 = zext i8 %v13 to i32
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%v16 = mul nsw i32 %v14, %v14
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%v17 = getelementptr inbounds i8, i8* %v3, i32 1
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%v18 = sub nsw i32 0, %v15
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%v19 = mul nsw i32 %v18, %v18
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%v20 = add nuw i32 %v16, 0
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%v21 = add i32 %v20, 0
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%v22 = add i32 %v21, 0
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%v23 = lshr i32 %v22, 1
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%v24 = add nuw nsw i32 %v23, %v19
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%v25 = add nsw i32 %v24, 0
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store i32 %v25, i32* null, align 4
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%v26 = icmp eq i32 %v5, undef
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br i1 %v26, label %b7, label %b3
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b7: ; preds = %b6
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unreachable
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b8: ; preds = %b1, %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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