forked from OSchip/llvm-project
273 lines
6.6 KiB
LLVM
273 lines
6.6 KiB
LLVM
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; RUN: llc -march=arc < %s | FileCheck %s
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; CHECK-LABEL: load32
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; CHECK: ld %r0, [%r0,16000]
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define i32 @load32(i32* %bp) nounwind {
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entry:
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%gep = getelementptr i32, i32* %bp, i32 4000
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%v = load i32, i32* %gep, align 4
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ret i32 %v
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}
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; CHECK-LABEL: load16
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; CHECK: ldh %r0, [%r0,8000]
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define i16 @load16(i16* %bp) nounwind {
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entry:
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%gep = getelementptr i16, i16* %bp, i32 4000
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%v = load i16, i16* %gep, align 2
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ret i16 %v
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}
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; CHECK-LABEL: load8
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; CHECK: ldb %r0, [%r0,4000]
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define i8 @load8(i8* %bp) nounwind {
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entry:
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%gep = getelementptr i8, i8* %bp, i32 4000
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%v = load i8, i8* %gep, align 1
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ret i8 %v
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}
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; CHECK-LABEL: sextload16
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; CHECK: ldh.x %r0, [%r0,8000]
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define i32 @sextload16(i16* %bp) nounwind {
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entry:
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%gep = getelementptr i16, i16* %bp, i32 4000
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%vl = load i16, i16* %gep, align 2
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%v = sext i16 %vl to i32
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ret i32 %v
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}
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; CHECK-LABEL: sextload8
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; CHECK: ldb.x %r0, [%r0,4000]
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define i32 @sextload8(i8* %bp) nounwind {
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entry:
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%gep = getelementptr i8, i8* %bp, i32 4000
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%vl = load i8, i8* %gep, align 1
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%v = sext i8 %vl to i32
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ret i32 %v
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}
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; CHECK-LABEL: s_sextload16
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; CHECK: ldh.x %r0, [%r0,32]
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define i32 @s_sextload16(i16* %bp) nounwind {
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entry:
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%gep = getelementptr i16, i16* %bp, i32 16
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%vl = load i16, i16* %gep, align 2
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%v = sext i16 %vl to i32
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ret i32 %v
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}
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; CHECK-LABEL: s_sextload8
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; CHECK: ldb.x %r0, [%r0,16]
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define i32 @s_sextload8(i8* %bp) nounwind {
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entry:
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%gep = getelementptr i8, i8* %bp, i32 16
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%vl = load i8, i8* %gep, align 1
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%v = sext i8 %vl to i32
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ret i32 %v
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}
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; CHECK-LABEL: store32
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; CHECK: add %r[[REG:[0-9]+]], %r1, 16000
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; CHECK: st %r0, [%r[[REG]],0]
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; Long range stores (offset does not fit in s9) must be add followed by st.
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define void @store32(i32 %val, i32* %bp) nounwind {
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entry:
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%gep = getelementptr i32, i32* %bp, i32 4000
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store i32 %val, i32* %gep, align 4
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ret void
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}
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; CHECK-LABEL: store16
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; CHECK: add %r[[REG:[0-9]+]], %r1, 8000
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; CHECK: sth %r0, [%r[[REG]],0]
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define void @store16(i16 zeroext %val, i16* %bp) nounwind {
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entry:
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%gep = getelementptr i16, i16* %bp, i32 4000
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store i16 %val, i16* %gep, align 2
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ret void
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}
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; CHECK-LABEL: store8
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; CHECK: add %r[[REG:[0-9]+]], %r1, 4000
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; CHECK: stb %r0, [%r[[REG]],0]
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define void @store8(i8 zeroext %val, i8* %bp) nounwind {
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entry:
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%gep = getelementptr i8, i8* %bp, i32 4000
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store i8 %val, i8* %gep, align 1
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ret void
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}
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; Short range stores can be done with [reg, s9].
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; CHECK-LABEL: s_store32
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; CHECK-NOT: add
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; CHECK: st %r0, [%r1,64]
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define void @s_store32(i32 %val, i32* %bp) nounwind {
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entry:
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%gep = getelementptr i32, i32* %bp, i32 16
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store i32 %val, i32* %gep, align 4
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ret void
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}
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; CHECK-LABEL: s_store16
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; CHECK-NOT: add
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; CHECK: sth %r0, [%r1,32]
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define void @s_store16(i16 zeroext %val, i16* %bp) nounwind {
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entry:
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%gep = getelementptr i16, i16* %bp, i32 16
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store i16 %val, i16* %gep, align 2
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ret void
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}
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; CHECK-LABEL: s_store8
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; CHECK-NOT: add
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; CHECK: stb %r0, [%r1,16]
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define void @s_store8(i8 zeroext %val, i8* %bp) nounwind {
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entry:
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%gep = getelementptr i8, i8* %bp, i32 16
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store i8 %val, i8* %gep, align 1
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ret void
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}
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@aaaa = internal global [128 x i32] zeroinitializer
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@bbbb = internal global [128 x i16] zeroinitializer
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@cccc = internal global [128 x i8] zeroinitializer
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; CHECK-LABEL: g_store32
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; CHECK-NOT: add
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; CHECK: st %r0, [@aaaa+64]
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define void @g_store32(i32 %val) nounwind {
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entry:
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store i32 %val, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @aaaa, i32 0, i32 16), align 4
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ret void
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}
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; CHECK-LABEL: g_load32
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; CHECK-NOT: add
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; CHECK: ld %r0, [@aaaa+64]
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define i32 @g_load32() nounwind {
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%gep = getelementptr inbounds [128 x i32], [128 x i32]* @aaaa, i32 0, i32 16
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%v = load i32, i32* %gep, align 4
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ret i32 %v
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}
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; CHECK-LABEL: g_store16
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; CHECK-NOT: add
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; CHECK: sth %r0, [@bbbb+32]
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define void @g_store16(i16 %val) nounwind {
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entry:
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store i16 %val, i16* getelementptr inbounds ([128 x i16], [128 x i16]* @bbbb, i16 0, i16 16), align 2
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ret void
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}
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; CHECK-LABEL: g_load16
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; CHECK-NOT: add
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; CHECK: ldh %r0, [@bbbb+32]
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define i16 @g_load16() nounwind {
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%gep = getelementptr inbounds [128 x i16], [128 x i16]* @bbbb, i16 0, i16 16
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%v = load i16, i16* %gep, align 2
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ret i16 %v
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}
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; CHECK-LABEL: g_store8
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; CHECK-NOT: add
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; CHECK: stb %r0, [@cccc+16]
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define void @g_store8(i8 %val) nounwind {
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entry:
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store i8 %val, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @cccc, i8 0, i8 16), align 1
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ret void
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}
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; CHECK-LABEL: g_load8
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; CHECK-NOT: add
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; CHECK: ldb %r0, [@cccc+16]
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define i8 @g_load8() nounwind {
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%gep = getelementptr inbounds [128 x i8], [128 x i8]* @cccc, i8 0, i8 16
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%v = load i8, i8* %gep, align 1
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ret i8 %v
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}
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; CHECK-LABEL: align2_load32
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; CHECK-DAG: ldh %r[[REG0:[0-9]+]], [%r0,0]
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; CHECK-DAG: ldh %r[[REG1:[0-9]+]], [%r0,2]
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; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 16
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define i32 @align2_load32(i8* %p) nounwind {
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entry:
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%bp = bitcast i8* %p to i32*
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%v = load i32, i32* %bp, align 2
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ret i32 %v
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}
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; CHECK-LABEL: align1_load32
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; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0]
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; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1]
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; CHECK-DAG: ldb %r[[REG2:[0-9]+]], [%r0,2]
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; CHECK-DAG: ldb %r[[REG3:[0-9]+]], [%r0,3]
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; CHECK-DAG: asl %r[[AREG1:[0-9]+]], %r[[REG1]], 8
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; CHECK-DAG: asl %r[[AREG3:[0-9]+]], %r[[REG3]], 8
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define i32 @align1_load32(i8* %p) nounwind {
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entry:
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%bp = bitcast i8* %p to i32*
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%v = load i32, i32* %bp, align 1
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ret i32 %v
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}
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; CHECK-LABEL: align1_load16
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; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0]
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; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1]
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; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 8
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define i16 @align1_load16(i8* %p) nounwind {
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entry:
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%bp = bitcast i8* %p to i16*
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%v = load i16, i16* %bp, align 1
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ret i16 %v
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}
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; CHECK-LABEL: align2_store32
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; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 16
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; CHECK-DAG: sth %r1, [%r0,0]
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; CHECK-DAG: sth %r[[REG:[0-9]+]], [%r0,2]
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define void @align2_store32(i8* %p, i32 %v) nounwind {
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entry:
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%bp = bitcast i8* %p to i32*
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store i32 %v, i32* %bp, align 2
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ret void
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}
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; CHECK-LABEL: align1_store16
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; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 8
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; CHECK-DAG: stb %r1, [%r0,0]
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; CHECK-DAG: stb %r[[REG:[0-9]+]], [%r0,1]
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define void @align1_store16(i8* %p, i16 %v) nounwind {
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entry:
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%bp = bitcast i8* %p to i16*
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store i16 %v, i16* %bp, align 1
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ret void
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}
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; CHECK-LABEL: align1_store32
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; CHECK-DAG: lsr %r[[REG0:[0-9]+]], %r1, 8
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; CHECK-DAG: lsr %r[[REG1:[0-9]+]], %r1, 16
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; CHECK-DAG: lsr %r[[REG2:[0-9]+]], %r1, 24
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; CHECK-DAG: stb %r1, [%r0,0]
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; CHECK-DAG: stb %r[[REG0]], [%r0,1]
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; CHECK-DAG: stb %r[[REG1]], [%r0,2]
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; CHECK-DAG: stb %r[[REG2]], [%r0,3]
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define void @align1_store32(i8* %p, i32 %v) nounwind {
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entry:
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%bp = bitcast i8* %p to i32*
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store i32 %v, i32* %bp, align 1
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ret void
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}
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