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llvm-project/llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the G4+ (7450) processor.
//
//===----------------------------------------------------------------------===//
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
def G4P_BPU : FuncUnit; // Branch unit
def G4P_SLU : FuncUnit; // Store/load unit
def G4P_SRU : FuncUnit; // special register unit
def G4P_IU1 : FuncUnit; // integer unit 1 (simple)
def G4P_IU2 : FuncUnit; // integer unit 2 (complex)
def G4P_IU3 : FuncUnit; // integer unit 3 (simple)
def G4P_IU4 : FuncUnit; // integer unit 4 (simple)
def G4P_FPU1 : FuncUnit; // floating point unit 1
def G4P_VPU : FuncUnit; // vector permutation unit
def G4P_VIU1 : FuncUnit; // vector integer unit 1 (simple)
def G4P_VIU2 : FuncUnit; // vector integer unit 2 (complex)
def G4P_VFPU : FuncUnit; // vector floating point unit
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
def G4PlusItineraries : ProcessorItineraries<
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
[G4P_IU1, G4P_IU2, G4P_IU3, G4P_IU4, G4P_BPU, G4P_SLU, G4P_FPU1,
G4P_VFPU, G4P_VIU1, G4P_VIU2, G4P_VPU], [], [
InstrItinData<IIC_IntSimple , [InstrStage<1, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_IntCompare , [InstrStage<1, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>,
InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>,
InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>,
InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>,
InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>,
InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>,
InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>,
InstrItinData<IIC_IntRotate , [InstrStage<1, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_IntShift , [InstrStage<2, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_BrB , [InstrStage<1, [G4P_BPU]>]>,
InstrItinData<IIC_BrCR , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_BrMCR , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_BrMCRX , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLoad , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G4P_SLU]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G4P_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStStore , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStDSS , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStICBI , [InstrStage<3, [G4P_IU2]>]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLFD , [InstrStage<4, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<4, [G4P_SLU]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_LdStLFDUX , [InstrStage<4, [G4P_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStLHA , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<3, [G4P_SLU]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_LdStLHAUX , [InstrStage<3, [G4P_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStLMW , [InstrStage<37, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLWA , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [G4P_SLU]>]>,
[PowerPC] Add Itineraries for STWU/STWUX etc When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8. Since there are already multiple IIC for store update, this patch also merge IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU IIC_LdStSTDUX to IIC_LdStSTUX and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference. Differential Revision: https://reviews.llvm.org/D54700 llvm-svn: 347311
2018-11-20 23:11:42 +08:00
InstrItinData<IIC_LdStSTU , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G4P_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSync , [InstrStage<35, [G4P_SLU]>]>,
InstrItinData<IIC_SprISYNC , [InstrStage<0, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_SprMFSR , [InstrStage<4, [G4P_IU2]>]>,
InstrItinData<IIC_SprMTMSR , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_SprMFCR , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G4P_IU2]>]>,
InstrItinData<IIC_SprMFSPR , [InstrStage<4, [G4P_IU2]>]>,
InstrItinData<IIC_SprMFTB , [InstrStage<5, [G4P_IU2]>]>,
InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4P_IU2]>]>,
InstrItinData<IIC_SprRFI , [InstrStage<1, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_SprSC , [InstrStage<0, [G4P_IU1, G4P_IU2,
G4P_IU3, G4P_IU4]>]>,
InstrItinData<IIC_FPGeneral , [InstrStage<5, [G4P_FPU1]>]>,
InstrItinData<IIC_FPAddSub , [InstrStage<5, [G4P_FPU1]>]>,
InstrItinData<IIC_FPCompare , [InstrStage<5, [G4P_FPU1]>]>,
InstrItinData<IIC_FPDivD , [InstrStage<35, [G4P_FPU1]>]>,
InstrItinData<IIC_FPDivS , [InstrStage<21, [G4P_FPU1]>]>,
InstrItinData<IIC_FPFused , [InstrStage<5, [G4P_FPU1]>]>,
InstrItinData<IIC_FPRes , [InstrStage<14, [G4P_FPU1]>]>,
InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4P_VIU1]>]>,
InstrItinData<IIC_VecFP , [InstrStage<4, [G4P_VFPU]>]>,
InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G4P_VFPU]>]>,
InstrItinData<IIC_VecComplex , [InstrStage<4, [G4P_VIU2]>]>,
InstrItinData<IIC_VecPerm , [InstrStage<2, [G4P_VPU]>]>,
InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4P_VIU1]>]>,
InstrItinData<IIC_VecVSL , [InstrStage<2, [G4P_VPU]>]>,
InstrItinData<IIC_VecVSR , [InstrStage<2, [G4P_VPU]>]>
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
]>;