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llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp

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Added -*- C++ -*- mode to the comments. llvm-svn: 4826
2002-11-23 06:42:50 +08:00
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
* Remove trailing whitespace * Convert tabs to spaces llvm-svn: 21426
2005-04-22 07:38:14 +08:00
//
Added LLVM project notice to the top of every C++ source file. Header files will be on the way. llvm-svn: 9298
2003-10-21 03:43:21 +08:00
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
* Remove trailing whitespace * Convert tabs to spaces llvm-svn: 21426
2005-04-22 07:38:14 +08:00
//
Added LLVM project notice to the top of every C++ source file. Header files will be on the way. llvm-svn: 9298
2003-10-21 03:43:21 +08:00
//===----------------------------------------------------------------------===//
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 06:55:53 +08:00
//
Rename MachineInstrInfo -> TargetInstrInfo llvm-svn: 5272
2003-01-15 06:00:31 +08:00
// This file contains the X86 implementation of the TargetInstrInfo class.
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 06:55:53 +08:00
//
//===----------------------------------------------------------------------===//
Rename X86InstructionInfo to X86InstrInfo llvm-svn: 4413
2002-10-30 05:05:24 +08:00
#include "X86InstrInfo.h"
* Move information about Implicit Defs/Uses into X86InstrInfo.def. * Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. llvm-svn: 4877
2002-12-03 13:42:53 +08:00
#include "X86.h"
Fix a build breaker. llvm-svn: 28574
2006-05-31 05:45:53 +08:00
#include "X86GenInstrInfo.inc"
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
#include "X86InstrBuilder.h"
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
#include "X86MachineFunctionInfo.h"
Fix a build breaker. llvm-svn: 28574
2006-05-31 05:45:53 +08:00
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
#include "llvm/DerivedTypes.h"
Add lengthof and endof templates that hide a lot of sizeof computations. Patch by Sterling Stein! llvm-svn: 41758
2007-09-07 12:06:50 +08:00
#include "llvm/ADT/STLExtras.h"
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
#include "llvm/CodeGen/MachineConstantPool.h"
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
#include "llvm/CodeGen/MachineFrameInfo.h"
Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface. llvm-svn: 6320
2003-05-24 08:09:50 +08:00
#include "llvm/CodeGen/MachineInstrBuilder.h"
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
2007-12-31 12:13:23 +08:00
#include "llvm/CodeGen/MachineRegisterInfo.h"
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
#include "llvm/CodeGen/LiveVariables.h"
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
#include "llvm/Support/CommandLine.h"
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
#include "llvm/Target/TargetOptions.h"
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
#include "llvm/Target/TargetAsmInfo.h"
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
Put all LLVM code into the llvm namespace, as per bug 109. llvm-svn: 9903
2003-11-12 06:41:34 +08:00
using namespace llvm;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
namespace {
cl::opt<bool>
NoFusing("disable-spill-fusing",
cl::desc("Disable fusing of spill code into instructions"));
cl::opt<bool>
PrintFailedFusing("print-failed-fuse-candidates",
cl::desc("Print instructions that the allocator wants to"
" fuse, but the X86 backend currently can't"),
cl::Hidden);
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now. llvm-svn: 49059
2008-04-02 07:26:12 +08:00
cl::opt<bool>
ReMatPICStubLoad("remat-pic-stub-load",
cl::desc("Re-materialize load from stub in PIC mode"),
cl::init(false), cl::Hidden);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
Fix a build breaker. llvm-svn: 28574
2006-05-31 05:45:53 +08:00
X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
Fix a problem where lib/Target/TargetInstrInfo.h would include and use a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
2008-01-01 09:03:04 +08:00
: TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
Committing X86-64 support. llvm-svn: 30177
2006-09-08 14:48:29 +08:00
TM(tm), RI(tm, *this) {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
SmallVector<unsigned,16> AmbEntries;
static const unsigned OpTbl2Addr[][2] = {
{ X86::ADC32ri, X86::ADC32mi },
{ X86::ADC32ri8, X86::ADC32mi8 },
{ X86::ADC32rr, X86::ADC32mr },
{ X86::ADC64ri32, X86::ADC64mi32 },
{ X86::ADC64ri8, X86::ADC64mi8 },
{ X86::ADC64rr, X86::ADC64mr },
{ X86::ADD16ri, X86::ADD16mi },
{ X86::ADD16ri8, X86::ADD16mi8 },
{ X86::ADD16rr, X86::ADD16mr },
{ X86::ADD32ri, X86::ADD32mi },
{ X86::ADD32ri8, X86::ADD32mi8 },
{ X86::ADD32rr, X86::ADD32mr },
{ X86::ADD64ri32, X86::ADD64mi32 },
{ X86::ADD64ri8, X86::ADD64mi8 },
{ X86::ADD64rr, X86::ADD64mr },
{ X86::ADD8ri, X86::ADD8mi },
{ X86::ADD8rr, X86::ADD8mr },
{ X86::AND16ri, X86::AND16mi },
{ X86::AND16ri8, X86::AND16mi8 },
{ X86::AND16rr, X86::AND16mr },
{ X86::AND32ri, X86::AND32mi },
{ X86::AND32ri8, X86::AND32mi8 },
{ X86::AND32rr, X86::AND32mr },
{ X86::AND64ri32, X86::AND64mi32 },
{ X86::AND64ri8, X86::AND64mi8 },
{ X86::AND64rr, X86::AND64mr },
{ X86::AND8ri, X86::AND8mi },
{ X86::AND8rr, X86::AND8mr },
{ X86::DEC16r, X86::DEC16m },
{ X86::DEC32r, X86::DEC32m },
{ X86::DEC64_16r, X86::DEC64_16m },
{ X86::DEC64_32r, X86::DEC64_32m },
{ X86::DEC64r, X86::DEC64m },
{ X86::DEC8r, X86::DEC8m },
{ X86::INC16r, X86::INC16m },
{ X86::INC32r, X86::INC32m },
{ X86::INC64_16r, X86::INC64_16m },
{ X86::INC64_32r, X86::INC64_32m },
{ X86::INC64r, X86::INC64m },
{ X86::INC8r, X86::INC8m },
{ X86::NEG16r, X86::NEG16m },
{ X86::NEG32r, X86::NEG32m },
{ X86::NEG64r, X86::NEG64m },
{ X86::NEG8r, X86::NEG8m },
{ X86::NOT16r, X86::NOT16m },
{ X86::NOT32r, X86::NOT32m },
{ X86::NOT64r, X86::NOT64m },
{ X86::NOT8r, X86::NOT8m },
{ X86::OR16ri, X86::OR16mi },
{ X86::OR16ri8, X86::OR16mi8 },
{ X86::OR16rr, X86::OR16mr },
{ X86::OR32ri, X86::OR32mi },
{ X86::OR32ri8, X86::OR32mi8 },
{ X86::OR32rr, X86::OR32mr },
{ X86::OR64ri32, X86::OR64mi32 },
{ X86::OR64ri8, X86::OR64mi8 },
{ X86::OR64rr, X86::OR64mr },
{ X86::OR8ri, X86::OR8mi },
{ X86::OR8rr, X86::OR8mr },
{ X86::ROL16r1, X86::ROL16m1 },
{ X86::ROL16rCL, X86::ROL16mCL },
{ X86::ROL16ri, X86::ROL16mi },
{ X86::ROL32r1, X86::ROL32m1 },
{ X86::ROL32rCL, X86::ROL32mCL },
{ X86::ROL32ri, X86::ROL32mi },
{ X86::ROL64r1, X86::ROL64m1 },
{ X86::ROL64rCL, X86::ROL64mCL },
{ X86::ROL64ri, X86::ROL64mi },
{ X86::ROL8r1, X86::ROL8m1 },
{ X86::ROL8rCL, X86::ROL8mCL },
{ X86::ROL8ri, X86::ROL8mi },
{ X86::ROR16r1, X86::ROR16m1 },
{ X86::ROR16rCL, X86::ROR16mCL },
{ X86::ROR16ri, X86::ROR16mi },
{ X86::ROR32r1, X86::ROR32m1 },
{ X86::ROR32rCL, X86::ROR32mCL },
{ X86::ROR32ri, X86::ROR32mi },
{ X86::ROR64r1, X86::ROR64m1 },
{ X86::ROR64rCL, X86::ROR64mCL },
{ X86::ROR64ri, X86::ROR64mi },
{ X86::ROR8r1, X86::ROR8m1 },
{ X86::ROR8rCL, X86::ROR8mCL },
{ X86::ROR8ri, X86::ROR8mi },
{ X86::SAR16r1, X86::SAR16m1 },
{ X86::SAR16rCL, X86::SAR16mCL },
{ X86::SAR16ri, X86::SAR16mi },
{ X86::SAR32r1, X86::SAR32m1 },
{ X86::SAR32rCL, X86::SAR32mCL },
{ X86::SAR32ri, X86::SAR32mi },
{ X86::SAR64r1, X86::SAR64m1 },
{ X86::SAR64rCL, X86::SAR64mCL },
{ X86::SAR64ri, X86::SAR64mi },
{ X86::SAR8r1, X86::SAR8m1 },
{ X86::SAR8rCL, X86::SAR8mCL },
{ X86::SAR8ri, X86::SAR8mi },
{ X86::SBB32ri, X86::SBB32mi },
{ X86::SBB32ri8, X86::SBB32mi8 },
{ X86::SBB32rr, X86::SBB32mr },
{ X86::SBB64ri32, X86::SBB64mi32 },
{ X86::SBB64ri8, X86::SBB64mi8 },
{ X86::SBB64rr, X86::SBB64mr },
{ X86::SHL16rCL, X86::SHL16mCL },
{ X86::SHL16ri, X86::SHL16mi },
{ X86::SHL32rCL, X86::SHL32mCL },
{ X86::SHL32ri, X86::SHL32mi },
{ X86::SHL64rCL, X86::SHL64mCL },
{ X86::SHL64ri, X86::SHL64mi },
{ X86::SHL8rCL, X86::SHL8mCL },
{ X86::SHL8ri, X86::SHL8mi },
{ X86::SHLD16rrCL, X86::SHLD16mrCL },
{ X86::SHLD16rri8, X86::SHLD16mri8 },
{ X86::SHLD32rrCL, X86::SHLD32mrCL },
{ X86::SHLD32rri8, X86::SHLD32mri8 },
{ X86::SHLD64rrCL, X86::SHLD64mrCL },
{ X86::SHLD64rri8, X86::SHLD64mri8 },
{ X86::SHR16r1, X86::SHR16m1 },
{ X86::SHR16rCL, X86::SHR16mCL },
{ X86::SHR16ri, X86::SHR16mi },
{ X86::SHR32r1, X86::SHR32m1 },
{ X86::SHR32rCL, X86::SHR32mCL },
{ X86::SHR32ri, X86::SHR32mi },
{ X86::SHR64r1, X86::SHR64m1 },
{ X86::SHR64rCL, X86::SHR64mCL },
{ X86::SHR64ri, X86::SHR64mi },
{ X86::SHR8r1, X86::SHR8m1 },
{ X86::SHR8rCL, X86::SHR8mCL },
{ X86::SHR8ri, X86::SHR8mi },
{ X86::SHRD16rrCL, X86::SHRD16mrCL },
{ X86::SHRD16rri8, X86::SHRD16mri8 },
{ X86::SHRD32rrCL, X86::SHRD32mrCL },
{ X86::SHRD32rri8, X86::SHRD32mri8 },
{ X86::SHRD64rrCL, X86::SHRD64mrCL },
{ X86::SHRD64rri8, X86::SHRD64mri8 },
{ X86::SUB16ri, X86::SUB16mi },
{ X86::SUB16ri8, X86::SUB16mi8 },
{ X86::SUB16rr, X86::SUB16mr },
{ X86::SUB32ri, X86::SUB32mi },
{ X86::SUB32ri8, X86::SUB32mi8 },
{ X86::SUB32rr, X86::SUB32mr },
{ X86::SUB64ri32, X86::SUB64mi32 },
{ X86::SUB64ri8, X86::SUB64mi8 },
{ X86::SUB64rr, X86::SUB64mr },
{ X86::SUB8ri, X86::SUB8mi },
{ X86::SUB8rr, X86::SUB8mr },
{ X86::XOR16ri, X86::XOR16mi },
{ X86::XOR16ri8, X86::XOR16mi8 },
{ X86::XOR16rr, X86::XOR16mr },
{ X86::XOR32ri, X86::XOR32mi },
{ X86::XOR32ri8, X86::XOR32mi8 },
{ X86::XOR32rr, X86::XOR32mr },
{ X86::XOR64ri32, X86::XOR64mi32 },
{ X86::XOR64ri8, X86::XOR64mi8 },
{ X86::XOR64rr, X86::XOR64mr },
{ X86::XOR8ri, X86::XOR8mi },
{ X86::XOR8rr, X86::XOR8mr }
};
for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
unsigned RegOp = OpTbl2Addr[i][0];
unsigned MemOp = OpTbl2Addr[i][1];
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
MemOp)).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
assert(false && "Duplicated entries?");
unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
std::make_pair(RegOp,
AuxInfo))).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AmbEntries.push_back(MemOp);
}
// If the third value is 1, then it's folding either a load or a store.
static const unsigned OpTbl0[][3] = {
{ X86::CALL32r, X86::CALL32m, 1 },
{ X86::CALL64r, X86::CALL64m, 1 },
{ X86::CMP16ri, X86::CMP16mi, 1 },
{ X86::CMP16ri8, X86::CMP16mi8, 1 },
Add CMP32mr and friends to the load-unfolding table. Among other things, this allows the scheduler to unfold a load operand in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully clones the comparison to avoid a pushf+popf. llvm-svn: 48777
2008-03-26 00:53:19 +08:00
{ X86::CMP16rr, X86::CMP16mr, 1 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::CMP32ri, X86::CMP32mi, 1 },
{ X86::CMP32ri8, X86::CMP32mi8, 1 },
Add CMP32mr and friends to the load-unfolding table. Among other things, this allows the scheduler to unfold a load operand in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully clones the comparison to avoid a pushf+popf. llvm-svn: 48777
2008-03-26 00:53:19 +08:00
{ X86::CMP32rr, X86::CMP32mr, 1 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::CMP64ri32, X86::CMP64mi32, 1 },
{ X86::CMP64ri8, X86::CMP64mi8, 1 },
Add CMP32mr and friends to the load-unfolding table. Among other things, this allows the scheduler to unfold a load operand in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully clones the comparison to avoid a pushf+popf. llvm-svn: 48777
2008-03-26 00:53:19 +08:00
{ X86::CMP64rr, X86::CMP64mr, 1 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::CMP8ri, X86::CMP8mi, 1 },
Add CMP32mr and friends to the load-unfolding table. Among other things, this allows the scheduler to unfold a load operand in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully clones the comparison to avoid a pushf+popf. llvm-svn: 48777
2008-03-26 00:53:19 +08:00
{ X86::CMP8rr, X86::CMP8mr, 1 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::DIV16r, X86::DIV16m, 1 },
{ X86::DIV32r, X86::DIV32m, 1 },
{ X86::DIV64r, X86::DIV64m, 1 },
{ X86::DIV8r, X86::DIV8m, 1 },
Add an EXTRACTPSmr pattern to match the pattern that X86ISelLowering creates. llvm-svn: 54544
2008-08-09 02:30:21 +08:00
{ X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
{ X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
{ X86::IDIV16r, X86::IDIV16m, 1 },
{ X86::IDIV32r, X86::IDIV32m, 1 },
{ X86::IDIV64r, X86::IDIV64m, 1 },
{ X86::IDIV8r, X86::IDIV8m, 1 },
{ X86::IMUL16r, X86::IMUL16m, 1 },
{ X86::IMUL32r, X86::IMUL32m, 1 },
{ X86::IMUL64r, X86::IMUL64m, 1 },
{ X86::IMUL8r, X86::IMUL8m, 1 },
{ X86::JMP32r, X86::JMP32m, 1 },
{ X86::JMP64r, X86::JMP64m, 1 },
{ X86::MOV16ri, X86::MOV16mi, 0 },
{ X86::MOV16rr, X86::MOV16mr, 0 },
{ X86::MOV16to16_, X86::MOV16_mr, 0 },
{ X86::MOV32ri, X86::MOV32mi, 0 },
{ X86::MOV32rr, X86::MOV32mr, 0 },
{ X86::MOV32to32_, X86::MOV32_mr, 0 },
{ X86::MOV64ri32, X86::MOV64mi32, 0 },
{ X86::MOV64rr, X86::MOV64mr, 0 },
{ X86::MOV8ri, X86::MOV8mi, 0 },
{ X86::MOV8rr, X86::MOV8mr, 0 },
{ X86::MOVAPDrr, X86::MOVAPDmr, 0 },
{ X86::MOVAPSrr, X86::MOVAPSmr, 0 },
{ X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
{ X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
{ X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
{ X86::MOVSDrr, X86::MOVSDmr, 0 },
{ X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
{ X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
{ X86::MOVSSrr, X86::MOVSSmr, 0 },
{ X86::MOVUPDrr, X86::MOVUPDmr, 0 },
{ X86::MOVUPSrr, X86::MOVUPSmr, 0 },
{ X86::MUL16r, X86::MUL16m, 1 },
{ X86::MUL32r, X86::MUL32m, 1 },
{ X86::MUL64r, X86::MUL64m, 1 },
{ X86::MUL8r, X86::MUL8m, 1 },
{ X86::SETAEr, X86::SETAEm, 0 },
{ X86::SETAr, X86::SETAm, 0 },
{ X86::SETBEr, X86::SETBEm, 0 },
{ X86::SETBr, X86::SETBm, 0 },
{ X86::SETEr, X86::SETEm, 0 },
{ X86::SETGEr, X86::SETGEm, 0 },
{ X86::SETGr, X86::SETGm, 0 },
{ X86::SETLEr, X86::SETLEm, 0 },
{ X86::SETLr, X86::SETLm, 0 },
{ X86::SETNEr, X86::SETNEm, 0 },
Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS". llvm-svn: 60385
2008-12-02 08:07:05 +08:00
{ X86::SETNOr, X86::SETNOm, 0 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::SETNPr, X86::SETNPm, 0 },
{ X86::SETNSr, X86::SETNSm, 0 },
Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS". llvm-svn: 60385
2008-12-02 08:07:05 +08:00
{ X86::SETOr, X86::SETOm, 0 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::SETPr, X86::SETPm, 0 },
{ X86::SETSr, X86::SETSm, 0 },
{ X86::TAILJMPr, X86::TAILJMPm, 1 },
{ X86::TEST16ri, X86::TEST16mi, 1 },
{ X86::TEST32ri, X86::TEST32mi, 1 },
{ X86::TEST64ri32, X86::TEST64mi32, 1 },
remove xchg and shift-reg-by-1 instructions, which are dead. llvm-svn: 45870
2008-01-12 02:00:50 +08:00
{ X86::TEST8ri, X86::TEST8mi, 1 }
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
};
for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
unsigned RegOp = OpTbl0[i][0];
unsigned MemOp = OpTbl0[i][1];
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
MemOp)).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
assert(false && "Duplicated entries?");
unsigned FoldedLoad = OpTbl0[i][2];
// Index 0, folded load or store.
unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
std::make_pair(RegOp, AuxInfo))).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AmbEntries.push_back(MemOp);
}
static const unsigned OpTbl1[][2] = {
{ X86::CMP16rr, X86::CMP16rm },
{ X86::CMP32rr, X86::CMP32rm },
{ X86::CMP64rr, X86::CMP64rm },
{ X86::CMP8rr, X86::CMP8rm },
{ X86::CVTSD2SSrr, X86::CVTSD2SSrm },
{ X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
{ X86::CVTSI2SDrr, X86::CVTSI2SDrm },
{ X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
{ X86::CVTSI2SSrr, X86::CVTSI2SSrm },
{ X86::CVTSS2SDrr, X86::CVTSS2SDrm },
{ X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
{ X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
{ X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
{ X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
{ X86::FsMOVAPDrr, X86::MOVSDrm },
{ X86::FsMOVAPSrr, X86::MOVSSrm },
{ X86::IMUL16rri, X86::IMUL16rmi },
{ X86::IMUL16rri8, X86::IMUL16rmi8 },
{ X86::IMUL32rri, X86::IMUL32rmi },
{ X86::IMUL32rri8, X86::IMUL32rmi8 },
{ X86::IMUL64rri32, X86::IMUL64rmi32 },
{ X86::IMUL64rri8, X86::IMUL64rmi8 },
{ X86::Int_CMPSDrr, X86::Int_CMPSDrm },
{ X86::Int_CMPSSrr, X86::Int_CMPSSrm },
{ X86::Int_COMISDrr, X86::Int_COMISDrm },
{ X86::Int_COMISSrr, X86::Int_COMISSrm },
{ X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
{ X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
{ X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
{ X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
{ X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
{ X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
{ X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
{ X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
{ X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
{ X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
{ X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
{ X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
{ X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
{ X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
{ X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
{ X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
{ X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
{ X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
{ X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
{ X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
{ X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
{ X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
{ X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
{ X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
{ X86::MOV16rr, X86::MOV16rm },
{ X86::MOV16to16_, X86::MOV16_rm },
{ X86::MOV32rr, X86::MOV32rm },
{ X86::MOV32to32_, X86::MOV32_rm },
{ X86::MOV64rr, X86::MOV64rm },
{ X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
{ X86::MOV64toSDrr, X86::MOV64toSDrm },
{ X86::MOV8rr, X86::MOV8rm },
{ X86::MOVAPDrr, X86::MOVAPDrm },
{ X86::MOVAPSrr, X86::MOVAPSrm },
{ X86::MOVDDUPrr, X86::MOVDDUPrm },
{ X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
{ X86::MOVDI2SSrr, X86::MOVDI2SSrm },
{ X86::MOVSD2PDrr, X86::MOVSD2PDrm },
{ X86::MOVSDrr, X86::MOVSDrm },
{ X86::MOVSHDUPrr, X86::MOVSHDUPrm },
{ X86::MOVSLDUPrr, X86::MOVSLDUPrm },
{ X86::MOVSS2PSrr, X86::MOVSS2PSrm },
{ X86::MOVSSrr, X86::MOVSSrm },
{ X86::MOVSX16rr8, X86::MOVSX16rm8 },
{ X86::MOVSX32rr16, X86::MOVSX32rm16 },
{ X86::MOVSX32rr8, X86::MOVSX32rm8 },
{ X86::MOVSX64rr16, X86::MOVSX64rm16 },
{ X86::MOVSX64rr32, X86::MOVSX64rm32 },
{ X86::MOVSX64rr8, X86::MOVSX64rm8 },
{ X86::MOVUPDrr, X86::MOVUPDrm },
{ X86::MOVUPSrr, X86::MOVUPSrm },
{ X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
{ X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
{ X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
{ X86::MOVZX16rr8, X86::MOVZX16rm8 },
{ X86::MOVZX32rr16, X86::MOVZX32rm16 },
{ X86::MOVZX32rr8, X86::MOVZX32rm8 },
{ X86::MOVZX64rr16, X86::MOVZX64rm16 },
Re-enable elimination of unnecessary SUBREG_TO_REG instructions in LowerSubregs, and fix an x86-64 isel bug that this exposed. SUBREG_TO_REG for x86-64 implicit zero extension is only safe for isel to generate when the source is known to always have zeros in the high 32 bits. The EXTRACT_SUBREG instruction does not clear the high 32 bits. llvm-svn: 54444
2008-08-07 10:54:50 +08:00
{ X86::MOVZX64rr32, X86::MOVZX64rm32 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::MOVZX64rr8, X86::MOVZX64rm8 },
{ X86::PSHUFDri, X86::PSHUFDmi },
{ X86::PSHUFHWri, X86::PSHUFHWmi },
{ X86::PSHUFLWri, X86::PSHUFLWmi },
{ X86::RCPPSr, X86::RCPPSm },
{ X86::RCPPSr_Int, X86::RCPPSm_Int },
{ X86::RSQRTPSr, X86::RSQRTPSm },
{ X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
{ X86::RSQRTSSr, X86::RSQRTSSm },
{ X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
{ X86::SQRTPDr, X86::SQRTPDm },
{ X86::SQRTPDr_Int, X86::SQRTPDm_Int },
{ X86::SQRTPSr, X86::SQRTPSm },
{ X86::SQRTPSr_Int, X86::SQRTPSm_Int },
{ X86::SQRTSDr, X86::SQRTSDm },
{ X86::SQRTSDr_Int, X86::SQRTSDm_Int },
{ X86::SQRTSSr, X86::SQRTSSm },
{ X86::SQRTSSr_Int, X86::SQRTSSm_Int },
{ X86::TEST16rr, X86::TEST16rm },
{ X86::TEST32rr, X86::TEST32rm },
{ X86::TEST64rr, X86::TEST64rm },
{ X86::TEST8rr, X86::TEST8rm },
// FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
{ X86::UCOMISDrr, X86::UCOMISDrm },
remove xchg and shift-reg-by-1 instructions, which are dead. llvm-svn: 45870
2008-01-12 02:00:50 +08:00
{ X86::UCOMISSrr, X86::UCOMISSrm }
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
};
for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
unsigned RegOp = OpTbl1[i][0];
unsigned MemOp = OpTbl1[i][1];
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
MemOp)).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
assert(false && "Duplicated entries?");
unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
std::make_pair(RegOp, AuxInfo))).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AmbEntries.push_back(MemOp);
}
static const unsigned OpTbl2[][2] = {
{ X86::ADC32rr, X86::ADC32rm },
{ X86::ADC64rr, X86::ADC64rm },
{ X86::ADD16rr, X86::ADD16rm },
{ X86::ADD32rr, X86::ADD32rm },
{ X86::ADD64rr, X86::ADD64rm },
{ X86::ADD8rr, X86::ADD8rm },
{ X86::ADDPDrr, X86::ADDPDrm },
{ X86::ADDPSrr, X86::ADDPSrm },
{ X86::ADDSDrr, X86::ADDSDrm },
{ X86::ADDSSrr, X86::ADDSSrm },
{ X86::ADDSUBPDrr, X86::ADDSUBPDrm },
{ X86::ADDSUBPSrr, X86::ADDSUBPSrm },
{ X86::AND16rr, X86::AND16rm },
{ X86::AND32rr, X86::AND32rm },
{ X86::AND64rr, X86::AND64rm },
{ X86::AND8rr, X86::AND8rm },
{ X86::ANDNPDrr, X86::ANDNPDrm },
{ X86::ANDNPSrr, X86::ANDNPSrm },
{ X86::ANDPDrr, X86::ANDPDrm },
{ X86::ANDPSrr, X86::ANDPSrm },
{ X86::CMOVA16rr, X86::CMOVA16rm },
{ X86::CMOVA32rr, X86::CMOVA32rm },
{ X86::CMOVA64rr, X86::CMOVA64rm },
{ X86::CMOVAE16rr, X86::CMOVAE16rm },
{ X86::CMOVAE32rr, X86::CMOVAE32rm },
{ X86::CMOVAE64rr, X86::CMOVAE64rm },
{ X86::CMOVB16rr, X86::CMOVB16rm },
{ X86::CMOVB32rr, X86::CMOVB32rm },
{ X86::CMOVB64rr, X86::CMOVB64rm },
{ X86::CMOVBE16rr, X86::CMOVBE16rm },
{ X86::CMOVBE32rr, X86::CMOVBE32rm },
{ X86::CMOVBE64rr, X86::CMOVBE64rm },
{ X86::CMOVE16rr, X86::CMOVE16rm },
{ X86::CMOVE32rr, X86::CMOVE32rm },
{ X86::CMOVE64rr, X86::CMOVE64rm },
{ X86::CMOVG16rr, X86::CMOVG16rm },
{ X86::CMOVG32rr, X86::CMOVG32rm },
{ X86::CMOVG64rr, X86::CMOVG64rm },
{ X86::CMOVGE16rr, X86::CMOVGE16rm },
{ X86::CMOVGE32rr, X86::CMOVGE32rm },
{ X86::CMOVGE64rr, X86::CMOVGE64rm },
{ X86::CMOVL16rr, X86::CMOVL16rm },
{ X86::CMOVL32rr, X86::CMOVL32rm },
{ X86::CMOVL64rr, X86::CMOVL64rm },
{ X86::CMOVLE16rr, X86::CMOVLE16rm },
{ X86::CMOVLE32rr, X86::CMOVLE32rm },
{ X86::CMOVLE64rr, X86::CMOVLE64rm },
{ X86::CMOVNE16rr, X86::CMOVNE16rm },
{ X86::CMOVNE32rr, X86::CMOVNE32rm },
{ X86::CMOVNE64rr, X86::CMOVNE64rm },
{ X86::CMOVNP16rr, X86::CMOVNP16rm },
{ X86::CMOVNP32rr, X86::CMOVNP32rm },
{ X86::CMOVNP64rr, X86::CMOVNP64rm },
{ X86::CMOVNS16rr, X86::CMOVNS16rm },
{ X86::CMOVNS32rr, X86::CMOVNS32rm },
{ X86::CMOVNS64rr, X86::CMOVNS64rm },
Define instructions for cmovo and cmovno. llvm-svn: 61836
2009-01-07 08:35:10 +08:00
{ X86::CMOVO16rr, X86::CMOVO16rm },
{ X86::CMOVO32rr, X86::CMOVO32rm },
{ X86::CMOVO64rr, X86::CMOVO64rm },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::CMOVP16rr, X86::CMOVP16rm },
{ X86::CMOVP32rr, X86::CMOVP32rm },
{ X86::CMOVP64rr, X86::CMOVP64rm },
{ X86::CMOVS16rr, X86::CMOVS16rm },
{ X86::CMOVS32rr, X86::CMOVS32rm },
{ X86::CMOVS64rr, X86::CMOVS64rm },
{ X86::CMPPDrri, X86::CMPPDrmi },
{ X86::CMPPSrri, X86::CMPPSrmi },
{ X86::CMPSDrr, X86::CMPSDrm },
{ X86::CMPSSrr, X86::CMPSSrm },
{ X86::DIVPDrr, X86::DIVPDrm },
{ X86::DIVPSrr, X86::DIVPSrm },
{ X86::DIVSDrr, X86::DIVSDrm },
{ X86::DIVSSrr, X86::DIVSSrm },
Undo r50574. We are already ensuring the folded load address is 16-byte aligned. llvm-svn: 50578
2008-05-03 01:01:01 +08:00
{ X86::FsANDNPDrr, X86::FsANDNPDrm },
{ X86::FsANDNPSrr, X86::FsANDNPSrm },
{ X86::FsANDPDrr, X86::FsANDPDrm },
{ X86::FsANDPSrr, X86::FsANDPSrm },
{ X86::FsORPDrr, X86::FsORPDrm },
{ X86::FsORPSrr, X86::FsORPSrm },
{ X86::FsXORPDrr, X86::FsXORPDrm },
{ X86::FsXORPSrr, X86::FsXORPSrm },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::HADDPDrr, X86::HADDPDrm },
{ X86::HADDPSrr, X86::HADDPSrm },
{ X86::HSUBPDrr, X86::HSUBPDrm },
{ X86::HSUBPSrr, X86::HSUBPSrm },
{ X86::IMUL16rr, X86::IMUL16rm },
{ X86::IMUL32rr, X86::IMUL32rm },
{ X86::IMUL64rr, X86::IMUL64rm },
{ X86::MAXPDrr, X86::MAXPDrm },
{ X86::MAXPDrr_Int, X86::MAXPDrm_Int },
{ X86::MAXPSrr, X86::MAXPSrm },
{ X86::MAXPSrr_Int, X86::MAXPSrm_Int },
{ X86::MAXSDrr, X86::MAXSDrm },
{ X86::MAXSDrr_Int, X86::MAXSDrm_Int },
{ X86::MAXSSrr, X86::MAXSSrm },
{ X86::MAXSSrr_Int, X86::MAXSSrm_Int },
{ X86::MINPDrr, X86::MINPDrm },
{ X86::MINPDrr_Int, X86::MINPDrm_Int },
{ X86::MINPSrr, X86::MINPSrm },
{ X86::MINPSrr_Int, X86::MINPSrm_Int },
{ X86::MINSDrr, X86::MINSDrm },
{ X86::MINSDrr_Int, X86::MINSDrm_Int },
{ X86::MINSSrr, X86::MINSSrm },
{ X86::MINSSrr_Int, X86::MINSSrm_Int },
{ X86::MULPDrr, X86::MULPDrm },
{ X86::MULPSrr, X86::MULPSrm },
{ X86::MULSDrr, X86::MULSDrm },
{ X86::MULSSrr, X86::MULSSrm },
{ X86::OR16rr, X86::OR16rm },
{ X86::OR32rr, X86::OR32rm },
{ X86::OR64rr, X86::OR64rm },
{ X86::OR8rr, X86::OR8rm },
{ X86::ORPDrr, X86::ORPDrm },
{ X86::ORPSrr, X86::ORPSrm },
{ X86::PACKSSDWrr, X86::PACKSSDWrm },
{ X86::PACKSSWBrr, X86::PACKSSWBrm },
{ X86::PACKUSWBrr, X86::PACKUSWBrm },
{ X86::PADDBrr, X86::PADDBrm },
{ X86::PADDDrr, X86::PADDDrm },
{ X86::PADDQrr, X86::PADDQrm },
{ X86::PADDSBrr, X86::PADDSBrm },
{ X86::PADDSWrr, X86::PADDSWrm },
{ X86::PADDWrr, X86::PADDWrm },
{ X86::PANDNrr, X86::PANDNrm },
{ X86::PANDrr, X86::PANDrm },
{ X86::PAVGBrr, X86::PAVGBrm },
{ X86::PAVGWrr, X86::PAVGWrm },
{ X86::PCMPEQBrr, X86::PCMPEQBrm },
{ X86::PCMPEQDrr, X86::PCMPEQDrm },
{ X86::PCMPEQWrr, X86::PCMPEQWrm },
{ X86::PCMPGTBrr, X86::PCMPGTBrm },
{ X86::PCMPGTDrr, X86::PCMPGTDrm },
{ X86::PCMPGTWrr, X86::PCMPGTWrm },
{ X86::PINSRWrri, X86::PINSRWrmi },
{ X86::PMADDWDrr, X86::PMADDWDrm },
{ X86::PMAXSWrr, X86::PMAXSWrm },
{ X86::PMAXUBrr, X86::PMAXUBrm },
{ X86::PMINSWrr, X86::PMINSWrm },
{ X86::PMINUBrr, X86::PMINUBrm },
Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add load-folding table entries for PMULDQ and PMULLD. llvm-svn: 51489
2008-05-24 01:49:40 +08:00
{ X86::PMULDQrr, X86::PMULDQrm },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::PMULHUWrr, X86::PMULHUWrm },
{ X86::PMULHWrr, X86::PMULHWrm },
Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add load-folding table entries for PMULDQ and PMULLD. llvm-svn: 51489
2008-05-24 01:49:40 +08:00
{ X86::PMULLDrr, X86::PMULLDrm },
{ X86::PMULLDrr_int, X86::PMULLDrm_int },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
{ X86::PMULLWrr, X86::PMULLWrm },
{ X86::PMULUDQrr, X86::PMULUDQrm },
{ X86::PORrr, X86::PORrm },
{ X86::PSADBWrr, X86::PSADBWrm },
{ X86::PSLLDrr, X86::PSLLDrm },
{ X86::PSLLQrr, X86::PSLLQrm },
{ X86::PSLLWrr, X86::PSLLWrm },
{ X86::PSRADrr, X86::PSRADrm },
{ X86::PSRAWrr, X86::PSRAWrm },
{ X86::PSRLDrr, X86::PSRLDrm },
{ X86::PSRLQrr, X86::PSRLQrm },
{ X86::PSRLWrr, X86::PSRLWrm },
{ X86::PSUBBrr, X86::PSUBBrm },
{ X86::PSUBDrr, X86::PSUBDrm },
{ X86::PSUBSBrr, X86::PSUBSBrm },
{ X86::PSUBSWrr, X86::PSUBSWrm },
{ X86::PSUBWrr, X86::PSUBWrm },
{ X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
{ X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
{ X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
{ X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
{ X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
{ X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
{ X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
{ X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
{ X86::PXORrr, X86::PXORrm },
{ X86::SBB32rr, X86::SBB32rm },
{ X86::SBB64rr, X86::SBB64rm },
{ X86::SHUFPDrri, X86::SHUFPDrmi },
{ X86::SHUFPSrri, X86::SHUFPSrmi },
{ X86::SUB16rr, X86::SUB16rm },
{ X86::SUB32rr, X86::SUB32rm },
{ X86::SUB64rr, X86::SUB64rm },
{ X86::SUB8rr, X86::SUB8rm },
{ X86::SUBPDrr, X86::SUBPDrm },
{ X86::SUBPSrr, X86::SUBPSrm },
{ X86::SUBSDrr, X86::SUBSDrm },
{ X86::SUBSSrr, X86::SUBSSrm },
// FIXME: TEST*rr -> swapped operand of TEST*mr.
{ X86::UNPCKHPDrr, X86::UNPCKHPDrm },
{ X86::UNPCKHPSrr, X86::UNPCKHPSrm },
{ X86::UNPCKLPDrr, X86::UNPCKLPDrm },
{ X86::UNPCKLPSrr, X86::UNPCKLPSrm },
{ X86::XOR16rr, X86::XOR16rm },
{ X86::XOR32rr, X86::XOR32rm },
{ X86::XOR64rr, X86::XOR64rm },
{ X86::XOR8rr, X86::XOR8rm },
{ X86::XORPDrr, X86::XORPDrm },
{ X86::XORPSrr, X86::XORPSrm }
};
for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
unsigned RegOp = OpTbl2[i][0];
unsigned MemOp = OpTbl2[i][1];
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
MemOp)).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
assert(false && "Duplicated entries?");
unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
Make DenseMap's insert return a pair, to more closely resemble std::map. llvm-svn: 53177
2008-07-08 01:46:23 +08:00
std::make_pair(RegOp, AuxInfo))).second)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AmbEntries.push_back(MemOp);
}
// Remove ambiguous entries.
assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 06:55:53 +08:00
}
Add TargetInstrInfo::isMoveInstr() to support coalescing in register allocation. llvm-svn: 10633
2003-12-29 01:35:08 +08:00
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
convert a massive if statement to a switch. llvm-svn: 48240
2008-03-12 03:28:17 +08:00
switch (MI.getOpcode()) {
default:
return false;
case X86::MOV8rr:
case X86::MOV16rr:
case X86::MOV32rr:
case X86::MOV64rr:
case X86::MOV16to16_:
case X86::MOV32to32_:
case X86::MOVSSrr:
case X86::MOVSDrr:
coalesce away 80-bit floating point copies. llvm-svn: 48241
2008-03-12 03:30:09 +08:00
// FP Stack register class copies
case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
case X86::MOV_Fp3264: case X86::MOV_Fp3280:
case X86::MOV_Fp6432: case X86::MOV_Fp8032:
convert a massive if statement to a switch. llvm-svn: 48240
2008-03-12 03:28:17 +08:00
case X86::FsMOVAPSrr:
case X86::FsMOVAPDrr:
case X86::MOVAPSrr:
case X86::MOVAPDrr:
case X86::MOVSS2PSrr:
case X86::MOVSD2PDrr:
case X86::MOVPS2SSrr:
case X86::MOVPD2SDrr:
case X86::MMX_MOVD64rr:
case X86::MMX_MOVQ64rr:
assert(MI.getNumOperands() >= 2 &&
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
convert a massive if statement to a switch. llvm-svn: 48240
2008-03-12 03:28:17 +08:00
"invalid register-register move instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
Add TargetInstrInfo::isMoveInstr() to support coalescing in register allocation. llvm-svn: 10633
2003-12-29 01:35:08 +08:00
}
}
Implement insertGoto and reverseBranchCondition for the X86. llvm-svn: 15362
2004-07-31 17:38:47 +08:00
Add more const qualifiers. This fixes build breakage from r59540. llvm-svn: 59542
2008-11-19 03:49:32 +08:00
unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
case X86::MOV8rm:
case X86::MOV16rm:
Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot llvm-svn: 28223
2006-05-11 15:33:49 +08:00
case X86::MOV16_rm:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
case X86::MOV32rm:
Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot llvm-svn: 28223
2006-05-11 15:33:49 +08:00
case X86::MOV32_rm:
Committing X86-64 support. llvm-svn: 30177
2006-09-08 14:48:29 +08:00
case X86::MOV64rm:
Refactor X87 instructions. As a side effect, all their names are changed. llvm-svn: 37876
2007-07-05 05:07:47 +08:00
case X86::LD_Fp64m:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
case X86::MOVSSrm:
case X86::MOVSDrm:
Teach the codegen about instructions used for SSE spill code, allowing it to optimize cases where it has to spill a lot llvm-svn: 27801
2006-04-19 00:44:51 +08:00
case X86::MOVAPSrm:
case X86::MOVAPDrm:
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. llvm-svn: 35616
2007-04-03 14:00:37 +08:00
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm llvm-svn: 45453
2007-12-31 04:49:49 +08:00
MI->getOperand(2).getImm() == 1 &&
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
MI->getOperand(3).getReg() == 0 &&
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm llvm-svn: 45453
2007-12-31 04:49:49 +08:00
MI->getOperand(4).getImm() == 0) {
Add new shorter predicates for testing machine operands for various types: e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
2007-12-31 07:10:15 +08:00
FrameIndex = MI->getOperand(1).getIndex();
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
return MI->getOperand(0).getReg();
}
break;
}
return 0;
}
Add more const qualifiers. This fixes build breakage from r59540. llvm-svn: 59542
2008-11-19 03:49:32 +08:00
unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
case X86::MOV8mr:
case X86::MOV16mr:
Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot llvm-svn: 28223
2006-05-11 15:33:49 +08:00
case X86::MOV16_mr:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
case X86::MOV32mr:
Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot llvm-svn: 28223
2006-05-11 15:33:49 +08:00
case X86::MOV32_mr:
Committing X86-64 support. llvm-svn: 30177
2006-09-08 14:48:29 +08:00
case X86::MOV64mr:
Refactor X87 instructions. As a side effect, all their names are changed. llvm-svn: 37876
2007-07-05 05:07:47 +08:00
case X86::ST_FpP64m:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
case X86::MOVSSmr:
case X86::MOVSDmr:
Teach the codegen about instructions used for SSE spill code, allowing it to optimize cases where it has to spill a lot llvm-svn: 27801
2006-04-19 00:44:51 +08:00
case X86::MOVAPSmr:
case X86::MOVAPDmr:
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. llvm-svn: 35616
2007-04-03 14:00:37 +08:00
case X86::MMX_MOVD64mr:
case X86::MMX_MOVQ64mr:
Adding more MMX instructions. llvm-svn: 35638
2007-04-04 07:48:32 +08:00
case X86::MMX_MOVNTQmr:
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm llvm-svn: 45453
2007-12-31 04:49:49 +08:00
MI->getOperand(1).getImm() == 1 &&
fix operand numbers llvm-svn: 25915
2006-02-03 04:38:12 +08:00
MI->getOperand(2).getReg() == 0 &&
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm llvm-svn: 45453
2007-12-31 04:49:49 +08:00
MI->getOperand(3).getImm() == 0) {
Add new shorter predicates for testing machine operands for various types: e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
2007-12-31 07:10:15 +08:00
FrameIndex = MI->getOperand(0).getIndex();
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
return MI->getOperand(4).getReg();
}
break;
}
return 0;
}
Code clean up. llvm-svn: 48856
2008-03-27 09:45:11 +08:00
/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
/// X86::MOVPC32r.
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Code clean up. llvm-svn: 48856
2008-03-27 09:45:11 +08:00
bool isPICBase = false;
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
E = MRI.def_end(); I != E; ++I) {
MachineInstr *DefMI = I.getOperand().getParent();
if (DefMI->getOpcode() != X86::MOVPC32r)
return false;
assert(!isPICBase && "More than one PIC base?");
isPICBase = true;
}
return isPICBase;
}
Re-apply 48911. llvm-svn: 48977
2008-03-31 15:54:19 +08:00
/// isGVStub - Return true if the GV requires an extra load to get the
/// real address.
static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
}
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
Constify the machine instruction passed into the "is{Trivially,Really}ReMaterializable" methods. llvm-svn: 51001
2008-05-13 04:54:26 +08:00
bool
X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
Add a target hook to allow loads from constant pools to be rematerialized, and an implementation for x86. llvm-svn: 37576
2007-06-15 04:50:44 +08:00
switch (MI->getOpcode()) {
default: break;
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV16_rm:
case X86::MOV32rm:
case X86::MOV32_rm:
case X86::MOV64rm:
case X86::LD_Fp64m:
case X86::MOVSSrm:
case X86::MOVSDrm:
case X86::MOVAPSrm:
case X86::MOVAPDrm:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm: {
// Loads from constant pools are trivially rematerializable.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
(MI->getOperand(4).isCPI() ||
(MI->getOperand(4).isGlobal() &&
Re-apply 48911. llvm-svn: 48977
2008-03-31 15:54:19 +08:00
isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
unsigned BaseReg = MI->getOperand(1).getReg();
if (BaseReg == 0)
return true;
// Allow re-materialization of PIC load.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now. llvm-svn: 49059
2008-04-02 07:26:12 +08:00
return false;
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
const MachineFunction &MF = *MI->getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
bool isPICBase = false;
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
E = MRI.def_end(); I != E; ++I) {
MachineInstr *DefMI = I.getOperand().getParent();
if (DefMI->getOpcode() != X86::MOVPC32r)
return false;
assert(!isPICBase && "More than one PIC base?");
isPICBase = true;
}
return isPICBase;
}
return false;
Allow re-materialization of pic load (controlled by -remat-pic-load for now). llvm-svn: 47476
2008-02-22 17:25:47 +08:00
}
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
case X86::LEA32r:
case X86::LEA64r: {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
!MI->getOperand(4).isReg()) {
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
// lea fi#, lea GV, etc. are all rematerializable.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (!MI->getOperand(1).isReg())
Mark lea fi# as being really rematerializable. llvm-svn: 56698
2008-09-27 05:30:20 +08:00
return true;
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
unsigned BaseReg = MI->getOperand(1).getReg();
if (BaseReg == 0)
return true;
// Allow re-materialization of lea PICBase + x.
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
const MachineFunction &MF = *MI->getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
Code clean up. llvm-svn: 48856
2008-03-27 09:45:11 +08:00
return regIsPICBase(BaseReg, MRI);
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
}
return false;
}
Add a target hook to allow loads from constant pools to be rematerialized, and an implementation for x86. llvm-svn: 37576
2007-06-15 04:50:44 +08:00
}
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
Revert the earlier change that removed the M_REMATERIALIZABLE machine instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
2007-06-26 08:48:07 +08:00
// All other instructions marked M_REMATERIALIZABLE are always trivially
// rematerializable.
return true;
Add a target hook to allow loads from constant pools to be rematerialized, and an implementation for x86. llvm-svn: 37576
2007-06-15 04:50:44 +08:00
}
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
/// would clobber the EFLAGS condition register. Note the result may be
/// conservative. If it cannot definitely determine the safety after visiting
/// two instructions it assumes it's not safe.
static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) {
When the coalescer is doing rematerializing, have it remove the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
2008-10-21 11:24:31 +08:00
// It's always safe to clobber EFLAGS at the end of a block.
if (I == MBB.end())
return true;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
// For compile time consideration, if we are not able to determine the
// safety after visiting 2 instructions, we will assume it's not safe.
for (unsigned i = 0; i < 2; ++i) {
bool SeenDef = false;
for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
MachineOperand &MO = I->getOperand(j);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (!MO.isReg())
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
continue;
if (MO.getReg() == X86::EFLAGS) {
if (MO.isUse())
return false;
SeenDef = true;
}
}
if (SeenDef)
// This instruction defines EFLAGS, no need to look any further.
return true;
++I;
When the coalescer is doing rematerializing, have it remove the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
2008-10-21 11:24:31 +08:00
// If we make it to the end of the block, it's safe to clobber EFLAGS.
if (I == MBB.end())
return true;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
}
// Conservative answer.
return false;
}
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
unsigned SubIdx = Orig->getOperand(0).isReg()
Don't forget about sub-register indices when rematting instructions. llvm-svn: 49830
2008-04-17 07:44:44 +08:00
? Orig->getOperand(0).getSubReg() : 0;
bool ChangeSubIdx = SubIdx != 0;
if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
DestReg = RI.getSubReg(DestReg, SubIdx);
SubIdx = 0;
}
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
// MOV32r0 etc. are implemented with xor which clobbers condition code.
// Re-materialize them as movri instructions to avoid side effects.
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
bool Emitted = false;
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
switch (Orig->getOpcode()) {
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
default: break;
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
case X86::MOV8r0:
case X86::MOV16r0:
case X86::MOV32r0:
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
case X86::MOV64r0: {
if (!isSafeToClobberEFLAGS(MBB, I)) {
unsigned Opc = 0;
switch (Orig->getOpcode()) {
default: break;
case X86::MOV8r0: Opc = X86::MOV8ri; break;
case X86::MOV16r0: Opc = X86::MOV16ri; break;
case X86::MOV32r0: Opc = X86::MOV32ri; break;
case X86::MOV64r0: Opc = X86::MOV64ri32; break;
}
BuildMI(MBB, I, get(Opc), DestReg).addImm(0);
Emitted = true;
}
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
break;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
}
}
if (!Emitted) {
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
Don't forget about sub-register indices when rematting instructions. llvm-svn: 49830
2008-04-17 07:44:44 +08:00
if (ChangeSubIdx) {
MachineInstr *NewMI = prior(I);
NewMI->getOperand(0).setSubReg(SubIdx);
}
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
}
Simplify the side effect stuff a bit more and make licm/sinking both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. llvm-svn: 45843
2008-01-11 07:08:24 +08:00
/// isInvariantLoad - Return true if the specified instruction (which is marked
/// mayLoad) is loading from a location whose value is invariant across the
/// function. For example, loading a value from the constant pool or from
/// from the argument area of a function if it does not change. This should
/// only return true of *all* loads the instruction does are invariant (if it
/// does multiple loads).
Add more const qualifiers. This fixes build breakage from r59540. llvm-svn: 59542
2008-11-19 03:49:32 +08:00
bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
Any x86 instruction that reads from an invariant location is invariant. This allows us to sink things like: cvtsi2sd 32(%esp), %xmm1 when reading from the argument area, for example. llvm-svn: 45895
2008-01-12 08:35:08 +08:00
// This code cares about loads from three cases: constant pool entries,
// invariant argument slots, and global stubs. In order to handle these cases
// for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
fix a wordo that gordon noticed :) llvm-svn: 45896
2008-01-12 08:53:16 +08:00
// operand and base our analysis on it. This is safe because the address of
Any x86 instruction that reads from an invariant location is invariant. This allows us to sink things like: cvtsi2sd 32(%esp), %xmm1 when reading from the argument area, for example. llvm-svn: 45895
2008-01-12 08:35:08 +08:00
// none of these three cases is ever used as anything other than a load base
// and X86 doesn't have any instructions that load from multiple places.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
Simplify the side effect stuff a bit more and make licm/sinking both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. llvm-svn: 45843
2008-01-11 07:08:24 +08:00
// Loads from constant pools are trivially invariant.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isCPI())
simplify some code by using shorter accessors. llvm-svn: 45622
2008-01-05 13:28:30 +08:00
return true;
Re-apply 48911. llvm-svn: 48977
2008-03-31 15:54:19 +08:00
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isGlobal())
Re-apply 48911. llvm-svn: 48977
2008-03-31 15:54:19 +08:00
return isGVStub(MO.getGlobal(), TM);
Any x86 instruction that reads from an invariant location is invariant. This allows us to sink things like: cvtsi2sd 32(%esp), %xmm1 when reading from the argument area, for example. llvm-svn: 45895
2008-01-12 08:35:08 +08:00
// If this is a load from an invariant stack slot, the load is a constant.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isFI()) {
Any x86 instruction that reads from an invariant location is invariant. This allows us to sink things like: cvtsi2sd 32(%esp), %xmm1 when reading from the argument area, for example. llvm-svn: 45895
2008-01-12 08:35:08 +08:00
const MachineFrameInfo &MFI =
*MI->getParent()->getParent()->getFrameInfo();
int Idx = MO.getIndex();
verify that the frame index is immutable before remat'ing (still disabled) or being side-effect free. llvm-svn: 45816
2008-01-10 12:16:31 +08:00
return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
}
Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I based what flag to set on whether it was already marked as "isRematerializable". If there was a further check to determine if it's "really" rematerializable, then I marked it as "mayHaveSideEffects" and created a check in the X86 back-end similar to the remat one. llvm-svn: 45132
2007-12-18 07:07:56 +08:00
}
Any x86 instruction that reads from an invariant location is invariant. This allows us to sink things like: cvtsi2sd 32(%esp), %xmm1 when reading from the argument area, for example. llvm-svn: 45895
2008-01-12 08:35:08 +08:00
Simplify the side effect stuff a bit more and make licm/sinking both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. llvm-svn: 45843
2008-01-11 07:08:24 +08:00
// All other instances of these instructions are presumed to have other
// issues.
revert my previous patch. llvm-svn: 45621
2008-01-05 13:26:26 +08:00
return false;
Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I based what flag to set on whether it was already marked as "isRematerializable". If there was a further check to determine if it's "really" rematerializable, then I marked it as "mayHaveSideEffects" and created a check in the X86 back-end similar to the remat one. llvm-svn: 45132
2007-12-18 07:07:56 +08:00
}
Testing convertToThreeeAddress as X86 llcbeta. llvm-svn: 42630
2007-10-05 16:04:01 +08:00
/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
/// is not marked dead.
static bool hasLiveCondCodeDef(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg() && MO.isDef() &&
Testing convertToThreeeAddress as X86 llcbeta. llvm-svn: 42630
2007-10-05 16:04:01 +08:00
MO.getReg() == X86::EFLAGS && !MO.isDead()) {
return true;
}
}
return false;
}
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
/// may be able to convert a two-address instruction into a true
/// three-address instruction on demand. This allows the X86 target (for
/// example) to convert ADD and SHL instructions into LEA instructions if they
/// would require register copies due to two-addressness.
///
/// This method returns a null pointer if the transformation cannot be
/// performed, otherwise it returns the new instruction.
///
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
MachineInstr *
X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. llvm-svn: 53058
2008-07-03 07:41:07 +08:00
LiveVariables *LV) const {
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
MachineInstr *MI = MBBI;
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineFunction &MF = *MI->getParent()->getParent();
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
// All instructions input are two-addr instructions. Get the known operands.
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
bool isDead = MI->getOperand(0).isDead();
bool isKill = MI->getOperand(1).isKill();
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
Properly transfer kill / dead info. llvm-svn: 31765
2006-11-16 04:58:11 +08:00
MachineInstr *NewMI = NULL;
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
// we have better subtarget support, enable the 16-bit LEA generation here.
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
bool DisableLEA16 = true;
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
unsigned MIOpc = MI->getOpcode();
switch (MIOpc) {
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. llvm-svn: 28565
2006-05-31 04:26:50 +08:00
case X86::SHUFPSrri: {
assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
Fix a build breaker. llvm-svn: 28574
2006-05-31 05:45:53 +08:00
unsigned B = MI->getOperand(1).getReg();
unsigned C = MI->getOperand(2).getReg();
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
if (B != C) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
unsigned A = MI->getOperand(0).getReg();
unsigned M = MI->getOperand(3).getImm();
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(B, false, false, isKill).addImm(M);
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
break;
}
Compile CodeGen/X86/lea-3.ll:test2 to: _test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret llvm-svn: 35434
2007-03-29 02:12:31 +08:00
case X86::SHL64ri: {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-15 05:48:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Compile CodeGen/X86/lea-3.ll:test2 to: _test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret llvm-svn: 35434
2007-03-29 02:12:31 +08:00
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
Compile CodeGen/X86/lea-3.ll:test2 to: _test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret llvm-svn: 35434
2007-03-29 02:12:31 +08:00
break;
}
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
case X86::SHL32ri: {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-15 05:48:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the system assembler not groking legal instructions like "leal (,%esi,8), %ecx". llvm-svn: 35393
2007-03-28 08:58:40 +08:00
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
X86::LEA64_32r : X86::LEA32r;
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead)
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0);
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
break;
}
case X86::SHL16ri: {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-15 05:48:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: leal (,%rcx,8), %rcx It should be leal (,%rcx,8), %ecx llvm-svn: 41735
2007-09-06 08:14:41 +08:00
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. llvm-svn: 41007
2007-08-11 05:18:25 +08:00
if (DisableLEA16) {
// If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
2007-12-31 12:13:23 +08:00
MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: leal (,%rcx,8), %rcx It should be leal (,%rcx,8), %ecx llvm-svn: 41735
2007-09-06 08:14:41 +08:00
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
? X86::LEA64_32r : X86::LEA32r;
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
2007-12-31 12:13:23 +08:00
unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. llvm-svn: 48167
2008-03-11 03:31:26 +08:00
Missed part of recommit. llvm-svn: 48224
2008-03-11 18:27:36 +08:00
// Build and insert into an implicit UNDEF value. This is OK because
// well be shifting and then extracting the lower 16-bits.
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg);
MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg)
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(leaInReg).addReg(Src, false, false, isKill)
.addImm(X86::SUBREG_16BIT);
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
2008-03-16 11:12:01 +08:00
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(leaInReg, false, false, true).addImm(0);
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. llvm-svn: 41007
2007-08-11 05:18:25 +08:00
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead)
.addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. llvm-svn: 53058
2008-07-03 07:41:07 +08:00
if (LV) {
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
// Update live variables
LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
if (isKill)
LV->replaceKillInstruction(Src, MI, InsMI);
if (isDead)
LV->replaceKillInstruction(Dest, MI, ExtMI);
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. llvm-svn: 53058
2008-07-03 07:41:07 +08:00
}
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
return ExtMI;
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. llvm-svn: 41007
2007-08-11 05:18:25 +08:00
} else {
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0);
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. llvm-svn: 41007
2007-08-11 05:18:25 +08:00
}
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
break;
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. llvm-svn: 28565
2006-05-31 04:26:50 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
default: {
// The following opcodes also sets the condition code register(s). Only
// convert them to equivalent lea if the condition code register def's
// are dead!
if (hasLiveCondCodeDef(MI))
return 0;
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. llvm-svn: 28565
2006-05-31 04:26:50 +08:00
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
switch (MIOpc) {
default: return 0;
case X86::INC64r:
Revert r42653 and forward-port the code that lets INC64_32r be converted to LEA64_32r in x86's convertToThreeAddress. This replaces code like this: movl %esi, %edi inc %edi with this: lea 1(%rsi), %edi which appears to be beneficial. llvm-svn: 61830
2009-01-07 07:34:46 +08:00
case X86::INC32r:
case X86::INC64_32r: {
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegOffset(BuildMI(MF, get(Opc))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, 1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
}
case X86::INC16r:
case X86::INC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, 1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::DEC64r:
Revert r42653 and forward-port the code that lets INC64_32r be converted to LEA64_32r in x86's convertToThreeAddress. This replaces code like this: movl %esi, %edi inc %edi with this: lea 1(%rsi), %edi which appears to be beneficial. llvm-svn: 61830
2009-01-07 07:34:46 +08:00
case X86::DEC32r:
case X86::DEC64_32r: {
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegOffset(BuildMI(MF, get(Opc))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, -1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
}
case X86::DEC16r:
case X86::DEC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, -1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::ADD64rr:
case X86::ADD32rr: {
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegReg(BuildMI(MF, get(Opc))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, Src2, isKill2);
if (LV && isKill2)
LV->replaceKillInstruction(Src2, MI, NewMI);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
}
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
case X86::ADD16rr: {
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, Src2, isKill2);
if (LV && isKill2)
LV->replaceKillInstruction(Src2, MI, NewMI);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
case X86::ADD64ri32:
case X86::ADD64ri8:
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(2).isImm())
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::ADD32ri:
case X86::ADD32ri8:
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(2).isImm()) {
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegOffset(BuildMI(MF, get(Opc))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::ADD16ri:
case X86::ADD16ri8:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(2).isImm())
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::SHL16ri:
if (DisableLEA16) return 0;
case X86::SHL32ri:
case X86::SHL64ri: {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
"Unknown shl instruction!");
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm llvm-svn: 45453
2007-12-31 04:49:49 +08:00
unsigned ShAmt = MI->getOperand(2).getImm();
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
X86AddressMode AM;
AM.Scale = 1 << ShAmt;
AM.IndexReg = Src;
unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
: (MIOpc == X86::SHL32ri
? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = addFullAddress(BuildMI(MF, get(Opc))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(Dest, true, false, false, isDead), AM);
if (isKill)
NewMI->getOperand(3).setIsKill(true);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
}
break;
}
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
}
}
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
In some cases, e.g. ADD32ri, no transformation is made. Guide against it. llvm-svn: 46849
2008-02-07 16:29:53 +08:00
if (!NewMI) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
if (LV) { // Update live variables
if (isKill)
LV->replaceKillInstruction(Src, MI, NewMI);
if (isDead)
LV->replaceKillInstruction(Dest, MI, NewMI);
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
MFI->insert(MBBI, NewMI); // Insert the new inst
Properly transfer kill / dead info. llvm-svn: 31765
2006-11-16 04:58:11 +08:00
return NewMI;
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
}
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
/// commuteInstruction - We have a few instructions that must be hacked on to
/// commute them.
///
Add option to commuteInstruction() which forces it to create a new (commuted) instruction. llvm-svn: 52308
2008-06-16 15:33:11 +08:00
MachineInstr *
X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
switch (MI->getOpcode()) {
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 15:31:24 +08:00
case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Add patterns for SHLD64* and SHRD64*. llvm-svn: 41975
2007-09-15 07:17:45 +08:00
case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 15:31:24 +08:00
unsigned Opc;
unsigned Size;
switch (MI->getOpcode()) {
default: assert(0 && "Unreachable!");
case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Add patterns for SHLD64* and SHRD64*. llvm-svn: 41975
2007-09-15 07:17:45 +08:00
case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 15:31:24 +08:00
}
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm llvm-svn: 45453
2007-12-31 04:49:49 +08:00
unsigned Amt = MI->getOperand(3).getImm();
Define patterns for shld and shrd that match immediate shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
2008-10-17 09:23:35 +08:00
if (NewMI) {
MachineFunction &MF = *MI->getParent()->getParent();
MI = MF.CloneMachineInstr(MI);
NewMI = false;
commuteInstr() can now commute non-ssa machine instrs. llvm-svn: 47043
2008-02-13 10:46:49 +08:00
}
Define patterns for shld and shrd that match immediate shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
2008-10-17 09:23:35 +08:00
MI->setDesc(get(Opc));
MI->getOperand(3).setImm(Size-Amt);
return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
}
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
case X86::CMOVB16rr:
case X86::CMOVB32rr:
case X86::CMOVB64rr:
case X86::CMOVAE16rr:
case X86::CMOVAE32rr:
case X86::CMOVAE64rr:
case X86::CMOVE16rr:
case X86::CMOVE32rr:
case X86::CMOVE64rr:
case X86::CMOVNE16rr:
case X86::CMOVNE32rr:
case X86::CMOVNE64rr:
case X86::CMOVBE16rr:
case X86::CMOVBE32rr:
case X86::CMOVBE64rr:
case X86::CMOVA16rr:
case X86::CMOVA32rr:
case X86::CMOVA64rr:
case X86::CMOVL16rr:
case X86::CMOVL32rr:
case X86::CMOVL64rr:
case X86::CMOVGE16rr:
case X86::CMOVGE32rr:
case X86::CMOVGE64rr:
case X86::CMOVLE16rr:
case X86::CMOVLE32rr:
case X86::CMOVLE64rr:
case X86::CMOVG16rr:
case X86::CMOVG32rr:
case X86::CMOVG64rr:
case X86::CMOVS16rr:
case X86::CMOVS32rr:
case X86::CMOVS64rr:
case X86::CMOVNS16rr:
case X86::CMOVNS32rr:
case X86::CMOVNS64rr:
case X86::CMOVP16rr:
case X86::CMOVP32rr:
case X86::CMOVP64rr:
case X86::CMOVNP16rr:
case X86::CMOVNP32rr:
Define instructions for cmovo and cmovno. llvm-svn: 61836
2009-01-07 08:35:10 +08:00
case X86::CMOVNP64rr:
case X86::CMOVO16rr:
case X86::CMOVO32rr:
case X86::CMOVO64rr:
case X86::CMOVNO16rr:
case X86::CMOVNO32rr:
case X86::CMOVNO64rr: {
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
unsigned Opc = 0;
switch (MI->getOpcode()) {
default: break;
case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Define instructions for cmovo and cmovno. llvm-svn: 61836
2009-01-07 08:35:10 +08:00
case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
case X86::CMOVO64rr: Opc = X86::CMOVNO32rr; break;
case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
}
Define patterns for shld and shrd that match immediate shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
2008-10-17 09:23:35 +08:00
if (NewMI) {
MachineFunction &MF = *MI->getParent()->getParent();
MI = MF.CloneMachineInstr(MI);
NewMI = false;
}
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
MI->setDesc(get(Opc));
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
// Fallthrough intended.
}
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
default:
Add option to commuteInstruction() which forces it to create a new (commuted) instruction. llvm-svn: 52308
2008-06-16 15:33:11 +08:00
return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
}
}
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
switch (BrOpc) {
default: return X86::COND_INVALID;
case X86::JE: return X86::COND_E;
case X86::JNE: return X86::COND_NE;
case X86::JL: return X86::COND_L;
case X86::JLE: return X86::COND_LE;
case X86::JG: return X86::COND_G;
case X86::JGE: return X86::COND_GE;
case X86::JB: return X86::COND_B;
case X86::JBE: return X86::COND_BE;
case X86::JA: return X86::COND_A;
case X86::JAE: return X86::COND_AE;
case X86::JS: return X86::COND_S;
case X86::JNS: return X86::COND_NS;
case X86::JP: return X86::COND_P;
case X86::JNP: return X86::COND_NP;
case X86::JO: return X86::COND_O;
case X86::JNO: return X86::COND_NO;
}
}
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
switch (CC) {
default: assert(0 && "Illegal condition code!");
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 08:00:36 +08:00
case X86::COND_E: return X86::JE;
case X86::COND_NE: return X86::JNE;
case X86::COND_L: return X86::JL;
case X86::COND_LE: return X86::JLE;
case X86::COND_G: return X86::JG;
case X86::COND_GE: return X86::JGE;
case X86::COND_B: return X86::JB;
case X86::COND_BE: return X86::JBE;
case X86::COND_A: return X86::JA;
case X86::COND_AE: return X86::JAE;
case X86::COND_S: return X86::JS;
case X86::COND_NS: return X86::JNS;
case X86::COND_P: return X86::JP;
case X86::COND_NP: return X86::JNP;
case X86::COND_O: return X86::JO;
case X86::COND_NO: return X86::JNO;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
}
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
/// GetOppositeBranchCondition - Return the inverse of the specified condition,
/// e.g. turning COND_E to COND_NE.
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
switch (CC) {
default: assert(0 && "Illegal condition code!");
case X86::COND_E: return X86::COND_NE;
case X86::COND_NE: return X86::COND_E;
case X86::COND_L: return X86::COND_GE;
case X86::COND_LE: return X86::COND_G;
case X86::COND_G: return X86::COND_LE;
case X86::COND_GE: return X86::COND_L;
case X86::COND_B: return X86::COND_AE;
case X86::COND_BE: return X86::COND_A;
case X86::COND_A: return X86::COND_BE;
case X86::COND_AE: return X86::COND_B;
case X86::COND_S: return X86::COND_NS;
case X86::COND_NS: return X86::COND_S;
case X86::COND_P: return X86::COND_NP;
case X86::COND_NP: return X86::COND_P;
case X86::COND_O: return X86::COND_NO;
case X86::COND_NO: return X86::COND_O;
}
}
Do not treat FP_REG_KILL as terminator in branch analysis (X86). llvm-svn: 37578
2007-06-15 06:03:45 +08:00
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
const TargetInstrDesc &TID = MI->getDesc();
if (!TID.isTerminator()) return false;
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
2008-01-07 09:56:04 +08:00
// Conditional branch is a special case.
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
if (TID.isBranch() && !TID.isBarrier())
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
2008-01-07 09:56:04 +08:00
return true;
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
if (!TID.isPredicable())
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
2008-01-07 09:56:04 +08:00
return true;
return !isPredicated(MI);
Do not treat FP_REG_KILL as terminator in branch analysis (X86). llvm-svn: 37578
2007-06-15 06:03:45 +08:00
}
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
Don't pollute the meaning of isUnpredicatedTerminator. llvm-svn: 40537
2007-07-27 01:32:14 +08:00
// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
const X86InstrInfo &TII) {
if (MI->getOpcode() == X86::FP_REG_KILL)
return false;
return TII.isUnpredicatedTerminator(MI);
}
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
2008-08-15 06:49:33 +08:00
SmallVectorImpl<MachineOperand> &Cond) const {
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Start from the bottom of the block and work up, examining the
// terminator instructions.
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
MachineBasicBlock::iterator I = MBB.end();
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
while (I != MBB.begin()) {
--I;
// Working from the bottom, when we see a non-terminator
// instruction, we're done.
if (!isBrAnalysisUnpredicatedTerminator(I, *this))
break;
// A terminator that isn't a branch can't easily be handled
// by this analysis.
if (!I->getDesc().isBranch())
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
return true;
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Handle unconditional branches.
if (I->getOpcode() == X86::JMP) {
// If the block has any instructions after a JMP, delete them.
while (next(I) != MBB.end())
next(I)->eraseFromParent();
Cond.clear();
FBB = 0;
// Delete the JMP if it's equivalent to a fall-through.
if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
TBB = 0;
I->eraseFromParent();
I = MBB.end();
continue;
}
// TBB is used to indicate the unconditinal destination.
TBB = I->getOperand(0).getMBB();
continue;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Handle conditional branches.
X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
if (BranchCode == X86::COND_INVALID)
return true; // Can't handle indirect branch.
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Working from the bottom, handle the first conditional branch.
if (Cond.empty()) {
FBB = TBB;
TBB = I->getOperand(0).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
continue;
}
// Handle subsequent conditional branches. Only handle the case
// where all conditional branches branch to the same destination
// and their condition opcodes fit one of the special
// multi-branch idioms.
assert(Cond.size() == 1);
assert(TBB);
// Only handle the case where all conditional branches branch to
// the same destination.
if (TBB != I->getOperand(0).getMBB())
return true;
X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
// If the conditions are the same, we can leave them alone.
if (OldBranchCode == BranchCode)
continue;
// If they differ, see if they fit one of the known patterns.
// Theoretically we could handle more patterns here, but
// we shouldn't expect to see them if instruction selection
// has done a reasonable job.
if ((OldBranchCode == X86::COND_NP &&
BranchCode == X86::COND_E) ||
(OldBranchCode == X86::COND_E &&
BranchCode == X86::COND_NP))
BranchCode = X86::COND_NP_OR_E;
else if ((OldBranchCode == X86::COND_P &&
BranchCode == X86::COND_NE) ||
(OldBranchCode == X86::COND_NE &&
BranchCode == X86::COND_P))
BranchCode = X86::COND_NE_OR_P;
else
return true;
// Update the MachineOperand.
Cond[0].setImm(BranchCode);
Handle blocks with 2 unconditional branches in AnalyzeBranch. llvm-svn: 37571
2007-06-14 01:59:52 +08:00
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
return false;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37193
2007-05-18 08:18:17 +08:00
unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
MachineBasicBlock::iterator I = MBB.end();
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
unsigned Count = 0;
while (I != MBB.begin()) {
--I;
if (I->getOpcode() != X86::JMP &&
GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
break;
// Remove the branch.
I->eraseFromParent();
I = MBB.end();
++Count;
}
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
return Count;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
Const-ify several TargetInstrInfo methods. llvm-svn: 57622
2008-10-16 09:49:15 +08:00
const MachineOperand &MO) {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg())
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
MO.isKill(), MO.isDead(), MO.getSubReg());
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isImm())
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
MIB = MIB.addImm(MO.getImm());
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isFI())
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
MIB = MIB.addFrameIndex(MO.getIndex());
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isGlobal())
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isCPI())
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isJTI())
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
MIB = MIB.addJumpTableIndex(MO.getIndex());
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isSymbol())
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
MIB = MIB.addExternalSymbol(MO.getSymbolName());
else
assert(0 && "Unknown operand for X86InstrAddOperand!");
return MIB;
}
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37193
2007-05-18 08:18:17 +08:00
unsigned
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
2008-08-15 06:49:33 +08:00
const SmallVectorImpl<MachineOperand> &Cond) const {
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
allow insertion of a conditional branch with fall-through llvm-svn: 31095
2006-10-21 13:34:23 +08:00
assert((Cond.size() == 1 || Cond.size() == 0) &&
"X86 branch conditions have one component!");
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if (Cond.empty()) {
// Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!");
BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37193
2007-05-18 08:18:17 +08:00
return 1;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Conditional branch.
unsigned Count = 0;
X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
switch (CC) {
case X86::COND_NP_OR_E:
// Synthesize NP_OR_E with two branches.
BuildMI(&MBB, get(X86::JNP)).addMBB(TBB);
++Count;
BuildMI(&MBB, get(X86::JE)).addMBB(TBB);
++Count;
break;
case X86::COND_NE_OR_P:
// Synthesize NE_OR_P with two branches.
BuildMI(&MBB, get(X86::JNE)).addMBB(TBB);
++Count;
BuildMI(&MBB, get(X86::JP)).addMBB(TBB);
++Count;
break;
default: {
unsigned Opc = GetCondBranchFromCond(CC);
BuildMI(&MBB, get(Opc)).addMBB(TBB);
++Count;
}
}
if (FBB) {
// Two-way Conditional branch. Insert the second branch.
BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
++Count;
}
return Count;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
if (DestRC == SrcRC) {
unsigned Opc;
if (DestRC == &X86::GR64RegClass) {
Opc = X86::MOV64rr;
} else if (DestRC == &X86::GR32RegClass) {
Opc = X86::MOV32rr;
} else if (DestRC == &X86::GR16RegClass) {
Opc = X86::MOV16rr;
} else if (DestRC == &X86::GR8RegClass) {
Opc = X86::MOV8rr;
} else if (DestRC == &X86::GR32_RegClass) {
Opc = X86::MOV32_rr;
} else if (DestRC == &X86::GR16_RegClass) {
Opc = X86::MOV16_rr;
} else if (DestRC == &X86::RFP32RegClass) {
Opc = X86::MOV_Fp3232;
} else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
Opc = X86::MOV_Fp6464;
} else if (DestRC == &X86::RFP80RegClass) {
Opc = X86::MOV_Fp8080;
} else if (DestRC == &X86::FR32RegClass) {
Opc = X86::FsMOVAPSrr;
} else if (DestRC == &X86::FR64RegClass) {
Opc = X86::FsMOVAPDrr;
} else if (DestRC == &X86::VR128RegClass) {
Opc = X86::MOVAPSrr;
} else if (DestRC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rr;
} else {
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return false;
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the Machine-level API cleanup instigated by Chris. llvm-svn: 45470
2007-12-31 14:32:00 +08:00
}
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return true;
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the Machine-level API cleanup instigated by Chris. llvm-svn: 45470
2007-12-31 14:32:00 +08:00
}
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
// Moving EFLAGS to / from another register requires a push and a pop.
if (SrcRC == &X86::CCRRegClass) {
These assertions should be return false's instead, allowing the client to detect the failure. llvm-svn: 55377
2008-08-27 02:50:40 +08:00
if (SrcReg != X86::EFLAGS)
return false;
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
if (DestRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFQ));
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return true;
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
} else if (DestRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFD));
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return true;
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
}
} else if (DestRC == &X86::CCRRegClass) {
These assertions should be return false's instead, allowing the client to detect the failure. llvm-svn: 55377
2008-08-27 02:50:40 +08:00
if (DestReg != X86::EFLAGS)
return false;
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
if (SrcRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFQ));
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return true;
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
} else if (SrcRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFD));
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return true;
rearrange some code, no functionality change. llvm-svn: 48101
2008-03-09 15:58:04 +08:00
}
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the Machine-level API cleanup instigated by Chris. llvm-svn: 45470
2007-12-31 14:32:00 +08:00
}
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
2008-03-09 17:15:31 +08:00
// Moving from ST(0) turns into FpGET_ST0_32 etc.
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
if (SrcRC == &X86::RSTRegClass) {
Add support for calls that return two FP values in ST(0)/ST(1). llvm-svn: 48634
2008-03-21 14:38:26 +08:00
// Copying from ST(0)/ST(1).
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
// Can only copy from ST(0)/ST(1) right now
return false;
Add support for calls that return two FP values in ST(0)/ST(1). llvm-svn: 48634
2008-03-21 14:38:26 +08:00
bool isST0 = SrcReg == X86::ST0;
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
unsigned Opc;
if (DestRC == &X86::RFP32RegClass)
Add support for calls that return two FP values in ST(0)/ST(1). llvm-svn: 48634
2008-03-21 14:38:26 +08:00
Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
else if (DestRC == &X86::RFP64RegClass)
Add support for calls that return two FP values in ST(0)/ST(1). llvm-svn: 48634
2008-03-21 14:38:26 +08:00
Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
else {
These assertions should be return false's instead, allowing the client to detect the failure. llvm-svn: 55377
2008-08-27 02:50:40 +08:00
if (DestRC != &X86::RFP80RegClass)
return false;
Add support for calls that return two FP values in ST(0)/ST(1). llvm-svn: 48634
2008-03-21 14:38:26 +08:00
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
}
BuildMI(MBB, MI, get(Opc), DestReg);
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return true;
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
}
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
2008-03-09 17:15:31 +08:00
// Moving to ST(0) turns into FpSET_ST0_32 etc.
if (DestRC == &X86::RSTRegClass) {
// Copying to ST(0). FIXME: handle ST(1) also
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
if (DestReg != X86::ST0)
// Can only copy to TOS right now
return false;
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
2008-03-09 17:15:31 +08:00
unsigned Opc;
if (SrcRC == &X86::RFP32RegClass)
Opc = X86::FpSET_ST0_32;
else if (SrcRC == &X86::RFP64RegClass)
Opc = X86::FpSET_ST0_64;
else {
These assertions should be return false's instead, allowing the client to detect the failure. llvm-svn: 55377
2008-08-27 02:50:40 +08:00
if (SrcRC != &X86::RFP80RegClass)
return false;
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
2008-03-09 17:15:31 +08:00
Opc = X86::FpSET_ST0_80;
}
BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
return true;
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
2008-03-09 17:15:31 +08:00
}
add some code to support cross-register class copying from RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
2008-03-09 16:46:19 +08:00
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
2008-08-27 02:03:31 +08:00
// Not yet supported!
return false;
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the Machine-level API cleanup instigated by Chris. llvm-svn: 45470
2007-12-31 14:32:00 +08:00
}
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
bool isStackAligned) {
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
unsigned Opc = 0;
if (RC == &X86::GR64RegClass) {
Opc = X86::MOV64mr;
} else if (RC == &X86::GR32RegClass) {
Opc = X86::MOV32mr;
} else if (RC == &X86::GR16RegClass) {
Opc = X86::MOV16mr;
} else if (RC == &X86::GR8RegClass) {
Opc = X86::MOV8mr;
} else if (RC == &X86::GR32_RegClass) {
Opc = X86::MOV32_mr;
} else if (RC == &X86::GR16_RegClass) {
Opc = X86::MOV16_mr;
} else if (RC == &X86::RFP80RegClass) {
Opc = X86::ST_FpP80m; // pops
} else if (RC == &X86::RFP64RegClass) {
Opc = X86::ST_Fp64m;
} else if (RC == &X86::RFP32RegClass) {
Opc = X86::ST_Fp32m;
} else if (RC == &X86::FR32RegClass) {
Opc = X86::MOVSSmr;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDmr;
} else if (RC == &X86::VR128RegClass) {
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
// If stack is realigned we can use aligned stores.
Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
} else if (RC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64mr;
} else {
assert(0 && "Unknown regclass");
abort();
}
return Opc;
}
void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC) const {
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
const MachineFunction &MF = *MBB.getParent();
Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions. llvm-svn: 53844
2008-07-21 14:34:17 +08:00
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getStoreRegOpcode(RC, isAligned);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
.addReg(SrcReg, false, false, isKill);
}
void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
bool isKill,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions. llvm-svn: 53844
2008-07-21 14:34:17 +08:00
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getStoreRegOpcode(RC, isAligned);
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, Addr[i]);
MIB.addReg(SrcReg, false, false, isKill);
NewMIs.push_back(MIB);
}
static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
bool isStackAligned) {
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
unsigned Opc = 0;
if (RC == &X86::GR64RegClass) {
Opc = X86::MOV64rm;
} else if (RC == &X86::GR32RegClass) {
Opc = X86::MOV32rm;
} else if (RC == &X86::GR16RegClass) {
Opc = X86::MOV16rm;
} else if (RC == &X86::GR8RegClass) {
Opc = X86::MOV8rm;
} else if (RC == &X86::GR32_RegClass) {
Opc = X86::MOV32_rm;
} else if (RC == &X86::GR16_RegClass) {
Opc = X86::MOV16_rm;
} else if (RC == &X86::RFP80RegClass) {
Opc = X86::LD_Fp80m;
} else if (RC == &X86::RFP64RegClass) {
Opc = X86::LD_Fp64m;
} else if (RC == &X86::RFP32RegClass) {
Opc = X86::LD_Fp32m;
} else if (RC == &X86::FR32RegClass) {
Opc = X86::MOVSSrm;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDrm;
} else if (RC == &X86::VR128RegClass) {
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
// If stack is realigned we can use aligned loads.
Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
} else if (RC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rm;
} else {
assert(0 && "Unknown regclass");
abort();
}
return Opc;
}
void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{
const MachineFunction &MF = *MBB.getParent();
Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions. llvm-svn: 53844
2008-07-21 14:34:17 +08:00
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getLoadRegOpcode(RC, isAligned);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
}
void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
SmallVectorImpl<MachineInstr*> &NewMIs) const {
Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions. llvm-svn: 53844
2008-07-21 14:34:17 +08:00
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getLoadRegOpcode(RC, isAligned);
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, Addr[i]);
NewMIs.push_back(MIB);
}
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
Revert r56675 - it breaks unwinding runtime everywhere. llvm-svn: 57048
2008-10-04 19:09:36 +08:00
MachineBasicBlock::iterator MI,
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
const std::vector<CalleeSavedInfo> &CSI) const {
if (CSI.empty())
return false;
Avoid spilling EBP / RBP twice in the prologue. llvm-svn: 56675
2008-09-27 03:14:21 +08:00
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
Revert r56675 - it breaks unwinding runtime everywhere. llvm-svn: 57048
2008-10-04 19:09:36 +08:00
unsigned SlotSize = is64Bit ? 8 : 4;
MachineFunction &MF = *MBB.getParent();
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
for (unsigned i = CSI.size(); i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
Fish kill flag annotations in PUSH instructions. llvm-svn: 60095
2008-11-26 14:39:12 +08:00
BuildMI(MBB, MI, get(Opc))
.addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
}
return true;
}
bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
Revert r56675 - it breaks unwinding runtime everywhere. llvm-svn: 57048
2008-10-04 19:09:36 +08:00
MachineBasicBlock::iterator MI,
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
const std::vector<CalleeSavedInfo> &CSI) const {
if (CSI.empty())
return false;
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
BuildMI(MBB, MI, get(Opc), Reg);
}
return true;
}
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
const SmallVectorImpl<MachineOperand> &MOs,
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstr *MI, const TargetInstrInfo &TII) {
// Create the base instruction with the memory operand as the first part.
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstrBuilder MIB(NewMI);
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
MIB = X86InstrAddOperand(MIB, MOs[i]);
if (NumAddrOps < 4) // FrameIndex only
MIB.addImm(1).addReg(0).addImm(0);
// Loop over the rest of the ri operands, converting them over.
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
unsigned NumOps = MI->getDesc().getNumOperands()-2;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
for (unsigned i = 0; i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i+2);
MIB = X86InstrAddOperand(MIB, MO);
}
for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
MIB = X86InstrAddOperand(MIB, MO);
}
return MIB;
}
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
static MachineInstr *FuseInst(MachineFunction &MF,
unsigned Opcode, unsigned OpNo,
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
const SmallVectorImpl<MachineOperand> &MOs,
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstr *MI, const TargetInstrInfo &TII) {
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstrBuilder MIB(NewMI);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (i == OpNo) {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
assert(MO.isReg() && "Expected to fold into reg operand!");
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
MIB = X86InstrAddOperand(MIB, MOs[i]);
if (NumAddrOps < 4) // FrameIndex only
MIB.addImm(1).addReg(0).addImm(0);
} else {
MIB = X86InstrAddOperand(MIB, MO);
}
}
return MIB;
}
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
const SmallVectorImpl<MachineOperand> &MOs,
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstr *MI) {
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineFunction &MF = *MI->getParent()->getParent();
MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
MIB = X86InstrAddOperand(MIB, MOs[i]);
if (NumAddrOps < 4) // FrameIndex only
MIB.addImm(1).addReg(0).addImm(0);
return MIB.addImm(0);
}
MachineInstr*
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI, unsigned i,
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
const SmallVectorImpl<MachineOperand> &MOs) const{
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
bool isTwoAddrFold = false;
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
unsigned NumOps = MI->getDesc().getNumOperands();
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
bool isTwoAddr = NumOps > 1 &&
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// replacing the *two* registers with the memory location.
if (isTwoAddr && NumOps >= 2 && i < 2 &&
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
MI->getOperand(0).isReg() &&
MI->getOperand(1).isReg() &&
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
isTwoAddrFold = true;
} else if (i == 0) { // If operand 0
if (MI->getOpcode() == X86::MOV16r0)
NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
else if (MI->getOpcode() == X86::MOV32r0)
NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
else if (MI->getOpcode() == X86::MOV64r0)
NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
else if (MI->getOpcode() == X86::MOV8r0)
NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
if (NewMI)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return NewMI;
OpcodeTablePtr = &RegOp2MemOpTable0;
} else if (i == 1) {
OpcodeTablePtr = &RegOp2MemOpTable1;
} else if (i == 2) {
OpcodeTablePtr = &RegOp2MemOpTable2;
}
// If table selected...
if (OpcodeTablePtr) {
// Find the Opcode to fuse
DenseMap<unsigned*, unsigned>::iterator I =
OpcodeTablePtr->find((unsigned*)MI->getOpcode());
if (I != OpcodeTablePtr->end()) {
if (isTwoAddrFold)
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
else
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return NewMI;
}
}
// No fusion
if (PrintFailedFusing)
Make the fuse-failed debug output human-readable. llvm-svn: 61356
2008-12-23 08:19:20 +08:00
cerr << "We failed to fuse operand " << i << " in " << *MI;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return NULL;
}
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Check switch flag
if (NoFusing) return NULL;
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
2008-02-09 05:20:40 +08:00
const MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
// FIXME: Move alignment requirement into tables?
if (Alignment < 16) {
switch (MI->getOpcode()) {
default: break;
// Not always safe to fold movsd into these instructions since their load
// folding variants expects the address to be 16 byte aligned.
case X86::FsANDNPDrr:
case X86::FsANDNPSrr:
case X86::FsANDPDrr:
case X86::FsANDPSrr:
case X86::FsORPDrr:
case X86::FsORPSrr:
case X86::FsXORPDrr:
case X86::FsXORPSrr:
return NULL;
}
}
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
unsigned NewOpc = 0;
switch (MI->getOpcode()) {
default: return NULL;
case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
}
// Change to CMPXXri r, 0 first.
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
MI->setDesc(get(NewOpc));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MI->getOperand(1).ChangeToImmediate(0);
} else if (Ops.size() != 1)
return NULL;
SmallVector<MachineOperand,4> MOs;
MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops,
MachineInstr *LoadMI) const {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Check switch flag
if (NoFusing) return NULL;
Add a utility function to MachineInstr for testing whether an instruction has exactly one MachineMemOperand, and change some X86 lowering code to make use of it. llvm-svn: 53498
2008-07-12 08:10:52 +08:00
// Determine the alignment of the load.
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
2008-02-09 05:20:40 +08:00
unsigned Alignment = 0;
Add a utility function to MachineInstr for testing whether an instruction has exactly one MachineMemOperand, and change some X86 lowering code to make use of it. llvm-svn: 53498
2008-07-12 08:10:52 +08:00
if (LoadMI->hasOneMemOperand())
Alignment = LoadMI->memoperands_begin()->getAlignment();
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
2008-02-09 05:20:40 +08:00
// FIXME: Move alignment requirement into tables?
if (Alignment < 16) {
switch (MI->getOpcode()) {
default: break;
// Not always safe to fold movsd into these instructions since their load
// folding variants expects the address to be 16 byte aligned.
case X86::FsANDNPDrr:
case X86::FsANDNPSrr:
case X86::FsANDPDrr:
case X86::FsANDPSrr:
case X86::FsORPDrr:
case X86::FsORPSrr:
case X86::FsXORPDrr:
case X86::FsXORPSrr:
return NULL;
}
}
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
unsigned NewOpc = 0;
switch (MI->getOpcode()) {
default: return NULL;
case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
}
// Change to CMPXXri r, 0 first.
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
MI->setDesc(get(NewOpc));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MI->getOperand(1).ChangeToImmediate(0);
} else if (Ops.size() != 1)
return NULL;
SmallVector<MachineOperand,4> MOs;
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
if (LoadMI->getOpcode() == X86::V_SET0 ||
LoadMI->getOpcode() == X86::V_SETALLONES) {
// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
// Create a constant-pool entry and operands to load from it.
// x86-32 PIC requires a PIC base register for constant pools.
unsigned PICBase = 0;
if (TM.getRelocationModel() == Reloc::PIC_ &&
!TM.getSubtarget<X86Subtarget>().is64Bit())
Effectively undo 60461 in PIC mode which simply transform V_SET0 / V_SETALLONES into a load from constpool in order to fold into restores. This is not safe to do when PIC base is being used for a number of reasons: 1. GlobalBaseReg may have been spilled. 2. It may not be live at the use. 3. Spiller doesn't know this is happening so it won't prevent GlobalBaseReg from being spilled later (That by itself is a nasty hack. It's needed because we don't insert the reload until later). llvm-svn: 60595
2008-12-06 01:23:48 +08:00
// FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
// This doesn't work for several reasons.
// 1. GlobalBaseReg may have been spilled.
// 2. It may not be live at MI.
return false;
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
// Create a v4i32 constant-pool entry.
MachineConstantPool &MCP = *MF.getConstantPool();
const VectorType *Ty = VectorType::get(Type::Int32Ty, 4);
Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
ConstantVector::getNullValue(Ty) :
ConstantVector::getAllOnesValue(Ty);
unsigned CPI = MCP.getConstantPoolIndex(C, /*AlignmentLog2=*/4);
// Create operands to load from the constant pool entry.
MOs.push_back(MachineOperand::CreateReg(PICBase, false));
MOs.push_back(MachineOperand::CreateImm(1));
MOs.push_back(MachineOperand::CreateReg(0, false));
MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
} else {
// Folding a normal load. Just copy the load's address operands.
unsigned NumOps = LoadMI->getDesc().getNumOperands();
for (unsigned i = NumOps - 4; i != NumOps; ++i)
MOs.push_back(LoadMI->getOperand(i));
}
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
Const-ify several TargetInstrInfo methods. llvm-svn: 57622
2008-10-16 09:49:15 +08:00
bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops) const {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Check switch flag
if (NoFusing) return 0;
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
switch (MI->getOpcode()) {
default: return false;
case X86::TEST8rr:
case X86::TEST16rr:
case X86::TEST32rr:
case X86::TEST64rr:
return true;
}
}
if (Ops.size() != 1)
return false;
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
unsigned NumOps = MI->getDesc().getNumOperands();
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
bool isTwoAddr = NumOps > 1 &&
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// replacing the *two* registers with the memory location.
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
} else if (OpNum == 0) { // If operand 0
switch (Opc) {
case X86::MOV16r0:
case X86::MOV32r0:
case X86::MOV64r0:
case X86::MOV8r0:
return true;
default: break;
}
OpcodeTablePtr = &RegOp2MemOpTable0;
} else if (OpNum == 1) {
OpcodeTablePtr = &RegOp2MemOpTable1;
} else if (OpNum == 2) {
OpcodeTablePtr = &RegOp2MemOpTable2;
}
if (OpcodeTablePtr) {
// Find the Opcode to fuse
DenseMap<unsigned*, unsigned>::iterator I =
OpcodeTablePtr->find((unsigned*)Opc);
if (I != OpcodeTablePtr->end())
return true;
}
return false;
}
bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
if (I == MemOp2RegOpTable.end())
return false;
unsigned Opc = I->second.first;
unsigned Index = I->second.second & 0xf;
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
if (UnfoldLoad && !FoldedLoad)
return false;
UnfoldLoad &= FoldedLoad;
if (UnfoldStore && !FoldedStore)
return false;
UnfoldStore &= FoldedStore;
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
const TargetInstrDesc &TID = get(Opc);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
const TargetOperandInfo &TOI = TID.OpInfo[Index];
Add predicates methods to TargetOperandInfo, and switch all clients over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. llvm-svn: 45677
2008-01-07 10:39:19 +08:00
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
SmallVector<MachineOperand,4> AddrOps;
SmallVector<MachineOperand,2> BeforeOps;
SmallVector<MachineOperand,2> AfterOps;
SmallVector<MachineOperand,4> ImpOps;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
if (i >= Index && i < Index+4)
AddrOps.push_back(Op);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (Op.isReg() && Op.isImplicit())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
ImpOps.push_back(Op);
else if (i < Index)
BeforeOps.push_back(Op);
else if (i > Index)
AfterOps.push_back(Op);
}
// Emit the load instruction.
if (UnfoldLoad) {
loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
if (UnfoldStore) {
// Address operands cannot be marked isKill.
for (unsigned i = 1; i != 5; ++i) {
MachineOperand &MO = NewMIs[0]->getOperand(i);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MO.setIsKill(false);
}
}
}
// Emit the data processing instruction.
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstr *DataMI = MF.CreateMachineInstr(TID, true);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstrBuilder MIB(DataMI);
if (FoldedStore)
MIB.addReg(Reg, true);
for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
if (FoldedLoad)
MIB.addReg(Reg);
for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, AfterOps[i]);
for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
MachineOperand &MO = ImpOps[i];
MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
}
// Change CMP32ri r, 0 back to TEST32rr r, r, etc.
unsigned NewOpc = 0;
switch (DataMI->getOpcode()) {
default: break;
case X86::CMP64ri32:
case X86::CMP32ri:
case X86::CMP16ri:
case X86::CMP8ri: {
MachineOperand &MO0 = DataMI->getOperand(0);
MachineOperand &MO1 = DataMI->getOperand(1);
if (MO1.getImm() == 0) {
switch (DataMI->getOpcode()) {
default: break;
case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
}
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
DataMI->setDesc(get(NewOpc));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MO1.ChangeToRegister(MO0.getReg(), false);
}
}
}
NewMIs.push_back(DataMI);
// Emit the store instruction.
if (UnfoldStore) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
Add predicates methods to TargetOperandInfo, and switch all clients over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. llvm-svn: 45677
2008-01-07 10:39:19 +08:00
const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
}
return true;
}
bool
X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
SmallVectorImpl<SDNode*> &NewNodes) const {
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
2008-07-18 03:10:17 +08:00
if (!N->isMachineOpcode())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return false;
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
2008-07-18 03:10:17 +08:00
MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (I == MemOp2RegOpTable.end())
return false;
unsigned Opc = I->second.first;
unsigned Index = I->second.second & 0xf;
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
const TargetInstrDesc &TID = get(Opc);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
const TargetOperandInfo &TOI = TID.OpInfo[Index];
Add predicates methods to TargetOperandInfo, and switch all clients over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. llvm-svn: 45677
2008-01-07 10:39:19 +08:00
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
std::vector<SDValue> AddrOps;
std::vector<SDValue> BeforeOps;
std::vector<SDValue> AfterOps;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
unsigned NumOps = N->getNumOperands();
for (unsigned i = 0; i != NumOps-1; ++i) {
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Op = N->getOperand(i);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (i >= Index && i < Index+4)
AddrOps.push_back(Op);
else if (i < Index)
BeforeOps.push_back(Op);
else if (i > Index)
AfterOps.push_back(Op);
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Chain = N->getOperand(NumOps-1);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AddrOps.push_back(Chain);
// Emit the load instruction.
SDNode *Load = 0;
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
const MachineFunction &MF = DAG.getMachineFunction();
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (FoldedLoad) {
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
MVT VT = *RC->vt_begin();
Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions. llvm-svn: 53844
2008-07-21 14:34:17 +08:00
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned),
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
VT, MVT::Other,
&AddrOps[0], AddrOps.size());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
NewNodes.push_back(Load);
}
// Emit the data processing instruction.
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
std::vector<MVT> VTs;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
const TargetRegisterClass *DstRC = 0;
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor llvm-svn: 45680
2008-01-07 11:13:06 +08:00
if (TID.getNumDefs() > 0) {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
Add predicates methods to TargetOperandInfo, and switch all clients over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. llvm-svn: 45677
2008-01-07 10:39:19 +08:00
DstRC = DstTOI.isLookupPtrRegClass()
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
MVT VT = N->getValueType(i);
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor llvm-svn: 45680
2008-01-07 11:13:06 +08:00
if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
VTs.push_back(VT);
}
if (Load)
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
BeforeOps.push_back(SDValue(Load, 0));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
NewNodes.push_back(NewNode);
// Emit the store instruction.
if (FoldedStore) {
AddrOps.pop_back();
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
AddrOps.push_back(SDValue(NewNode, 0));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AddrOps.push_back(Chain);
Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions. llvm-svn: 53844
2008-07-21 14:34:17 +08:00
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned),
MVT::Other, &AddrOps[0], AddrOps.size());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
NewNodes.push_back(Store);
}
return true;
}
unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
bool UnfoldLoad, bool UnfoldStore) const {
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
MemOp2RegOpTable.find((unsigned*)Opc);
if (I == MemOp2RegOpTable.end())
return 0;
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
if (UnfoldLoad && !FoldedLoad)
return 0;
if (UnfoldStore && !FoldedStore)
return 0;
return I->second.first;
}
Const-ify several TargetInstrInfo methods. llvm-svn: 57622
2008-10-16 09:49:15 +08:00
bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
add another target hook for branch folding. llvm-svn: 31262
2006-10-29 01:29:57 +08:00
if (MBB.empty()) return false;
switch (MBB.back().getOpcode()) {
Added tail call optimization to the x86 back end. It can be enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden llvm-svn: 42870
2007-10-12 03:40:01 +08:00
case X86::TCRETURNri:
case X86::TCRETURNdi:
BlockHasNoFallThrough() now returns true if block ends with a return instruction. llvm-svn: 37266
2007-05-22 02:44:17 +08:00
case X86::RET: // Return.
case X86::RETI:
case X86::TAILJMPd:
case X86::TAILJMPr:
case X86::TAILJMPm:
add another target hook for branch folding. llvm-svn: 31262
2006-10-29 01:29:57 +08:00
case X86::JMP: // Uncond branch.
case X86::JMP32r: // Indirect branch.
Add 64-bit jmp instructions to the list of instructions that can terminate a block with no fall-through. llvm-svn: 42029
2007-09-17 23:19:08 +08:00
case X86::JMP64r: // Indirect branch (64-bit).
add another target hook for branch folding. llvm-svn: 31262
2006-10-29 01:29:57 +08:00
case X86::JMP32m: // Indirect branch through mem.
Add 64-bit jmp instructions to the list of instructions that can terminate a block with no fall-through. llvm-svn: 42029
2007-09-17 23:19:08 +08:00
case X86::JMP64m: // Indirect branch through mem (64-bit).
add another target hook for branch folding. llvm-svn: 31262
2006-10-29 01:29:57 +08:00
return true;
default: return false;
}
}
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
bool X86InstrInfo::
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
2008-08-15 06:49:33 +08:00
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Use static_cast instead of C style cast. llvm-svn: 55552
2008-08-30 07:21:31 +08:00
X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
return true;
Use static_cast instead of C style cast. llvm-svn: 55552
2008-08-30 07:21:31 +08:00
Cond[0].setImm(GetOppositeBranchCondition(CC));
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
return false;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. llvm-svn: 58230
2008-10-27 15:14:50 +08:00
bool X86InstrInfo::
IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
// FIXME: Ignore bariers of x87 stack registers for now. We can't
// allow any loads of these registers before FpGet_ST0_80.
return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
}
Committing X86-64 support. llvm-svn: 30177
2006-09-08 14:48:29 +08:00
const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
if (Subtarget->is64Bit())
return &X86::GR64RegClass;
else
return &X86::GR32RegClass;
}
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
switch (Desc->TSFlags & X86II::ImmMask) {
case X86II::Imm8: return 1;
case X86II::Imm16: return 2;
case X86II::Imm32: return 4;
case X86II::Imm64: return 8;
default: assert(0 && "Immediate size not set!");
return 0;
}
}
/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
/// e.g. r8, xmm8, etc.
bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (!MO.isReg()) return false;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
switch (MO.getReg()) {
default: break;
case X86::R8: case X86::R9: case X86::R10: case X86::R11:
case X86::R12: case X86::R13: case X86::R14: case X86::R15:
case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
return true;
}
return false;
}
/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
/// size, and 3) use of X86-64 extended registers.
unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
unsigned REX = 0;
const TargetInstrDesc &Desc = MI.getDesc();
// Pseudo instructions do not need REX prefix byte.
if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
return 0;
if (Desc.TSFlags & X86II::REX_W)
REX |= 1 << 3;
unsigned NumOps = Desc.getNumOperands();
if (NumOps) {
bool isTwoAddr = NumOps > 1 &&
Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
unsigned i = isTwoAddr ? 1 : 0;
for (unsigned e = NumOps; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
unsigned Reg = MO.getReg();
if (isX86_64NonExtLowByteReg(Reg))
REX |= 0x40;
}
}
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::MRMInitReg:
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= (1 << 0) | (1 << 2);
break;
case X86II::MRMSrcReg: {
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= 1 << 2;
i = isTwoAddr ? 2 : 1;
for (unsigned e = NumOps; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
if (isX86_64ExtendedReg(MO))
REX |= 1 << 0;
}
break;
}
case X86II::MRMSrcMem: {
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= 1 << 2;
unsigned Bit = 0;
i = isTwoAddr ? 2 : 1;
for (; i != NumOps; ++i) {
const MachineOperand& MO = MI.getOperand(i);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
if (isX86_64ExtendedReg(MO))
REX |= 1 << Bit;
Bit++;
}
}
break;
}
case X86II::MRM0m: case X86II::MRM1m:
case X86II::MRM2m: case X86II::MRM3m:
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m:
case X86II::MRMDestMem: {
unsigned e = isTwoAddr ? 5 : 4;
i = isTwoAddr ? 1 : 0;
if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
REX |= 1 << 2;
unsigned Bit = 0;
for (; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
if (isX86_64ExtendedReg(MO))
REX |= 1 << Bit;
Bit++;
}
}
break;
}
default: {
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= 1 << 0;
i = isTwoAddr ? 2 : 1;
for (unsigned e = NumOps; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
if (isX86_64ExtendedReg(MO))
REX |= 1 << 2;
}
break;
}
}
}
return REX;
}
/// sizePCRelativeBlockAddress - This method returns the size of a PC
/// relative block address instruction
///
static unsigned sizePCRelativeBlockAddress() {
return 4;
}
/// sizeGlobalAddress - Give the size of the emission of this global address
///
static unsigned sizeGlobalAddress(bool dword) {
return dword ? 8 : 4;
}
/// sizeConstPoolAddress - Give the size of the emission of this constant
/// pool address
///
static unsigned sizeConstPoolAddress(bool dword) {
return dword ? 8 : 4;
}
/// sizeExternalSymbolAddress - Give the size of the emission of this external
/// symbol
///
static unsigned sizeExternalSymbolAddress(bool dword) {
return dword ? 8 : 4;
}
/// sizeJumpTableAddress - Give the size of the emission of this jump
/// table address
///
static unsigned sizeJumpTableAddress(bool dword) {
return dword ? 8 : 4;
}
static unsigned sizeConstant(unsigned Size) {
return Size;
}
static unsigned sizeRegModRMByte(){
return 1;
}
static unsigned sizeSIBByte(){
return 1;
}
static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
unsigned FinalSize = 0;
// If this is a simple integer displacement that doesn't require a relocation.
if (!RelocOp) {
FinalSize += sizeConstant(4);
return FinalSize;
}
// Otherwise, this is something that requires a relocation.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (RelocOp->isGlobal()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeGlobalAddress(false);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (RelocOp->isCPI()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstPoolAddress(false);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (RelocOp->isJTI()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeJumpTableAddress(false);
} else {
assert(0 && "Unknown value to relocate!");
}
return FinalSize;
}
static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
bool IsPIC, bool Is64BitMode) {
const MachineOperand &Op3 = MI.getOperand(Op+3);
int DispVal = 0;
const MachineOperand *DispForReloc = 0;
unsigned FinalSize = 0;
// Figure out what sort of displacement we have to handle here.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (Op3.isGlobal()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
DispForReloc = &Op3;
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (Op3.isCPI()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
if (Is64BitMode || IsPIC) {
DispForReloc = &Op3;
} else {
DispVal = 1;
}
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (Op3.isJTI()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
if (Is64BitMode || IsPIC) {
DispForReloc = &Op3;
} else {
DispVal = 1;
}
} else {
DispVal = 1;
}
const MachineOperand &Base = MI.getOperand(Op);
const MachineOperand &IndexReg = MI.getOperand(Op+2);
unsigned BaseReg = Base.getReg();
// Is a SIB byte needed?
if (IndexReg.getReg() == 0 &&
(BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
if (BaseReg == 0) { // Just a displacement?
// Emit special case [disp32] encoding
++FinalSize;
FinalSize += getDisplacementFieldSize(DispForReloc);
} else {
unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
// Emit simple indirect register encoding... [EAX] f.e.
++FinalSize;
// Be pessimistic and assume it's a disp32, not a disp8
} else {
// Emit the most general non-SIB encoding: [REG+disp32]
++FinalSize;
FinalSize += getDisplacementFieldSize(DispForReloc);
}
}
} else { // We need a SIB byte, so start by outputting the ModR/M byte first
assert(IndexReg.getReg() != X86::ESP &&
IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
bool ForceDisp32 = false;
if (BaseReg == 0 || DispForReloc) {
// Emit the normal disp32 encoding.
++FinalSize;
ForceDisp32 = true;
} else {
++FinalSize;
}
FinalSize += sizeSIBByte();
// Do we need to output a displacement?
if (DispVal != 0 || ForceDisp32) {
FinalSize += getDisplacementFieldSize(DispForReloc);
}
}
return FinalSize;
}
static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
const TargetInstrDesc *Desc,
bool IsPIC, bool Is64BitMode) {
unsigned Opcode = Desc->Opcode;
unsigned FinalSize = 0;
// Emit the lock opcode prefix as needed.
if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
Update size of inst correctly with segment override. llvm-svn: 57414
2008-10-12 18:30:11 +08:00
// Emit segment overrid opcode prefix as needed.
switch (Desc->TSFlags & X86II::SegOvrMask) {
case X86II::FS:
case X86II::GS:
++FinalSize;
break;
default: assert(0 && "Invalid segment!");
case 0: break; // No segment override!
}
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
// Emit the repeat opcode prefix as needed.
if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
// Emit the operand size opcode prefix as needed.
if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
// Emit the address size opcode prefix as needed.
if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
bool Need0FPrefix = false;
switch (Desc->TSFlags & X86II::Op0Mask) {
case X86II::TB: // Two-byte opcode prefix
case X86II::T8: // 0F 38
case X86II::TA: // 0F 3A
Need0FPrefix = true;
break;
case X86II::REP: break; // already handled.
case X86II::XS: // F3 0F
++FinalSize;
Need0FPrefix = true;
break;
case X86II::XD: // F2 0F
++FinalSize;
Need0FPrefix = true;
break;
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
++FinalSize;
break; // Two-byte opcode prefix
default: assert(0 && "Invalid prefix!");
case 0: break; // No prefix!
}
if (Is64BitMode) {
// REX prefix
unsigned REX = X86InstrInfo::determineREX(MI);
if (REX)
++FinalSize;
}
// 0x0F escape code must be emitted just before the opcode.
if (Need0FPrefix)
++FinalSize;
switch (Desc->TSFlags & X86II::Op0Mask) {
case X86II::T8: // 0F 38
++FinalSize;
break;
case X86II::TA: // 0F 3A
++FinalSize;
break;
}
// If this is a two-address instruction, skip one of the register operands.
unsigned NumOps = Desc->getNumOperands();
unsigned CurOp = 0;
if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
CurOp++;
switch (Desc->TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
// Remember the current PC offset, this is the PIC relocation
// base address.
switch (Opcode) {
default:
break;
case TargetInstrInfo::INLINEASM: {
const MachineFunction *MF = MI.getParent()->getParent();
const char *AsmStr = MI.getOperand(0).getSymbolName();
const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
FinalSize += AI->getInlineAsmLength(AsmStr);
break;
}
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
2008-07-01 08:05:16 +08:00
case TargetInstrInfo::DBG_LABEL:
case TargetInstrInfo::EH_LABEL:
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
break;
case TargetInstrInfo::IMPLICIT_DEF:
case TargetInstrInfo::DECLARE:
case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
case X86::MOVPC32r: {
// This emits the "call" portion of this pseudo instruction.
++FinalSize;
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
break;
}
Generate code for TLS instructions. llvm-svn: 58141
2008-10-25 23:22:06 +08:00
case X86::TLS_tp:
case X86::TLS_gs_ri:
FinalSize += 2;
FinalSize += sizeGlobalAddress(false);
break;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
}
CurOp = NumOps;
break;
case X86II::RawFrm:
++FinalSize;
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isMBB()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizePCRelativeBlockAddress();
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (MO.isGlobal()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeGlobalAddress(false);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (MO.isSymbol()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeExternalSymbolAddress(false);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (MO.isImm()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
} else {
assert(0 && "Unknown RawFrm operand!");
}
}
break;
case X86II::AddRegFrm:
++FinalSize;
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
++CurOp;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
unsigned Size = X86InstrInfo::sizeOfImm(Desc);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO1.isImm())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(Size);
else {
bool dword = false;
if (Opcode == X86::MOV64ri)
dword = true;
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO1.isGlobal()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeGlobalAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (MO1.isSymbol())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeExternalSymbolAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO1.isCPI())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstPoolAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO1.isJTI())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeJumpTableAddress(dword);
}
}
break;
case X86II::MRMDestReg: {
++FinalSize;
FinalSize += sizeRegModRMByte();
CurOp += 2;
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
if (CurOp != NumOps) {
++CurOp;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
}
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
break;
}
case X86II::MRMDestMem: {
++FinalSize;
FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
CurOp += 5;
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
if (CurOp != NumOps) {
++CurOp;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
}
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
break;
}
case X86II::MRMSrcReg:
++FinalSize;
FinalSize += sizeRegModRMByte();
CurOp += 2;
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
if (CurOp != NumOps) {
++CurOp;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
}
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
break;
case X86II::MRMSrcMem: {
++FinalSize;
FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
CurOp += 5;
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
if (CurOp != NumOps) {
++CurOp;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
}
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
break;
}
case X86II::MRM0r: case X86II::MRM1r:
case X86II::MRM2r: case X86II::MRM3r:
case X86II::MRM4r: case X86II::MRM5r:
case X86II::MRM6r: case X86II::MRM7r:
++FinalSize;
Don't forget to update the current operand when getting the size of an instruction. llvm-svn: 50007
2008-04-21 07:36:47 +08:00
++CurOp;
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeRegModRMByte();
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
unsigned Size = X86InstrInfo::sizeOfImm(Desc);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO1.isImm())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(Size);
else {
bool dword = false;
if (Opcode == X86::MOV64ri32)
dword = true;
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO1.isGlobal()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeGlobalAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (MO1.isSymbol())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeExternalSymbolAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO1.isCPI())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstPoolAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO1.isJTI())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeJumpTableAddress(dword);
}
}
break;
case X86II::MRM0m: case X86II::MRM1m:
case X86II::MRM2m: case X86II::MRM3m:
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m: {
++FinalSize;
FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
CurOp += 4;
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
unsigned Size = X86InstrInfo::sizeOfImm(Desc);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isImm())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstant(Size);
else {
bool dword = false;
if (Opcode == X86::MOV64mi32)
dword = true;
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isGlobal()) {
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeGlobalAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
} else if (MO.isSymbol())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeExternalSymbolAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isCPI())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeConstPoolAddress(dword);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (MO.isJTI())
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
FinalSize += sizeJumpTableAddress(dword);
}
}
break;
}
case X86II::MRMInitReg:
++FinalSize;
// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
FinalSize += sizeRegModRMByte();
++CurOp;
break;
}
if (!Desc->isVariadic() && CurOp != NumOps) {
cerr << "Cannot determine size: ";
MI.dump();
cerr << '\n';
abort();
}
return FinalSize;
}
unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
const TargetInstrDesc &Desc = MI->getDesc();
bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
Change target-specific classes to use more precise static types. This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
2008-05-14 09:58:56 +08:00
bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-04-17 04:10:13 +08:00
unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
if (Desc.getOpcode() == X86::MOVPC32r) {
Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
}
return Size;
}
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
/// getGlobalBaseReg - Return a virtual register initialized with the
/// the global base register value. Output instructions required to
/// initialize the register in the function entry block, if necessary.
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
///
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
"X86-64 PIC uses RIP relative addressing");
X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
if (GlobalBaseReg != 0)
return GlobalBaseReg;
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = MF->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
const TargetInstrInfo *TII = TM.getInstrInfo();
// Operand of MovePCtoStack is completely ignored by asm printer. It's
// only used in JIT code emission as displacement to pc.
BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0);
// If we're using vanilla 'GOT' PIC style, we should use relative addressing
// not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
if (TM.getRelocationModel() == Reloc::PIC_ &&
TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
GlobalBaseReg =
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
RegInfo.createVirtualRegister(X86::GR32RegisterClass);
BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg)
.addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
} else {
GlobalBaseReg = PC;
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
}
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
X86FI->setGlobalBaseReg(GlobalBaseReg);
return GlobalBaseReg;
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
}