2016-02-25 01:08:59 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512F
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;
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; Combine tests involving SSE3/SSSE3 target shuffles (MOVDDUP, MOVSHDUP, MOVSLDUP, PSHUFB)
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declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
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2016-08-10 22:15:41 +08:00
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define <16 x i8> @combine_vpshufb_as_zero(<16 x i8> %a0) {
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; SSE-LABEL: combine_vpshufb_as_zero:
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2016-04-24 21:45:30 +08:00
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; SSE: # BB#0:
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2016-04-24 22:53:54 +08:00
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; SSE-NEXT: xorps %xmm0, %xmm0
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2016-04-24 21:45:30 +08:00
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; SSE-NEXT: retq
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;
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2016-08-10 22:15:41 +08:00
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; AVX-LABEL: combine_vpshufb_as_zero:
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2016-04-24 21:45:30 +08:00
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; AVX: # BB#0:
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2016-04-24 22:53:54 +08:00
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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2016-04-24 21:45:30 +08:00
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; AVX-NEXT: retq
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%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>)
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%res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 128, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>)
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%res2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res1, <16 x i8> <i8 0, i8 1, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
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ret <16 x i8> %res2
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}
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2016-08-10 22:15:41 +08:00
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define <16 x i8> @combine_vpshufb_as_movq(<16 x i8> %a0) {
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; SSE-LABEL: combine_vpshufb_as_movq:
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2016-05-03 21:12:44 +08:00
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; SSE: # BB#0:
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2016-05-03 23:05:13 +08:00
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; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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2016-05-03 21:12:44 +08:00
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; SSE-NEXT: retq
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;
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2016-08-10 22:15:41 +08:00
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; AVX-LABEL: combine_vpshufb_as_movq:
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2016-05-03 21:12:44 +08:00
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; AVX: # BB#0:
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2016-05-03 23:05:13 +08:00
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; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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2016-05-03 21:12:44 +08:00
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; AVX-NEXT: retq
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%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 128, i8 1, i8 128, i8 2, i8 128, i8 3, i8 128, i8 4, i8 128, i8 5, i8 128, i8 6, i8 128, i8 7, i8 128>)
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%res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i8 12, i8 14, i8 1, i8 3, i8 5, i8 7, i8 9, i8 11, i8 13, i8 15>)
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ret <16 x i8> %res1
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}
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2016-08-10 22:15:41 +08:00
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define <2 x double> @combine_pshufb_as_movsd(<2 x double> %a0, <2 x double> %a1) {
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; SSSE3-LABEL: combine_pshufb_as_movsd:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSSE3-NEXT: movapd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_pshufb_as_movsd:
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; SSE41: # BB#0:
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2016-10-01 23:33:01 +08:00
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; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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2016-08-10 22:15:41 +08:00
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; SSE41-NEXT: retq
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;
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2016-10-01 23:33:01 +08:00
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; AVX1-LABEL: combine_pshufb_as_movsd:
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; AVX1: # BB#0:
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; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_pshufb_as_movsd:
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; AVX2: # BB#0:
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; AVX2-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: combine_pshufb_as_movsd:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; AVX512F-NEXT: retq
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2016-08-10 22:15:41 +08:00
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%1 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 3, i32 0>
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%2 = bitcast <2 x double> %1 to <16 x i8>
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%3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
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%4 = bitcast <16 x i8> %3 to <2 x double>
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ret <2 x double> %4
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}
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define <4 x float> @combine_pshufb_as_movss(<4 x float> %a0, <4 x float> %a1) {
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; SSSE3-LABEL: combine_pshufb_as_movss:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_pshufb_as_movss:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE41-NEXT: retq
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;
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2016-10-01 23:33:01 +08:00
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; AVX1-LABEL: combine_pshufb_as_movss:
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; AVX1: # BB#0:
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; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_pshufb_as_movss:
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; AVX2: # BB#0:
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; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: combine_pshufb_as_movss:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX512F-NEXT: retq
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2016-08-10 22:15:41 +08:00
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%1 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 3, i32 2, i32 1>
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%2 = bitcast <4 x float> %1 to <16 x i8>
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%3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 12, i8 13, i8 14, i8 15, i8 8, i8 9, i8 10, i8 11, i8 4, i8 5, i8 6, i8 7>)
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%4 = bitcast <16 x i8> %3 to <4 x float>
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ret <4 x float> %4
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}
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2016-08-20 01:02:00 +08:00
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define <2 x double> @combine_pshufb_as_vzmovl_64(<2 x double> %a0) {
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; SSE-LABEL: combine_pshufb_as_vzmovl_64:
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; SSE: # BB#0:
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; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufb_as_vzmovl_64:
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; AVX: # BB#0:
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; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; AVX-NEXT: retq
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%1 = bitcast <2 x double> %a0 to <16 x i8>
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%2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
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%3 = bitcast <16 x i8> %2 to <2 x double>
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ret <2 x double> %3
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}
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define <4 x float> @combine_pshufb_as_vzmovl_32(<4 x float> %a0) {
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; SSSE3-LABEL: combine_pshufb_as_vzmovl_32:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: xorps %xmm1, %xmm1
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; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_pshufb_as_vzmovl_32:
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; SSE41: # BB#0:
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; SSE41-NEXT: xorps %xmm1, %xmm1
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: combine_pshufb_as_vzmovl_32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_pshufb_as_vzmovl_32:
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; AVX2: # BB#0:
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; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: combine_pshufb_as_vzmovl_32:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX512F-NEXT: retq
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%1 = bitcast <4 x float> %a0 to <16 x i8>
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%2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
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%3 = bitcast <16 x i8> %2 to <4 x float>
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ret <4 x float> %3
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}
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2016-02-25 01:08:59 +08:00
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define <4 x float> @combine_pshufb_movddup(<4 x float> %a0) {
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; SSE-LABEL: combine_pshufb_movddup:
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; SSE: # BB#0:
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2016-02-25 17:12:12 +08:00
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; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,7,7,7,7,5,5,5,5,7,7,7,7]
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2016-02-25 01:08:59 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufb_movddup:
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; AVX: # BB#0:
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2016-02-25 17:12:12 +08:00
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,7,7,7,7,5,5,5,5,7,7,7,7]
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2016-02-25 01:08:59 +08:00
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; AVX-NEXT: retq
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%1 = bitcast <4 x float> %a0 to <16 x i8>
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%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 1, i8 1, i8 1, i8 1, i8 3, i8 3, i8 3, i8 3>)
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%3 = bitcast <16 x i8> %2 to <4 x float>
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%4 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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ret <4 x float> %4
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}
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define <4 x float> @combine_pshufb_movshdup(<4 x float> %a0) {
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; SSE-LABEL: combine_pshufb_movshdup:
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; SSE: # BB#0:
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2016-02-25 17:12:12 +08:00
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; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[7,7,7,7,7,7,7,7,3,3,3,3,3,3,3,3]
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2016-02-25 01:08:59 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufb_movshdup:
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; AVX: # BB#0:
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2016-02-25 17:12:12 +08:00
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[7,7,7,7,7,7,7,7,3,3,3,3,3,3,3,3]
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2016-02-25 01:08:59 +08:00
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; AVX-NEXT: retq
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%1 = bitcast <4 x float> %a0 to <16 x i8>
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%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 1, i8 1, i8 1, i8 1, i8 3, i8 3, i8 3, i8 3>)
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%3 = bitcast <16 x i8> %2 to <4 x float>
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%4 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
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ret <4 x float> %4
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}
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define <4 x float> @combine_pshufb_movsldup(<4 x float> %a0) {
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; SSE-LABEL: combine_pshufb_movsldup:
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; SSE: # BB#0:
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2016-02-25 17:12:12 +08:00
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|
|
; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1]
|
2016-02-25 01:08:59 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_movsldup:
|
|
|
|
|
; AVX: # BB#0:
|
2016-02-25 17:12:12 +08:00
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1]
|
2016-02-25 01:08:59 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = bitcast <4 x float> %a0 to <16 x i8>
|
|
|
|
|
%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 1, i8 1, i8 1, i8 1, i8 3, i8 3, i8 3, i8 3>)
|
|
|
|
|
%3 = bitcast <16 x i8> %2 to <4 x float>
|
|
|
|
|
%4 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
|
|
|
|
ret <4 x float> %4
|
|
|
|
|
}
|
2016-03-02 22:16:50 +08:00
|
|
|
|
2016-06-10 21:03:22 +08:00
|
|
|
define <16 x i8> @combine_pshufb_palignr(<16 x i8> %a0, <16 x i8> %a1) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_palignr:
|
|
|
|
|
; SSE: # BB#0:
|
2016-08-12 18:10:51 +08:00
|
|
|
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
|
2016-06-10 21:03:22 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_palignr:
|
|
|
|
|
; AVX: # BB#0:
|
2016-08-12 18:10:51 +08:00
|
|
|
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
|
2016-06-10 21:03:22 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
|
|
|
|
|
%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
|
|
|
|
|
ret <16 x i8> %2
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pshufb_pslldq(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_pslldq:
|
|
|
|
|
; SSE: # BB#0:
|
2016-06-11 21:38:28 +08:00
|
|
|
; SSE-NEXT: xorps %xmm0, %xmm0
|
2016-06-10 21:03:22 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_pslldq:
|
|
|
|
|
; AVX: # BB#0:
|
2016-06-11 21:38:28 +08:00
|
|
|
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
|
2016-06-10 21:03:22 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
|
|
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
|
ret <16 x i8> %2
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pshufb_psrldq(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_psrldq:
|
|
|
|
|
; SSE: # BB#0:
|
2016-06-11 21:38:28 +08:00
|
|
|
; SSE-NEXT: xorps %xmm0, %xmm0
|
2016-06-10 21:03:22 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_psrldq:
|
|
|
|
|
; AVX: # BB#0:
|
2016-06-11 21:38:28 +08:00
|
|
|
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
|
2016-06-10 21:03:22 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
|
|
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
|
|
|
|
|
ret <16 x i8> %2
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-16 18:03:23 +08:00
|
|
|
define <16 x i8> @combine_pshufb_as_palignr(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_palignr:
|
|
|
|
|
; SSE: # BB#0:
|
|
|
|
|
; SSE-NEXT: palignr {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0]
|
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_palignr:
|
|
|
|
|
; AVX: # BB#0:
|
|
|
|
|
; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0]
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 undef, i8 undef, i8 0>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-06 23:09:48 +08:00
|
|
|
define <16 x i8> @combine_pshufb_as_pslldq(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_pslldq:
|
|
|
|
|
; SSE: # BB#0:
|
2016-08-12 19:24:34 +08:00
|
|
|
; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
|
2016-07-06 23:09:48 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_pslldq:
|
|
|
|
|
; AVX: # BB#0:
|
2016-08-12 19:24:34 +08:00
|
|
|
; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
|
2016-07-06 23:09:48 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pshufb_as_psrldq(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_psrldq:
|
|
|
|
|
; SSE: # BB#0:
|
2016-08-12 19:24:34 +08:00
|
|
|
; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
2016-07-06 23:09:48 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_psrldq:
|
|
|
|
|
; AVX: # BB#0:
|
2016-08-12 19:24:34 +08:00
|
|
|
; AVX-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
2016-07-06 23:09:48 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-28 02:25:02 +08:00
|
|
|
define <16 x i8> @combine_pshufb_as_psrlw(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_psrlw:
|
|
|
|
|
; SSE: # BB#0:
|
2016-11-28 05:08:19 +08:00
|
|
|
; SSE-NEXT: psrlw $8, %xmm0
|
2016-11-28 02:25:02 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_psrlw:
|
|
|
|
|
; AVX: # BB#0:
|
2016-11-28 05:08:19 +08:00
|
|
|
; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0
|
2016-11-28 02:25:02 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 1, i8 128, i8 3, i8 128, i8 5, i8 128, i8 7, i8 128, i8 9, i8 128, i8 11, i8 128, i8 13, i8 128, i8 15, i8 128>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pshufb_as_pslld(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_pslld:
|
|
|
|
|
; SSE: # BB#0:
|
2016-11-28 05:08:19 +08:00
|
|
|
; SSE-NEXT: pslld $24, %xmm0
|
2016-11-28 02:25:02 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_pslld:
|
|
|
|
|
; AVX: # BB#0:
|
2016-11-28 05:08:19 +08:00
|
|
|
; AVX-NEXT: vpslld $24, %xmm0, %xmm0
|
2016-11-28 02:25:02 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 128, i8 128, i8 0, i8 128, i8 128, i8 128, i8 4, i8 128, i8 128, i8 128, i8 8, i8 128, i8 128, i8 128, i8 12>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pshufb_as_psrlq(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_psrlq:
|
|
|
|
|
; SSE: # BB#0:
|
2016-11-28 05:08:19 +08:00
|
|
|
; SSE-NEXT: psrlq $40, %xmm0
|
2016-11-28 02:25:02 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_psrlq:
|
|
|
|
|
; AVX: # BB#0:
|
2016-11-28 05:08:19 +08:00
|
|
|
; AVX-NEXT: vpsrlq $40, %xmm0, %xmm0
|
2016-11-28 02:25:02 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 5, i8 6, i8 7, i8 128, i8 128, i8 128, i8 128, i8 128, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-11 04:19:56 +08:00
|
|
|
define <16 x i8> @combine_pshufb_as_pshuflw(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_pshuflw:
|
|
|
|
|
; SSE: # BB#0:
|
2016-07-11 05:02:47 +08:00
|
|
|
; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
|
2016-07-11 04:19:56 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_pshuflw:
|
|
|
|
|
; AVX: # BB#0:
|
2016-07-11 05:02:47 +08:00
|
|
|
; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
|
2016-07-11 04:19:56 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 2, i8 3, i8 0, i8 1, i8 6, i8 7, i8 4, i8 5, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pshufb_as_pshufhw(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_pshufhw:
|
|
|
|
|
; SSE: # BB#0:
|
2016-07-11 05:02:47 +08:00
|
|
|
; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
|
2016-07-11 04:19:56 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_pshufhw:
|
|
|
|
|
; AVX: # BB#0:
|
2016-07-11 05:02:47 +08:00
|
|
|
; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
|
2016-07-11 04:19:56 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 10, i8 11, i8 8, i8 9, i8 14, i8 15, i8 12, i8 13>)
|
|
|
|
|
ret <16 x i8> %res0
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-11 05:02:47 +08:00
|
|
|
define <16 x i8> @combine_pshufb_not_as_pshufw(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_not_as_pshufw:
|
2016-07-11 04:19:56 +08:00
|
|
|
; SSE: # BB#0:
|
|
|
|
|
; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
|
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
2016-07-11 05:02:47 +08:00
|
|
|
; AVX-LABEL: combine_pshufb_not_as_pshufw:
|
2016-07-11 04:19:56 +08:00
|
|
|
; AVX: # BB#0:
|
|
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 2, i8 3, i8 0, i8 1, i8 6, i8 7, i8 4, i8 5, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
|
|
|
|
|
%res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 10, i8 11, i8 8, i8 9, i8 14, i8 15, i8 12, i8 13>)
|
|
|
|
|
ret <16 x i8> %res1
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-19 05:18:21 +08:00
|
|
|
define <16 x i8> @combine_pshufb_as_unary_unpcklbw(<16 x i8> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pshufb_as_unary_unpcklbw:
|
|
|
|
|
; SSE: # BB#0:
|
2016-06-20 02:03:52 +08:00
|
|
|
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
2016-06-19 05:18:21 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_unary_unpcklbw:
|
|
|
|
|
; AVX: # BB#0:
|
2016-06-20 02:03:52 +08:00
|
|
|
; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
2016-06-19 05:18:21 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 undef, i8 undef, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7>)
|
|
|
|
|
ret <16 x i8> %1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pshufb_as_unary_unpckhwd(<16 x i8> %a0) {
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|
|
|
|
; SSE-LABEL: combine_pshufb_as_unary_unpckhwd:
|
|
|
|
|
; SSE: # BB#0:
|
2016-06-20 02:03:52 +08:00
|
|
|
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
|
2016-06-19 05:18:21 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pshufb_as_unary_unpckhwd:
|
|
|
|
|
; AVX: # BB#0:
|
2016-06-20 02:03:52 +08:00
|
|
|
; AVX-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
|
2016-06-19 05:18:21 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 8, i8 9, i8 8, i8 9, i8 10, i8 11, i8 10, i8 11, i8 12, i8 13, i8 12, i8 13, i8 14, i8 15, i8 undef, i8 undef>)
|
|
|
|
|
ret <16 x i8> %1
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-28 23:50:39 +08:00
|
|
|
define <16 x i8> @combine_psrlw_pshufb(<8 x i16> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_psrlw_pshufb:
|
|
|
|
|
; SSE: # BB#0:
|
2016-11-29 00:25:01 +08:00
|
|
|
; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero
|
2016-11-28 23:50:39 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_psrlw_pshufb:
|
|
|
|
|
; AVX: # BB#0:
|
2016-11-29 00:25:01 +08:00
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero
|
2016-11-28 23:50:39 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = lshr <8 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
|
|
|
|
|
%2 = bitcast <8 x i16> %1 to <16 x i8>
|
|
|
|
|
%3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1>)
|
|
|
|
|
ret <16 x i8> %3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_pslld_pshufb(<4 x i32> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_pslld_pshufb:
|
|
|
|
|
; SSE: # BB#0:
|
2016-11-29 00:25:01 +08:00
|
|
|
; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,1,0],zero,xmm0[6,5,4],zero,xmm0[10,9,8],zero,xmm0[14,13,12],zero
|
2016-11-28 23:50:39 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_pslld_pshufb:
|
|
|
|
|
; AVX: # BB#0:
|
2016-11-29 00:25:01 +08:00
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,1,0],zero,xmm0[6,5,4],zero,xmm0[10,9,8],zero,xmm0[14,13,12],zero
|
2016-11-28 23:50:39 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = shl <4 x i32> %a0, <i32 8, i32 8, i32 8, i32 8>
|
|
|
|
|
%2 = bitcast <4 x i32> %1 to <16 x i8>
|
|
|
|
|
%3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>)
|
|
|
|
|
ret <16 x i8> %3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i8> @combine_psrlq_pshufb(<2 x i64> %a0) {
|
|
|
|
|
; SSE-LABEL: combine_psrlq_pshufb:
|
|
|
|
|
; SSE: # BB#0:
|
2016-11-29 00:25:01 +08:00
|
|
|
; SSE-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[7,6],zero,zero,zero,zero,zero,zero,xmm0[15,14]
|
2016-11-28 23:50:39 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_psrlq_pshufb:
|
|
|
|
|
; AVX: # BB#0:
|
2016-11-29 00:25:01 +08:00
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[7,6],zero,zero,zero,zero,zero,zero,xmm0[15,14]
|
2016-11-28 23:50:39 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = lshr <2 x i64> %a0, <i64 48, i64 48>
|
|
|
|
|
%2 = bitcast <2 x i64> %1 to <16 x i8>
|
|
|
|
|
%3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>)
|
|
|
|
|
ret <16 x i8> %3
|
|
|
|
|
}
|
|
|
|
|
|
2016-03-04 19:15:23 +08:00
|
|
|
define <16 x i8> @combine_unpckl_arg0_pshufb(<16 x i8> %a0, <16 x i8> %a1) {
|
|
|
|
|
; SSE-LABEL: combine_unpckl_arg0_pshufb:
|
2016-03-02 22:16:50 +08:00
|
|
|
; SSE: # BB#0:
|
|
|
|
|
; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
|
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
2016-03-04 19:15:23 +08:00
|
|
|
; AVX-LABEL: combine_unpckl_arg0_pshufb:
|
2016-03-02 22:16:50 +08:00
|
|
|
; AVX: # BB#0:
|
|
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
|
|
|
|
|
%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1>)
|
|
|
|
|
ret <16 x i8> %2
|
|
|
|
|
}
|
2016-03-04 19:15:23 +08:00
|
|
|
|
|
|
|
|
define <16 x i8> @combine_unpckl_arg1_pshufb(<16 x i8> %a0, <16 x i8> %a1) {
|
|
|
|
|
; SSE-LABEL: combine_unpckl_arg1_pshufb:
|
|
|
|
|
; SSE: # BB#0:
|
2016-03-10 19:23:51 +08:00
|
|
|
; SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
|
|
|
|
|
; SSE-NEXT: movdqa %xmm1, %xmm0
|
2016-03-04 19:15:23 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: combine_unpckl_arg1_pshufb:
|
|
|
|
|
; AVX: # BB#0:
|
2016-03-10 19:23:51 +08:00
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
|
2016-03-04 19:15:23 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
|
|
|
|
|
%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 1, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1>)
|
|
|
|
|
ret <16 x i8> %2
|
|
|
|
|
}
|
2016-09-18 01:40:08 +08:00
|
|
|
|
|
|
|
|
define <16 x i8> @constant_fold_pshufb() {
|
|
|
|
|
; SSE-LABEL: constant_fold_pshufb:
|
|
|
|
|
; SSE: # BB#0:
|
|
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
|
|
|
|
|
; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1],zero,zero,zero,xmm0[u,u],zero,zero,xmm0[15],zero,zero,zero,zero,zero,xmm0[7,6]
|
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: constant_fold_pshufb:
|
|
|
|
|
; AVX: # BB#0:
|
|
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
|
|
|
|
|
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1],zero,zero,zero,xmm0[u,u],zero,zero,xmm0[15],zero,zero,zero,zero,zero,xmm0[7,6]
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8> <i8 1, i8 -1, i8 -1, i8 -1, i8 undef, i8 undef, i8 -1, i8 -1, i8 15, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 7, i8 6>)
|
|
|
|
|
ret <16 x i8> %1
|
|
|
|
|
}
|
