forked from OSchip/llvm-project
56 lines
1.9 KiB
TableGen
56 lines
1.9 KiB
TableGen
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// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=MATCHER
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// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s --check-prefix=WRITER
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// Check that an instruction that uses mixed upper/lower case in its mnemonic
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// is printed as-is, and is parsed in its "canonicalized" lowercase form.
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
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// Define instructions that demonstrate case-insensitivity.
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// In case-sensitive ASCII order, "BInst" < "aInst".
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// In case-insensitive order, "aInst" < "BInst".
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// If the matcher really treats the mnemonics in a case-insensitive way,
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// then we should see "aInst" appearing before "BInst", despite the
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// fact that "BInst" would appear before "aInst" in ASCIIbetical order.
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def AlphabeticallySecondInst : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins);
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let AsmString = "BInst";
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}
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def AlphabeticallyFirstInst : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins);
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let AsmString = "aInst";
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}
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// Check that the matcher lower()s the mnemonics it matches.
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// MATCHER: static const char *const MnemonicTable =
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// MATCHER-NEXT: "\005ainst\005binst";
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// Check that aInst appears before BInst in the match table.
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// This shows that the mnemonics are sorted in a case-insensitive way,
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// since otherwise "B" would be less than "a" by ASCII order.
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// MATCHER: static const MatchEntry MatchTable0[] = {
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// MATCHER-NEXT: /* aInst */, ::AlphabeticallyFirstInst
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// MATCHER-NEXT: /* BInst */, ::AlphabeticallySecondInst
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// MATCHER-NEXT: };
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// Check that the writer preserves the case of the mnemonics.
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// WRITER: static const char AsmStrs[] = {
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// WRITER: "BInst\0"
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// WRITER-NEXT: "aInst\0"
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// WRITER-NEXT: };
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