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llvm-project/llvm/test/MC/Mips/mips-expansions-bad.s

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[mips] Implementation of dli. Patch by David Chisnall His work was sponsored by: DARPA, AFRL Some small modifications to the original patch: we now error if it's not possible to expand an instruction (mips-expansions-bad.s has some examples). Added some comments to the expansions. llvm-svn: 211271
2014-06-19 23:08:04 +08:00
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
[mips] [IAS] Fix error messages for using LI with 64-bit immediates. Summary: LI should never accept immediates larger than 32 bits. The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9289 llvm-svn: 236313
2015-05-01 20:19:27 +08:00
# RUN: FileCheck %s < %t1 --check-prefix=32-BIT
[mips] [IAS] Warn when LA is used with a 64-bit symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9295 llvm-svn: 237356
2015-05-14 18:53:40 +08:00
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N32-ONLY
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY
[mips] Implementation of dli. Patch by David Chisnall His work was sponsored by: DARPA, AFRL Some small modifications to the original patch: we now error if it's not possible to expand an instruction (mips-expansions-bad.s has some examples). Added some comments to the expansions. llvm-svn: 211271
2014-06-19 23:08:04 +08:00
[mips] [IAS] Make the mips-expansions-bad.s test more readable. NFC. Move the check lines below the code lines and change the indentation from 8 spaces to 2 spaces. llvm-svn: 234584
2015-04-10 18:46:59 +08:00
.text
dli $5, 1
[mips] [IAS] Fix error messages for using LI with 64-bit immediates. Summary: LI should never accept immediates larger than 32 bits. The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9289 llvm-svn: 236313
2015-05-01 20:19:27 +08:00
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
2015-06-11 18:36:10 +08:00
bne $2, 0x100010001, 1332
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
beq $2, 0x100010001, 1332
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
.set mips32r6
[mips][ias] Implement ulh macro. Summary: This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from failing after the integrated assembler is enabled by default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13654 llvm-svn: 250414
2015-10-15 22:52:58 +08:00
ulh $5, 0
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
ulhu $5, 0
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips32
[mips][ias] Implement ulh macro. Summary: This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from failing after the integrated assembler is enabled by default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13654 llvm-svn: 250414
2015-10-15 22:52:58 +08:00
ulh $5, 1
# 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
ulhu $5, 1
# 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips64r6
[mips][ias] Implement ulh macro. Summary: This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from failing after the integrated assembler is enabled by default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13654 llvm-svn: 250414
2015-10-15 22:52:58 +08:00
ulh $5, 2
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
ulhu $5, 2
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
[mips] [IAS] Add partial support for the ULW pseudo-instruction. Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
2015-06-26 21:20:17 +08:00
.set mips32r6
ulw $5, 0
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips32
ulw $5, 1
# 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips64r6
ulw $5, 2
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6