2012-02-17 16:55:11 +08:00
|
|
|
//===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
|
2011-12-20 10:50:00 +08:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2017-01-31 07:21:32 +08:00
|
|
|
#include "MCTargetDesc/MipsABIInfo.h"
|
2015-02-13 17:09:03 +08:00
|
|
|
#include "MipsMachineFunction.h"
|
2012-02-25 06:34:47 +08:00
|
|
|
#include "MipsSubtarget.h"
|
2015-01-30 07:27:36 +08:00
|
|
|
#include "MipsTargetMachine.h"
|
2017-01-31 07:21:32 +08:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2012-02-25 06:34:47 +08:00
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2017-01-31 07:21:32 +08:00
|
|
|
#include "llvm/CodeGen/PseudoSourceValue.h"
|
2012-02-25 06:34:47 +08:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2017-01-31 07:21:32 +08:00
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
2011-12-20 10:50:00 +08:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2012-02-25 06:34:47 +08:00
|
|
|
static cl::opt<bool>
|
|
|
|
FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
|
|
|
|
cl::desc("Always use $gp as the global base register."));
|
|
|
|
|
2017-01-31 07:21:32 +08:00
|
|
|
MipsFunctionInfo::~MipsFunctionInfo() = default;
|
2013-09-28 06:30:36 +08:00
|
|
|
|
2012-02-25 06:34:47 +08:00
|
|
|
bool MipsFunctionInfo::globalBaseRegSet() const {
|
|
|
|
return GlobalBaseReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MipsFunctionInfo::getGlobalBaseReg() {
|
|
|
|
// Return if it has already been initialized.
|
|
|
|
if (GlobalBaseReg)
|
|
|
|
return GlobalBaseReg;
|
|
|
|
|
2015-02-27 23:03:50 +08:00
|
|
|
MipsSubtarget const &STI =
|
|
|
|
static_cast<const MipsSubtarget &>(MF.getSubtarget());
|
|
|
|
|
2014-11-21 13:58:21 +08:00
|
|
|
const TargetRegisterClass *RC =
|
2015-02-27 23:03:50 +08:00
|
|
|
STI.inMips16Mode()
|
2015-01-30 07:27:36 +08:00
|
|
|
? &Mips::CPU16RegsRegClass
|
2017-04-26 19:40:12 +08:00
|
|
|
: static_cast<const MipsTargetMachine &>(MF.getTarget())
|
2015-02-27 23:03:50 +08:00
|
|
|
.getABI()
|
|
|
|
.IsN64()
|
|
|
|
? &Mips::GPR64RegClass
|
|
|
|
: &Mips::GPR32RegClass;
|
2012-02-25 06:34:47 +08:00
|
|
|
return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
|
|
}
|
|
|
|
|
2013-01-30 08:26:49 +08:00
|
|
|
void MipsFunctionInfo::createEhDataRegsFI() {
|
2017-04-25 02:55:33 +08:00
|
|
|
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
2013-01-30 08:26:49 +08:00
|
|
|
for (int I = 0; I < 4; ++I) {
|
2017-04-25 02:55:33 +08:00
|
|
|
const TargetRegisterClass &RC =
|
2015-01-30 07:27:36 +08:00
|
|
|
static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
|
2017-04-25 02:55:33 +08:00
|
|
|
? Mips::GPR64RegClass
|
|
|
|
: Mips::GPR32RegClass;
|
2013-01-30 08:26:49 +08:00
|
|
|
|
2017-04-25 02:55:33 +08:00
|
|
|
EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
|
|
|
|
TRI.getSpillAlignment(RC), false);
|
2013-01-30 08:26:49 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
void MipsFunctionInfo::createISRRegFI() {
|
|
|
|
// ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
|
|
|
|
// The current implementation only supports Mips32r2+ not Mips64rX. Status
|
2016-11-18 19:53:36 +08:00
|
|
|
// is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
|
2015-10-26 20:38:43 +08:00
|
|
|
// however Mips32r2+ is the supported architecture.
|
2017-04-25 02:55:33 +08:00
|
|
|
const TargetRegisterClass &RC = Mips::GPR32RegClass;
|
|
|
|
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
2015-10-26 20:38:43 +08:00
|
|
|
|
|
|
|
for (int I = 0; I < 2; ++I)
|
2016-07-29 02:40:00 +08:00
|
|
|
ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
|
2017-04-25 02:55:33 +08:00
|
|
|
TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
|
2015-10-26 20:38:43 +08:00
|
|
|
}
|
|
|
|
|
2013-01-30 08:26:49 +08:00
|
|
|
bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
|
|
|
|
return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
|
|
|
|
|| FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
|
|
|
|
}
|
|
|
|
|
2015-10-26 20:38:43 +08:00
|
|
|
bool MipsFunctionInfo::isISRRegFI(int FI) const {
|
|
|
|
return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
|
|
|
|
}
|
2015-08-12 07:23:17 +08:00
|
|
|
MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) {
|
|
|
|
return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES));
|
2013-09-28 06:30:36 +08:00
|
|
|
}
|
|
|
|
|
2015-08-12 07:23:17 +08:00
|
|
|
MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) {
|
|
|
|
return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV));
|
2013-09-28 06:30:36 +08:00
|
|
|
}
|
|
|
|
|
2014-07-14 21:08:14 +08:00
|
|
|
int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
|
2017-04-25 02:55:33 +08:00
|
|
|
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
2014-07-14 21:08:14 +08:00
|
|
|
if (MoveF64ViaSpillFI == -1) {
|
2016-07-29 02:40:00 +08:00
|
|
|
MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
|
2017-04-25 02:55:33 +08:00
|
|
|
TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
|
2014-07-14 17:40:29 +08:00
|
|
|
}
|
2014-07-14 21:08:14 +08:00
|
|
|
return MoveF64ViaSpillFI;
|
2014-07-14 17:40:29 +08:00
|
|
|
}
|
|
|
|
|
2017-01-31 07:21:32 +08:00
|
|
|
void MipsFunctionInfo::anchor() {}
|