maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/avx512-i1test.ll

59 lines
2.0 KiB
LLVM
Raw Normal View History

autogenerate checks llvm-svn: 278624
2016-08-14 17:34:39 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
AVX-512: Fixed a bug in lowering setcc for MVT::i1 type llvm-svn: 224008
2014-12-11 18:21:12 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define void @func() {
autogenerate checks llvm-svn: 278624
2016-08-14 17:34:39 +08:00
; CHECK-LABEL: func:
; CHECK: ## BB#0: ## %L_10
[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence. Differential Revision: http://reviews.llvm.org/D23490 llvm-svn: 279960
2016-08-29 16:52:52 +08:00
; CHECK-NEXT: kortestw %k0, %k0
autogenerate checks llvm-svn: 278624
2016-08-14 17:34:39 +08:00
; CHECK-NEXT: je LBB0_1
[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence. Differential Revision: http://reviews.llvm.org/D23490 llvm-svn: 279960
2016-08-29 16:52:52 +08:00
; CHECK-NEXT: ## BB#3: ## %L_30
autogenerate checks llvm-svn: 278624
2016-08-14 17:34:39 +08:00
; CHECK-NEXT: retq
; CHECK-NEXT: .p2align 4, 0x90
[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence. Differential Revision: http://reviews.llvm.org/D23490 llvm-svn: 279960
2016-08-29 16:52:52 +08:00
; CHECK-NEXT: LBB0_2: ## %bb35
; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: kortestw %k0, %k0
; CHECK-NEXT: LBB0_1: ## %bb33
autogenerate checks llvm-svn: 278624
2016-08-14 17:34:39 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence. Differential Revision: http://reviews.llvm.org/D23490 llvm-svn: 279960
2016-08-29 16:52:52 +08:00
; CHECK-NEXT: kortestw %k0, %k0
; CHECK-NEXT: jne LBB0_1
; CHECK-NEXT: jmp LBB0_2
AVX-512: Fixed a bug in lowering setcc for MVT::i1 type llvm-svn: 224008
2014-12-11 18:21:12 +08:00
bb1:
br i1 undef, label %L_10, label %L_10
L_10: ; preds = %bb1, %bb1
br i1 undef, label %L_30, label %bb56
bb56: ; preds = %L_10
br label %bb33
bb33: ; preds = %bb51, %bb56
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%r111 = load i64, i64* undef, align 8
AVX-512: Fixed a bug in lowering setcc for MVT::i1 type llvm-svn: 224008
2014-12-11 18:21:12 +08:00
br i1 undef, label %bb51, label %bb35
bb35: ; preds = %bb33
br i1 undef, label %L_19, label %bb37
bb37: ; preds = %bb35
%r128 = and i64 %r111, 576460752303423488
%phitmp = icmp eq i64 %r128, 0
br label %L_19
L_19: ; preds = %bb37, %bb35
%"$V_S25.0" = phi i1 [ %phitmp, %bb37 ], [ true, %bb35 ]
br i1 undef, label %bb51, label %bb42
bb42: ; preds = %L_19
%r136 = select i1 %"$V_S25.0", i32* undef, i32* undef
br label %bb51
bb51: ; preds = %bb42, %L_19, %bb33
br i1 false, label %L_30, label %bb33
L_30: ; preds = %bb51, %L_10
ret void
}