2017-07-22 05:37:46 +08:00
|
|
|
//===- DemandedBits.cpp - Determine demanded bits -------------------------===//
|
2015-08-14 19:09:09 +08:00
|
|
|
//
|
2019-01-19 16:50:56 +08:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2015-08-14 19:09:09 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This pass implements a demanded bits analysis. A demanded bit is one that
|
|
|
|
// contributes to a result; bits that are not demanded can be either zero or
|
|
|
|
// one without affecting control or data flow. For example in this sequence:
|
|
|
|
//
|
|
|
|
// %1 = add i32 %x, %y
|
|
|
|
// %2 = trunc i32 %1 to i16
|
|
|
|
//
|
|
|
|
// Only the lowest 16 bits of %1 are demanded; the rest are removed by the
|
|
|
|
// trunc.
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|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
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|
|
|
|
|
#include "llvm/Analysis/DemandedBits.h"
|
2017-07-22 05:37:46 +08:00
|
|
|
#include "llvm/ADT/APInt.h"
|
2019-01-12 17:09:15 +08:00
|
|
|
#include "llvm/ADT/SetVector.h"
|
2015-10-08 20:39:59 +08:00
|
|
|
#include "llvm/ADT/StringExtras.h"
|
2016-12-19 16:22:17 +08:00
|
|
|
#include "llvm/Analysis/AssumptionCache.h"
|
2015-08-14 19:09:09 +08:00
|
|
|
#include "llvm/Analysis/ValueTracking.h"
|
|
|
|
#include "llvm/IR/BasicBlock.h"
|
2017-07-22 05:37:46 +08:00
|
|
|
#include "llvm/IR/Constants.h"
|
2015-08-14 19:09:09 +08:00
|
|
|
#include "llvm/IR/DataLayout.h"
|
2017-07-22 05:37:46 +08:00
|
|
|
#include "llvm/IR/DerivedTypes.h"
|
2015-08-14 19:09:09 +08:00
|
|
|
#include "llvm/IR/Dominators.h"
|
|
|
|
#include "llvm/IR/InstIterator.h"
|
2017-07-22 05:37:46 +08:00
|
|
|
#include "llvm/IR/InstrTypes.h"
|
|
|
|
#include "llvm/IR/Instruction.h"
|
2015-08-14 19:09:09 +08:00
|
|
|
#include "llvm/IR/IntrinsicInst.h"
|
2017-07-22 05:37:46 +08:00
|
|
|
#include "llvm/IR/Intrinsics.h"
|
2015-08-14 19:09:09 +08:00
|
|
|
#include "llvm/IR/Module.h"
|
|
|
|
#include "llvm/IR/Operator.h"
|
2017-07-22 05:37:46 +08:00
|
|
|
#include "llvm/IR/PassManager.h"
|
2018-12-07 23:38:13 +08:00
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|
|
#include "llvm/IR/PatternMatch.h"
|
2017-07-22 05:37:46 +08:00
|
|
|
#include "llvm/IR/Type.h"
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|
|
|
#include "llvm/IR/Use.h"
|
Sink all InitializePasses.h includes
This file lists every pass in LLVM, and is included by Pass.h, which is
very popular. Every time we add, remove, or rename a pass in LLVM, it
caused lots of recompilation.
I found this fact by looking at this table, which is sorted by the
number of times a file was changed over the last 100,000 git commits
multiplied by the number of object files that depend on it in the
current checkout:
recompiles touches affected_files header
342380 95 3604 llvm/include/llvm/ADT/STLExtras.h
314730 234 1345 llvm/include/llvm/InitializePasses.h
307036 118 2602 llvm/include/llvm/ADT/APInt.h
213049 59 3611 llvm/include/llvm/Support/MathExtras.h
170422 47 3626 llvm/include/llvm/Support/Compiler.h
162225 45 3605 llvm/include/llvm/ADT/Optional.h
158319 63 2513 llvm/include/llvm/ADT/Triple.h
140322 39 3598 llvm/include/llvm/ADT/StringRef.h
137647 59 2333 llvm/include/llvm/Support/Error.h
131619 73 1803 llvm/include/llvm/Support/FileSystem.h
Before this change, touching InitializePasses.h would cause 1345 files
to recompile. After this change, touching it only causes 550 compiles in
an incremental rebuild.
Reviewers: bkramer, asbirlea, bollu, jdoerfert
Differential Revision: https://reviews.llvm.org/D70211
2019-11-14 05:15:01 +08:00
|
|
|
#include "llvm/InitializePasses.h"
|
2015-08-14 19:09:09 +08:00
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#include "llvm/Pass.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/Support/Casting.h"
|
2015-08-14 19:09:09 +08:00
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#include "llvm/Support/Debug.h"
|
2017-04-27 00:39:58 +08:00
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|
#include "llvm/Support/KnownBits.h"
|
2015-08-14 19:09:09 +08:00
|
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|
#include "llvm/Support/raw_ostream.h"
|
2017-07-22 05:37:46 +08:00
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|
|
#include <algorithm>
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#include <cstdint>
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|
2015-08-14 19:09:09 +08:00
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using namespace llvm;
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2018-12-07 23:38:13 +08:00
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using namespace llvm::PatternMatch;
|
2015-08-14 19:09:09 +08:00
|
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|
|
#define DEBUG_TYPE "demanded-bits"
|
|
|
|
|
2016-04-19 07:55:01 +08:00
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|
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char DemandedBitsWrapperPass::ID = 0;
|
2017-07-22 05:37:46 +08:00
|
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|
|
2016-04-19 07:55:01 +08:00
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INITIALIZE_PASS_BEGIN(DemandedBitsWrapperPass, "demanded-bits",
|
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|
|
"Demanded bits analysis", false, false)
|
2016-12-19 16:22:17 +08:00
|
|
|
INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
|
2015-08-14 19:09:09 +08:00
|
|
|
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
|
2016-04-19 07:55:01 +08:00
|
|
|
INITIALIZE_PASS_END(DemandedBitsWrapperPass, "demanded-bits",
|
|
|
|
"Demanded bits analysis", false, false)
|
2015-08-14 19:09:09 +08:00
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
DemandedBitsWrapperPass::DemandedBitsWrapperPass() : FunctionPass(ID) {
|
|
|
|
initializeDemandedBitsWrapperPassPass(*PassRegistry::getPassRegistry());
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
void DemandedBitsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
|
2015-08-14 19:09:09 +08:00
|
|
|
AU.setPreservesCFG();
|
2016-12-19 16:22:17 +08:00
|
|
|
AU.addRequired<AssumptionCacheTracker>();
|
2015-08-14 19:09:09 +08:00
|
|
|
AU.addRequired<DominatorTreeWrapperPass>();
|
|
|
|
AU.setPreservesAll();
|
|
|
|
}
|
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
void DemandedBitsWrapperPass::print(raw_ostream &OS, const Module *M) const {
|
|
|
|
DB->print(OS);
|
|
|
|
}
|
|
|
|
|
2015-08-14 19:09:09 +08:00
|
|
|
static bool isAlwaysLive(Instruction *I) {
|
2018-08-26 17:51:22 +08:00
|
|
|
return I->isTerminator() || isa<DbgInfoIntrinsic>(I) || I->isEHPad() ||
|
|
|
|
I->mayHaveSideEffects();
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
|
2015-09-22 19:15:07 +08:00
|
|
|
void DemandedBits::determineLiveOperandBits(
|
2019-01-05 05:21:43 +08:00
|
|
|
const Instruction *UserI, const Value *Val, unsigned OperandNo,
|
|
|
|
const APInt &AOut, APInt &AB, KnownBits &Known, KnownBits &Known2,
|
|
|
|
bool &KnownBitsComputed) {
|
2015-08-14 19:09:09 +08:00
|
|
|
unsigned BitWidth = AB.getBitWidth();
|
|
|
|
|
|
|
|
// We're called once per operand, but for some instructions, we need to
|
|
|
|
// compute known bits of both operands in order to determine the live bits of
|
|
|
|
// either (when both operands are instructions themselves). We don't,
|
|
|
|
// however, want to do this twice, so we cache the result in APInts that live
|
|
|
|
// in the caller. For the two-relevant-operands case, both operand values are
|
|
|
|
// provided here.
|
|
|
|
auto ComputeKnownBits =
|
|
|
|
[&](unsigned BitWidth, const Value *V1, const Value *V2) {
|
2019-01-05 05:21:43 +08:00
|
|
|
if (KnownBitsComputed)
|
|
|
|
return;
|
|
|
|
KnownBitsComputed = true;
|
|
|
|
|
|
|
|
const DataLayout &DL = UserI->getModule()->getDataLayout();
|
2017-04-27 00:39:58 +08:00
|
|
|
Known = KnownBits(BitWidth);
|
2017-05-14 01:22:16 +08:00
|
|
|
computeKnownBits(V1, Known, DL, 0, &AC, UserI, &DT);
|
2015-08-14 19:09:09 +08:00
|
|
|
|
|
|
|
if (V2) {
|
2017-04-27 00:39:58 +08:00
|
|
|
Known2 = KnownBits(BitWidth);
|
2017-05-14 01:22:16 +08:00
|
|
|
computeKnownBits(V2, Known2, DL, 0, &AC, UserI, &DT);
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
switch (UserI->getOpcode()) {
|
|
|
|
default: break;
|
|
|
|
case Instruction::Call:
|
|
|
|
case Instruction::Invoke:
|
2020-09-11 04:11:04 +08:00
|
|
|
if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(UserI)) {
|
2015-08-14 19:09:09 +08:00
|
|
|
switch (II->getIntrinsicID()) {
|
|
|
|
default: break;
|
|
|
|
case Intrinsic::bswap:
|
|
|
|
// The alive bits of the input are the swapped alive bits of
|
|
|
|
// the output.
|
|
|
|
AB = AOut.byteSwap();
|
|
|
|
break;
|
2017-04-14 00:44:25 +08:00
|
|
|
case Intrinsic::bitreverse:
|
2017-06-20 04:10:41 +08:00
|
|
|
// The alive bits of the input are the reversed alive bits of
|
|
|
|
// the output.
|
2017-04-14 00:44:25 +08:00
|
|
|
AB = AOut.reverseBits();
|
|
|
|
break;
|
2015-08-14 19:09:09 +08:00
|
|
|
case Intrinsic::ctlz:
|
|
|
|
if (OperandNo == 0) {
|
|
|
|
// We need some output bits, so we need all bits of the
|
|
|
|
// input to the left of, and including, the leftmost bit
|
|
|
|
// known to be one.
|
2019-01-05 05:21:43 +08:00
|
|
|
ComputeKnownBits(BitWidth, Val, nullptr);
|
2015-08-14 19:09:09 +08:00
|
|
|
AB = APInt::getHighBitsSet(BitWidth,
|
2017-05-13 01:20:30 +08:00
|
|
|
std::min(BitWidth, Known.countMaxLeadingZeros()+1));
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Intrinsic::cttz:
|
|
|
|
if (OperandNo == 0) {
|
|
|
|
// We need some output bits, so we need all bits of the
|
|
|
|
// input to the right of, and including, the rightmost bit
|
|
|
|
// known to be one.
|
2019-01-05 05:21:43 +08:00
|
|
|
ComputeKnownBits(BitWidth, Val, nullptr);
|
2015-08-14 19:09:09 +08:00
|
|
|
AB = APInt::getLowBitsSet(BitWidth,
|
2017-05-13 01:20:30 +08:00
|
|
|
std::min(BitWidth, Known.countMaxTrailingZeros()+1));
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
break;
|
2018-11-26 23:36:57 +08:00
|
|
|
case Intrinsic::fshl:
|
2018-12-07 23:38:13 +08:00
|
|
|
case Intrinsic::fshr: {
|
|
|
|
const APInt *SA;
|
2018-11-26 23:36:57 +08:00
|
|
|
if (OperandNo == 2) {
|
|
|
|
// Shift amount is modulo the bitwidth. For powers of two we have
|
|
|
|
// SA % BW == SA & (BW - 1).
|
|
|
|
if (isPowerOf2_32(BitWidth))
|
|
|
|
AB = BitWidth - 1;
|
2018-12-07 23:38:13 +08:00
|
|
|
} else if (match(II->getOperand(2), m_APInt(SA))) {
|
2018-11-26 23:36:57 +08:00
|
|
|
// Normalize to funnel shift left. APInt shifts of BitWidth are well-
|
|
|
|
// defined, so no need to special-case zero shifts here.
|
2018-12-07 23:38:13 +08:00
|
|
|
uint64_t ShiftAmt = SA->urem(BitWidth);
|
2018-11-26 23:36:57 +08:00
|
|
|
if (II->getIntrinsicID() == Intrinsic::fshr)
|
|
|
|
ShiftAmt = BitWidth - ShiftAmt;
|
|
|
|
|
|
|
|
if (OperandNo == 0)
|
|
|
|
AB = AOut.lshr(ShiftAmt);
|
|
|
|
else if (OperandNo == 1)
|
|
|
|
AB = AOut.shl(BitWidth - ShiftAmt);
|
|
|
|
}
|
|
|
|
break;
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
2018-12-07 23:38:13 +08:00
|
|
|
}
|
2020-09-11 04:11:04 +08:00
|
|
|
}
|
2015-08-14 19:09:09 +08:00
|
|
|
break;
|
|
|
|
case Instruction::Add:
|
2020-08-17 19:53:52 +08:00
|
|
|
if (AOut.isMask()) {
|
|
|
|
AB = AOut;
|
|
|
|
} else {
|
|
|
|
ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
|
|
|
|
AB = determineLiveOperandBitsAdd(OperandNo, AOut, Known, Known2);
|
|
|
|
}
|
|
|
|
break;
|
2015-08-14 19:09:09 +08:00
|
|
|
case Instruction::Sub:
|
2020-08-17 19:53:52 +08:00
|
|
|
if (AOut.isMask()) {
|
|
|
|
AB = AOut;
|
|
|
|
} else {
|
|
|
|
ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
|
|
|
|
AB = determineLiveOperandBitsSub(OperandNo, AOut, Known, Known2);
|
|
|
|
}
|
|
|
|
break;
|
2015-10-08 20:39:59 +08:00
|
|
|
case Instruction::Mul:
|
2015-08-14 19:09:09 +08:00
|
|
|
// Find the highest live output bit. We don't need any more input
|
|
|
|
// bits than that (adds, and thus subtracts, ripple only to the
|
|
|
|
// left).
|
|
|
|
AB = APInt::getLowBitsSet(BitWidth, AOut.getActiveBits());
|
|
|
|
break;
|
|
|
|
case Instruction::Shl:
|
2018-12-07 23:38:13 +08:00
|
|
|
if (OperandNo == 0) {
|
|
|
|
const APInt *ShiftAmtC;
|
|
|
|
if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
|
2017-07-07 22:39:26 +08:00
|
|
|
uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
|
2015-08-14 19:09:09 +08:00
|
|
|
AB = AOut.lshr(ShiftAmt);
|
|
|
|
|
|
|
|
// If the shift is nuw/nsw, then the high bits are not dead
|
|
|
|
// (because we've promised that they *must* be zero).
|
|
|
|
const ShlOperator *S = cast<ShlOperator>(UserI);
|
|
|
|
if (S->hasNoSignedWrap())
|
|
|
|
AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
|
|
|
|
else if (S->hasNoUnsignedWrap())
|
|
|
|
AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
|
|
|
|
}
|
2018-12-07 23:38:13 +08:00
|
|
|
}
|
2015-08-14 19:09:09 +08:00
|
|
|
break;
|
|
|
|
case Instruction::LShr:
|
2018-12-07 23:38:13 +08:00
|
|
|
if (OperandNo == 0) {
|
|
|
|
const APInt *ShiftAmtC;
|
|
|
|
if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
|
2017-07-07 22:39:26 +08:00
|
|
|
uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
|
2015-08-14 19:09:09 +08:00
|
|
|
AB = AOut.shl(ShiftAmt);
|
|
|
|
|
|
|
|
// If the shift is exact, then the low bits are not dead
|
|
|
|
// (they must be zero).
|
|
|
|
if (cast<LShrOperator>(UserI)->isExact())
|
|
|
|
AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
|
|
|
|
}
|
2018-12-07 23:38:13 +08:00
|
|
|
}
|
2015-08-14 19:09:09 +08:00
|
|
|
break;
|
|
|
|
case Instruction::AShr:
|
2018-12-07 23:38:13 +08:00
|
|
|
if (OperandNo == 0) {
|
|
|
|
const APInt *ShiftAmtC;
|
|
|
|
if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
|
2017-07-07 22:39:26 +08:00
|
|
|
uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
|
2015-08-14 19:09:09 +08:00
|
|
|
AB = AOut.shl(ShiftAmt);
|
|
|
|
// Because the high input bit is replicated into the
|
|
|
|
// high-order bits of the result, if we need any of those
|
|
|
|
// bits, then we must keep the highest input bit.
|
|
|
|
if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
|
|
|
|
.getBoolValue())
|
2017-04-29 00:58:05 +08:00
|
|
|
AB.setSignBit();
|
2015-08-14 19:09:09 +08:00
|
|
|
|
|
|
|
// If the shift is exact, then the low bits are not dead
|
|
|
|
// (they must be zero).
|
|
|
|
if (cast<AShrOperator>(UserI)->isExact())
|
|
|
|
AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
|
|
|
|
}
|
2018-12-07 23:38:13 +08:00
|
|
|
}
|
2015-08-14 19:09:09 +08:00
|
|
|
break;
|
|
|
|
case Instruction::And:
|
|
|
|
AB = AOut;
|
|
|
|
|
|
|
|
// For bits that are known zero, the corresponding bits in the
|
|
|
|
// other operand are dead (unless they're both zero, in which
|
|
|
|
// case they can't both be dead, so just mark the LHS bits as
|
|
|
|
// dead).
|
2019-01-05 05:21:43 +08:00
|
|
|
ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
|
|
|
|
if (OperandNo == 0)
|
2017-04-27 00:39:58 +08:00
|
|
|
AB &= ~Known2.Zero;
|
2019-01-05 05:21:43 +08:00
|
|
|
else
|
2017-04-27 00:39:58 +08:00
|
|
|
AB &= ~(Known.Zero & ~Known2.Zero);
|
2015-08-14 19:09:09 +08:00
|
|
|
break;
|
|
|
|
case Instruction::Or:
|
|
|
|
AB = AOut;
|
|
|
|
|
|
|
|
// For bits that are known one, the corresponding bits in the
|
|
|
|
// other operand are dead (unless they're both one, in which
|
|
|
|
// case they can't both be dead, so just mark the LHS bits as
|
|
|
|
// dead).
|
2019-01-05 05:21:43 +08:00
|
|
|
ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
|
|
|
|
if (OperandNo == 0)
|
2017-04-27 00:39:58 +08:00
|
|
|
AB &= ~Known2.One;
|
2019-01-05 05:21:43 +08:00
|
|
|
else
|
2017-04-27 00:39:58 +08:00
|
|
|
AB &= ~(Known.One & ~Known2.One);
|
2015-08-14 19:09:09 +08:00
|
|
|
break;
|
|
|
|
case Instruction::Xor:
|
|
|
|
case Instruction::PHI:
|
|
|
|
AB = AOut;
|
|
|
|
break;
|
|
|
|
case Instruction::Trunc:
|
|
|
|
AB = AOut.zext(BitWidth);
|
|
|
|
break;
|
|
|
|
case Instruction::ZExt:
|
|
|
|
AB = AOut.trunc(BitWidth);
|
|
|
|
break;
|
|
|
|
case Instruction::SExt:
|
|
|
|
AB = AOut.trunc(BitWidth);
|
|
|
|
// Because the high input bit is replicated into the
|
|
|
|
// high-order bits of the result, if we need any of those
|
|
|
|
// bits, then we must keep the highest input bit.
|
|
|
|
if ((AOut & APInt::getHighBitsSet(AOut.getBitWidth(),
|
|
|
|
AOut.getBitWidth() - BitWidth))
|
|
|
|
.getBoolValue())
|
2017-04-29 00:58:05 +08:00
|
|
|
AB.setSignBit();
|
2015-08-14 19:09:09 +08:00
|
|
|
break;
|
|
|
|
case Instruction::Select:
|
|
|
|
if (OperandNo != 0)
|
|
|
|
AB = AOut;
|
|
|
|
break;
|
2018-12-07 23:38:13 +08:00
|
|
|
case Instruction::ExtractElement:
|
|
|
|
if (OperandNo == 0)
|
|
|
|
AB = AOut;
|
|
|
|
break;
|
|
|
|
case Instruction::InsertElement:
|
|
|
|
case Instruction::ShuffleVector:
|
|
|
|
if (OperandNo == 0 || OperandNo == 1)
|
|
|
|
AB = AOut;
|
|
|
|
break;
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
bool DemandedBitsWrapperPass::runOnFunction(Function &F) {
|
2016-12-19 16:22:17 +08:00
|
|
|
auto &AC = getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
|
2016-04-19 07:55:01 +08:00
|
|
|
auto &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
|
2016-12-19 16:22:17 +08:00
|
|
|
DB.emplace(F, AC, DT);
|
2015-10-08 20:39:50 +08:00
|
|
|
return false;
|
|
|
|
}
|
2015-08-14 19:09:09 +08:00
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
void DemandedBitsWrapperPass::releaseMemory() {
|
|
|
|
DB.reset();
|
|
|
|
}
|
|
|
|
|
2015-10-08 20:39:50 +08:00
|
|
|
void DemandedBits::performAnalysis() {
|
|
|
|
if (Analyzed)
|
|
|
|
// Analysis already completed for this function.
|
|
|
|
return;
|
|
|
|
Analyzed = true;
|
2018-07-31 03:41:25 +08:00
|
|
|
|
2015-08-14 19:09:09 +08:00
|
|
|
Visited.clear();
|
|
|
|
AliveBits.clear();
|
Reapply "[BDCE][DemandedBits] Detect dead uses of undead instructions"
This (mostly) fixes https://bugs.llvm.org/show_bug.cgi?id=39771.
BDCE currently detects instructions that don't have any demanded bits
and replaces their uses with zero. However, if an instruction has
multiple uses, then some of the uses may be dead (have no demanded bits)
even though the instruction itself is still live. This patch extends
DemandedBits/BDCE to detect such uses and replace them with zero.
While this will not immediately render any instructions dead, it may
lead to simplifications (in the motivating case, by converting a rotate
into a simple shift), break dependencies, etc.
The implementation tries to strike a balance between analysis power and
complexity/memory usage. Originally I wanted to track demanded bits on
a per-use level, but ultimately we're only really interested in whether
a use is entirely dead or not. I'm using an extra set to track which uses
are dead. However, as initially all uses are dead, I'm not storing uses
those user is also dead. This case is checked separately instead.
The previous attempt to land this lead to miscompiles, because cases
where uses were initially dead but were later found to be live during
further analysis were not always correctly removed from the DeadUses
set. This is fixed now and the added test case demanstrates such an
instance.
Differential Revision: https://reviews.llvm.org/D55563
llvm-svn: 350188
2019-01-01 18:05:26 +08:00
|
|
|
DeadUses.clear();
|
2015-08-14 19:09:09 +08:00
|
|
|
|
2019-01-12 17:09:15 +08:00
|
|
|
SmallSetVector<Instruction*, 16> Worklist;
|
2015-08-14 19:09:09 +08:00
|
|
|
|
|
|
|
// Collect the set of "root" instructions that are known live.
|
2016-04-19 07:55:01 +08:00
|
|
|
for (Instruction &I : instructions(F)) {
|
2015-08-14 19:09:09 +08:00
|
|
|
if (!isAlwaysLive(&I))
|
|
|
|
continue;
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "DemandedBits: Root: " << I << "\n");
|
2015-08-14 19:09:09 +08:00
|
|
|
// For integer-valued instructions, set up an initial empty set of alive
|
|
|
|
// bits and add the instruction to the work list. For other instructions
|
|
|
|
// add their operands to the work list (for integer values operands, mark
|
|
|
|
// all bits as live).
|
2018-12-07 23:38:13 +08:00
|
|
|
Type *T = I.getType();
|
|
|
|
if (T->isIntOrIntVectorTy()) {
|
|
|
|
if (AliveBits.try_emplace(&I, T->getScalarSizeInBits(), 0).second)
|
2019-01-12 17:09:15 +08:00
|
|
|
Worklist.insert(&I);
|
2015-08-14 19:09:09 +08:00
|
|
|
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Non-integer-typed instructions...
|
|
|
|
for (Use &OI : I.operands()) {
|
|
|
|
if (Instruction *J = dyn_cast<Instruction>(OI)) {
|
2018-12-07 23:38:13 +08:00
|
|
|
Type *T = J->getType();
|
|
|
|
if (T->isIntOrIntVectorTy())
|
|
|
|
AliveBits[J] = APInt::getAllOnesValue(T->getScalarSizeInBits());
|
2019-03-03 22:50:01 +08:00
|
|
|
else
|
|
|
|
Visited.insert(J);
|
2019-01-12 17:09:15 +08:00
|
|
|
Worklist.insert(J);
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
// To save memory, we don't add I to the Visited set here. Instead, we
|
|
|
|
// check isAlwaysLive on every instruction when searching for dead
|
|
|
|
// instructions later (we need to check isAlwaysLive for the
|
|
|
|
// integer-typed instructions anyway).
|
|
|
|
}
|
|
|
|
|
|
|
|
// Propagate liveness backwards to operands.
|
|
|
|
while (!Worklist.empty()) {
|
|
|
|
Instruction *UserI = Worklist.pop_back_val();
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "DemandedBits: Visiting: " << *UserI);
|
2015-08-14 19:09:09 +08:00
|
|
|
APInt AOut;
|
2019-03-03 22:50:01 +08:00
|
|
|
bool InputIsKnownDead = false;
|
2018-12-07 23:38:13 +08:00
|
|
|
if (UserI->getType()->isIntOrIntVectorTy()) {
|
2015-08-14 19:09:09 +08:00
|
|
|
AOut = AliveBits[UserI];
|
Reapply "[BDCE][DemandedBits] Detect dead uses of undead instructions"
This (mostly) fixes https://bugs.llvm.org/show_bug.cgi?id=39771.
BDCE currently detects instructions that don't have any demanded bits
and replaces their uses with zero. However, if an instruction has
multiple uses, then some of the uses may be dead (have no demanded bits)
even though the instruction itself is still live. This patch extends
DemandedBits/BDCE to detect such uses and replace them with zero.
While this will not immediately render any instructions dead, it may
lead to simplifications (in the motivating case, by converting a rotate
into a simple shift), break dependencies, etc.
The implementation tries to strike a balance between analysis power and
complexity/memory usage. Originally I wanted to track demanded bits on
a per-use level, but ultimately we're only really interested in whether
a use is entirely dead or not. I'm using an extra set to track which uses
are dead. However, as initially all uses are dead, I'm not storing uses
those user is also dead. This case is checked separately instead.
The previous attempt to land this lead to miscompiles, because cases
where uses were initially dead but were later found to be live during
further analysis were not always correctly removed from the DeadUses
set. This is fixed now and the added test case demanstrates such an
instance.
Differential Revision: https://reviews.llvm.org/D55563
llvm-svn: 350188
2019-01-01 18:05:26 +08:00
|
|
|
LLVM_DEBUG(dbgs() << " Alive Out: 0x"
|
|
|
|
<< Twine::utohexstr(AOut.getLimitedValue()));
|
2019-03-03 22:50:01 +08:00
|
|
|
|
|
|
|
// If all bits of the output are dead, then all bits of the input
|
|
|
|
// are also dead.
|
|
|
|
InputIsKnownDead = !AOut && !isAlwaysLive(UserI);
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\n");
|
2015-08-14 19:09:09 +08:00
|
|
|
|
2017-04-27 00:39:58 +08:00
|
|
|
KnownBits Known, Known2;
|
2019-01-05 05:21:43 +08:00
|
|
|
bool KnownBitsComputed = false;
|
2015-08-14 19:09:09 +08:00
|
|
|
// Compute the set of alive bits for each operand. These are anded into the
|
|
|
|
// existing set, if any, and if that changes the set of alive bits, the
|
|
|
|
// operand is added to the work-list.
|
|
|
|
for (Use &OI : UserI->operands()) {
|
2019-01-05 05:21:43 +08:00
|
|
|
// We also want to detect dead uses of arguments, but will only store
|
|
|
|
// demanded bits for instructions.
|
|
|
|
Instruction *I = dyn_cast<Instruction>(OI);
|
|
|
|
if (!I && !isa<Argument>(OI))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
Type *T = OI->getType();
|
|
|
|
if (T->isIntOrIntVectorTy()) {
|
|
|
|
unsigned BitWidth = T->getScalarSizeInBits();
|
|
|
|
APInt AB = APInt::getAllOnesValue(BitWidth);
|
2019-03-03 22:50:01 +08:00
|
|
|
if (InputIsKnownDead) {
|
2019-01-05 05:21:43 +08:00
|
|
|
AB = APInt(BitWidth, 0);
|
|
|
|
} else {
|
|
|
|
// Bits of each operand that are used to compute alive bits of the
|
|
|
|
// output are alive, all others are dead.
|
|
|
|
determineLiveOperandBits(UserI, OI, OI.getOperandNo(), AOut, AB,
|
|
|
|
Known, Known2, KnownBitsComputed);
|
|
|
|
|
|
|
|
// Keep track of uses which have no demanded bits.
|
|
|
|
if (AB.isNullValue())
|
|
|
|
DeadUses.insert(&OI);
|
|
|
|
else
|
|
|
|
DeadUses.erase(&OI);
|
|
|
|
}
|
2015-08-14 19:09:09 +08:00
|
|
|
|
2019-01-05 05:21:43 +08:00
|
|
|
if (I) {
|
2015-08-14 19:09:09 +08:00
|
|
|
// If we've added to the set of alive bits (or the operand has not
|
|
|
|
// been previously visited), then re-queue the operand to be visited
|
|
|
|
// again.
|
2019-03-03 19:12:57 +08:00
|
|
|
auto Res = AliveBits.try_emplace(I);
|
|
|
|
if (Res.second || (AB |= Res.first->second) != Res.first->second) {
|
|
|
|
Res.first->second = std::move(AB);
|
2019-01-12 17:09:15 +08:00
|
|
|
Worklist.insert(I);
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
}
|
2019-03-03 22:50:01 +08:00
|
|
|
} else if (I && Visited.insert(I).second) {
|
2019-01-12 17:09:15 +08:00
|
|
|
Worklist.insert(I);
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
APInt DemandedBits::getDemandedBits(Instruction *I) {
|
2018-12-07 07:50:32 +08:00
|
|
|
performAnalysis();
|
2018-12-07 08:42:03 +08:00
|
|
|
|
2016-07-21 21:37:55 +08:00
|
|
|
auto Found = AliveBits.find(I);
|
|
|
|
if (Found != AliveBits.end())
|
|
|
|
return Found->second;
|
2018-12-07 23:38:13 +08:00
|
|
|
|
|
|
|
const DataLayout &DL = I->getModule()->getDataLayout();
|
|
|
|
return APInt::getAllOnesValue(
|
|
|
|
DL.getTypeSizeInBits(I->getType()->getScalarType()));
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool DemandedBits::isInstructionDead(Instruction *I) {
|
2015-10-08 20:39:50 +08:00
|
|
|
performAnalysis();
|
|
|
|
|
2015-08-14 19:09:09 +08:00
|
|
|
return !Visited.count(I) && AliveBits.find(I) == AliveBits.end() &&
|
|
|
|
!isAlwaysLive(I);
|
|
|
|
}
|
|
|
|
|
Reapply "[BDCE][DemandedBits] Detect dead uses of undead instructions"
This (mostly) fixes https://bugs.llvm.org/show_bug.cgi?id=39771.
BDCE currently detects instructions that don't have any demanded bits
and replaces their uses with zero. However, if an instruction has
multiple uses, then some of the uses may be dead (have no demanded bits)
even though the instruction itself is still live. This patch extends
DemandedBits/BDCE to detect such uses and replace them with zero.
While this will not immediately render any instructions dead, it may
lead to simplifications (in the motivating case, by converting a rotate
into a simple shift), break dependencies, etc.
The implementation tries to strike a balance between analysis power and
complexity/memory usage. Originally I wanted to track demanded bits on
a per-use level, but ultimately we're only really interested in whether
a use is entirely dead or not. I'm using an extra set to track which uses
are dead. However, as initially all uses are dead, I'm not storing uses
those user is also dead. This case is checked separately instead.
The previous attempt to land this lead to miscompiles, because cases
where uses were initially dead but were later found to be live during
further analysis were not always correctly removed from the DeadUses
set. This is fixed now and the added test case demanstrates such an
instance.
Differential Revision: https://reviews.llvm.org/D55563
llvm-svn: 350188
2019-01-01 18:05:26 +08:00
|
|
|
bool DemandedBits::isUseDead(Use *U) {
|
|
|
|
// We only track integer uses, everything else is assumed live.
|
|
|
|
if (!(*U)->getType()->isIntOrIntVectorTy())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Uses by always-live instructions are never dead.
|
|
|
|
Instruction *UserI = cast<Instruction>(U->getUser());
|
|
|
|
if (isAlwaysLive(UserI))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
performAnalysis();
|
|
|
|
if (DeadUses.count(U))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If no output bits are demanded, no input bits are demanded and the use
|
|
|
|
// is dead. These uses might not be explicitly present in the DeadUses map.
|
|
|
|
if (UserI->getType()->isIntOrIntVectorTy()) {
|
|
|
|
auto Found = AliveBits.find(UserI);
|
|
|
|
if (Found != AliveBits.end() && Found->second.isNullValue())
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
void DemandedBits::print(raw_ostream &OS) {
|
|
|
|
performAnalysis();
|
2015-10-08 20:39:59 +08:00
|
|
|
for (auto &KV : AliveBits) {
|
2017-12-29 00:58:54 +08:00
|
|
|
OS << "DemandedBits: 0x" << Twine::utohexstr(KV.second.getLimitedValue())
|
|
|
|
<< " for " << *KV.first << '\n';
|
2015-10-08 20:39:59 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-08-17 19:53:52 +08:00
|
|
|
static APInt determineLiveOperandBitsAddCarry(unsigned OperandNo,
|
|
|
|
const APInt &AOut,
|
|
|
|
const KnownBits &LHS,
|
|
|
|
const KnownBits &RHS,
|
|
|
|
bool CarryZero, bool CarryOne) {
|
|
|
|
assert(!(CarryZero && CarryOne) &&
|
|
|
|
"Carry can't be zero and one at the same time");
|
|
|
|
|
|
|
|
// The following check should be done by the caller, as it also indicates
|
|
|
|
// that LHS and RHS don't need to be computed.
|
|
|
|
//
|
|
|
|
// if (AOut.isMask())
|
|
|
|
// return AOut;
|
|
|
|
|
|
|
|
// Boundary bits' carry out is unaffected by their carry in.
|
|
|
|
APInt Bound = (LHS.Zero & RHS.Zero) | (LHS.One & RHS.One);
|
|
|
|
|
|
|
|
// First, the alive carry bits are determined from the alive output bits:
|
|
|
|
// Let demand ripple to the right but only up to any set bit in Bound.
|
|
|
|
// AOut = -1----
|
|
|
|
// Bound = ----1-
|
|
|
|
// ACarry&~AOut = --111-
|
|
|
|
APInt RBound = Bound.reverseBits();
|
|
|
|
APInt RAOut = AOut.reverseBits();
|
|
|
|
APInt RProp = RAOut + (RAOut | ~RBound);
|
|
|
|
APInt RACarry = RProp ^ ~RBound;
|
|
|
|
APInt ACarry = RACarry.reverseBits();
|
|
|
|
|
|
|
|
// Then, the alive input bits are determined from the alive carry bits:
|
|
|
|
APInt NeededToMaintainCarryZero;
|
|
|
|
APInt NeededToMaintainCarryOne;
|
|
|
|
if (OperandNo == 0) {
|
|
|
|
NeededToMaintainCarryZero = LHS.Zero | ~RHS.Zero;
|
|
|
|
NeededToMaintainCarryOne = LHS.One | ~RHS.One;
|
|
|
|
} else {
|
|
|
|
NeededToMaintainCarryZero = RHS.Zero | ~LHS.Zero;
|
|
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NeededToMaintainCarryOne = RHS.One | ~LHS.One;
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|
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|
}
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|
|
|
|
|
|
|
// As in computeForAddCarry
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|
|
|
APInt PossibleSumZero = ~LHS.Zero + ~RHS.Zero + !CarryZero;
|
|
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|
APInt PossibleSumOne = LHS.One + RHS.One + CarryOne;
|
|
|
|
|
|
|
|
// The below is simplified from
|
|
|
|
//
|
|
|
|
// APInt CarryKnownZero = ~(PossibleSumZero ^ LHS.Zero ^ RHS.Zero);
|
|
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|
// APInt CarryKnownOne = PossibleSumOne ^ LHS.One ^ RHS.One;
|
|
|
|
// APInt CarryUnknown = ~(CarryKnownZero | CarryKnownOne);
|
|
|
|
//
|
|
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|
// APInt NeededToMaintainCarry =
|
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|
// (CarryKnownZero & NeededToMaintainCarryZero) |
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|
// (CarryKnownOne & NeededToMaintainCarryOne) |
|
|
|
|
// CarryUnknown;
|
|
|
|
|
|
|
|
APInt NeededToMaintainCarry = (~PossibleSumZero | NeededToMaintainCarryZero) &
|
|
|
|
(PossibleSumOne | NeededToMaintainCarryOne);
|
|
|
|
|
|
|
|
APInt AB = AOut | (ACarry & NeededToMaintainCarry);
|
|
|
|
return AB;
|
|
|
|
}
|
|
|
|
|
|
|
|
APInt DemandedBits::determineLiveOperandBitsAdd(unsigned OperandNo,
|
|
|
|
const APInt &AOut,
|
|
|
|
const KnownBits &LHS,
|
|
|
|
const KnownBits &RHS) {
|
|
|
|
return determineLiveOperandBitsAddCarry(OperandNo, AOut, LHS, RHS, true,
|
|
|
|
false);
|
|
|
|
}
|
|
|
|
|
|
|
|
APInt DemandedBits::determineLiveOperandBitsSub(unsigned OperandNo,
|
|
|
|
const APInt &AOut,
|
|
|
|
const KnownBits &LHS,
|
|
|
|
const KnownBits &RHS) {
|
|
|
|
KnownBits NRHS;
|
|
|
|
NRHS.Zero = RHS.One;
|
|
|
|
NRHS.One = RHS.Zero;
|
|
|
|
return determineLiveOperandBitsAddCarry(OperandNo, AOut, LHS, NRHS, false,
|
|
|
|
true);
|
|
|
|
}
|
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
FunctionPass *llvm::createDemandedBitsWrapperPass() {
|
|
|
|
return new DemandedBitsWrapperPass();
|
|
|
|
}
|
|
|
|
|
2016-11-24 01:53:26 +08:00
|
|
|
AnalysisKey DemandedBitsAnalysis::Key;
|
2016-04-19 07:55:01 +08:00
|
|
|
|
|
|
|
DemandedBits DemandedBitsAnalysis::run(Function &F,
|
2016-08-09 08:28:15 +08:00
|
|
|
FunctionAnalysisManager &AM) {
|
2016-12-19 16:22:17 +08:00
|
|
|
auto &AC = AM.getResult<AssumptionAnalysis>(F);
|
2016-04-19 07:55:01 +08:00
|
|
|
auto &DT = AM.getResult<DominatorTreeAnalysis>(F);
|
2016-12-19 16:22:17 +08:00
|
|
|
return DemandedBits(F, AC, DT);
|
2016-04-19 07:55:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
PreservedAnalyses DemandedBitsPrinterPass::run(Function &F,
|
|
|
|
FunctionAnalysisManager &AM) {
|
|
|
|
AM.getResult<DemandedBitsAnalysis>(F).print(OS);
|
|
|
|
return PreservedAnalyses::all();
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|