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llvm-project/llvm/test/CodeGen/ARM/ldrd-memoper.ll

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Preserve MachineMemOperands in ARMLoadStoreOptimizer. Fixes PR8113. llvm-svn: 144409
2011-11-12 06:18:09 +08:00
; RUN: llc %s -o /dev/null -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -debug-only=arm-ldst-opt 2> %t
; RUN: FileCheck %s < %t
; REQUIRES: asserts
; PR8113: ARMLoadStoreOptimizer must preserve memoperands.
@b = external global i64*
; CHECK: Formed {{.*}} t2LDRD{{.*}} mem:LD4[%0] LD4[%0+4]
define i64 @t(i64 %a) nounwind readonly {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i64*, i64** @b, align 4
%1 = load i64, i64* %0, align 4
Preserve MachineMemOperands in ARMLoadStoreOptimizer. Fixes PR8113. llvm-svn: 144409
2011-11-12 06:18:09 +08:00
%2 = mul i64 %1, %a
ret i64 %2
}