2019-07-27 22:32:23 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-flat-for-global,+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s
|
|
|
|
|
; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s
|
2013-10-09 02:06:36 +08:00
|
|
|
|
2014-02-02 08:05:35 +08:00
|
|
|
; FIXME: Broken on evergreen
|
|
|
|
|
; FIXME: For some reason the 8 and 16 vectors are being stored as
|
|
|
|
|
; individual elements instead of 128-bit stores.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; FIXME: Why is the constant moved into the intermediate register and
|
|
|
|
|
; not just directly into the vector component?
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insertelement_v4f32_0:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s4, 0x40a00000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
2020-01-14 06:54:17 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insertelement_v4f32_0:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s4, 0x40a00000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
2020-01-14 06:54:17 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0
|
|
|
|
|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insertelement_v4f32_1:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insertelement_v4f32_1:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s5, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1
|
|
|
|
|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insertelement_v4f32_2:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insertelement_v4f32_2:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2
|
|
|
|
|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insertelement_v4f32_3:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s7
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insertelement_v4f32_3:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s7
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3
|
|
|
|
|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insertelement_v4i32_0:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_movk_i32 s4, 0x3e7
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
2020-01-14 06:54:17 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insertelement_v4i32_0:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_movk_i32 s4, 0x3e7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
2020-01-14 06:54:17 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <4 x i32> %a, i32 999, i32 0
|
|
|
|
|
store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insertelement_v3f32_1:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, 0x40a00000
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insertelement_v3f32_1:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0x40a00000
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1
|
|
|
|
|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insertelement_v3f32_2:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, 0x40a00000
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insertelement_v3f32_2:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0x40a00000
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2
|
|
|
|
|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; GCN-LABEL: insertelement_v3f32_3:
|
|
|
|
|
; GCN: ; %bb.0:
|
|
|
|
|
; GCN-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3
|
|
|
|
|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
define <4 x float> @insertelement_to_sgpr() nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; GCN-LABEL: insertelement_to_sgpr:
|
|
|
|
|
; GCN: ; %bb.0:
|
|
|
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
|
|
|
; GCN-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x0
|
|
|
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s12, 0
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s4, s12
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s5, s12
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s6, s12
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s7, s12
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s8, s12
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s9, s12
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s10, s12
|
|
|
|
|
; GCN-NEXT: s_mov_b32 s11, s12
|
|
|
|
|
; GCN-NEXT: image_gather4_lz v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1
|
|
|
|
|
; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
%tmp = load <4 x i32>, <4 x i32> addrspace(4)* undef
|
|
|
|
|
%tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> %tmp1, i1 0, i32 0, i32 0)
|
2016-07-12 16:12:16 +08:00
|
|
|
ret <4 x float> %tmp2
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v2f32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x4
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v2f32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x10
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v3f32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x8
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s10
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s8
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v3f32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x20
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s10
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s8
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v4f32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x8
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s10
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s8
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-10-14 20:01:10 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v4f32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x20
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s10
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s8
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-10-14 20:01:10 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v8f32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x10
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, 0x40a00000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s15
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s14
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s13
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v8, s12
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v8f32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x40
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, 0x40a00000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s10
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s15
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s14
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s13
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v8, s12
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v16f32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x10
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x20
|
2020-01-14 06:54:17 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v16, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s11
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s13
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v6, s14
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v7, s15
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v8, s16
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v9, s17
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v10, s18
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v11, s19
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v12, s20
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v13, s21
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v14, s22
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v15, s23
|
|
|
|
|
; SI-NEXT: s_mov_b32 m0, s4
|
|
|
|
|
; SI-NEXT: v_movreld_b32_e32 v0, v16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v16f32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x40
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x80
|
2020-01-14 06:54:17 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40a00000
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s9
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s11
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s13
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v6, s14
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v7, s15
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v8, s16
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v9, s17
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v10, s18
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v11, s19
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v12, s20
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v13, s21
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v14, s22
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v15, s23
|
|
|
|
|
; VI-NEXT: s_mov_b32 m0, s4
|
|
|
|
|
; VI-NEXT: v_movreld_b32_e32 v0, v16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v2i32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2020-07-30 19:56:06 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s6
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v2i32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
[AMDGPU] Select s_cselect
Summary:
Add patterns to select s_cselect in the isel.
Handle more cases of implicit SCC accesses in si-fix-sgpr-copies
to allow new patterns to work.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commits
Tags: #llvm
Re-commit D81925 with a bugfix D82370.
Differential Revision: https://reviews.llvm.org/D81925
Differential Revision: https://reviews.llvm.org/D82370
2020-03-04 22:13:08 +08:00
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 1
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s5, s7, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s4, s6, 5
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <2 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v3i32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2020-07-30 19:56:06 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v3i32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
[AMDGPU] Select s_cselect
Summary:
Add patterns to select s_cselect in the isel.
Handle more cases of implicit SCC accesses in si-fix-sgpr-copies
to allow new patterns to work.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commits
Tags: #llvm
Re-commit D81925 with a bugfix D82370.
Differential Revision: https://reviews.llvm.org/D81925
Differential Revision: https://reviews.llvm.org/D82370
2020-03-04 22:13:08 +08:00
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 2
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s5, s10, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 1
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s6, s9, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s4, s8, 5
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s5
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, [8 x i32], i32 %val) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v4i32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x11
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2020-07-30 19:56:06 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s11
|
|
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 3
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s4
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 2
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
|
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v4i32:
|
|
|
|
|
; VI: ; %bb.0:
|
2020-07-30 19:56:06 +08:00
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x44
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_cmp_eq_u32 s6, 3
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s5, s4, s11
|
|
|
|
|
; VI-NEXT: s_cmp_eq_u32 s6, 2
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s7, s4, s10
|
|
|
|
|
; VI-NEXT: s_cmp_eq_u32 s6, 1
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s9, s4, s9
|
|
|
|
|
; VI-NEXT: s_cmp_eq_u32 s6, 0
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s4, s4, s8
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s9
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s7
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-07-19 08:35:03 +08:00
|
|
|
%vecins = insertelement <4 x i32> %a, i32 %val, i32 %b
|
2014-02-02 08:05:35 +08:00
|
|
|
store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v8i32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2020-07-30 19:56:06 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s11
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s15
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v7, 5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s14
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v6, 5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s13
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v5, 5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v8i32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x40
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
[AMDGPU] Select s_cselect
Summary:
Add patterns to select s_cselect in the isel.
Handle more cases of implicit SCC accesses in si-fix-sgpr-copies
to allow new patterns to work.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commits
Tags: #llvm
Re-commit D81925 with a bugfix D82370.
Differential Revision: https://reviews.llvm.org/D81925
Differential Revision: https://reviews.llvm.org/D82370
2020-03-04 22:13:08 +08:00
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 3
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s5, s11, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 2
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s6, s10, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 1
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s7, s9, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s8, s8, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 7
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s9, s15, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 6
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s10, s14, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 5
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s11, s13, 5
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 4
|
|
|
|
|
; VI-NEXT: s_cselect_b32 s4, s12, 5
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s11
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s9
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s8
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s7
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v6, s6
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v7, s5
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <8 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v16i32:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x10
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x20
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s11
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s13
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v6, s14
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v7, s15
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v8, s16
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v9, s17
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v10, s18
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v11, s19
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v12, s20
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v13, s21
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v14, s22
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v15, s23
|
|
|
|
|
; SI-NEXT: s_mov_b32 m0, s4
|
|
|
|
|
; SI-NEXT: v_movreld_b32_e32 v0, 5
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v16i32:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x40
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x80
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s9
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s11
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s13
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v6, s14
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v7, s15
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v8, s16
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v9, s17
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v10, s18
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v11, s19
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v12, s20
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v13, s21
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v14, s22
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v15, s23
|
|
|
|
|
; VI-NEXT: s_mov_b32 m0, s4
|
|
|
|
|
; VI-NEXT: v_movreld_b32_e32 v0, 5
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <16 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v2i16:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0x2
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x3
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, 0x50005
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 4
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, 0xffff, s4
|
|
|
|
|
; SI-NEXT: v_bfi_b32 v0, s4, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v2i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x8
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0xc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x50005
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, s4, 4
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, 0xffff, s4
|
|
|
|
|
; VI-NEXT: v_bfi_b32 v0, s4, v0, v1
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <2 x i16> %a, i16 5, i32 %b
|
|
|
|
|
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v3i16:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s8, s4, 4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s4, 0xffff
|
|
|
|
|
; SI-NEXT: s_lshl_b64 s[4:5], s[4:5], s8
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, 0x50005
|
|
|
|
|
; SI-NEXT: s_and_b32 s9, s5, s8
|
|
|
|
|
; SI-NEXT: s_and_b32 s8, s4, s8
|
|
|
|
|
; SI-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
|
|
|
|
|
; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s5
|
2019-12-20 22:59:15 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s4
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
|
2019-12-20 22:59:15 +08:00
|
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v3i16:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s5, 0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s8, s4, 4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s4, 0xffff
|
|
|
|
|
; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s8
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, 0x50005
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: v_bfi_b32 v0, s5, v0, v1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s8
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s6
|
|
|
|
|
; VI-NEXT: v_bfi_b32 v1, s4, v1, v2
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
|
|
|
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x i16> %a, i16 5, i32 %b
|
|
|
|
|
store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, [8 x i32], <2 x i8> %a, [8 x i32], i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v2i8:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0xa
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x13
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, 0x505
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 3
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, -1, s4
|
|
|
|
|
; SI-NEXT: v_bfi_b32 v0, s4, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v2i8:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x28
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x4c
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, s4, 3
|
|
|
|
|
; VI-NEXT: v_lshlrev_b16_e64 v0, s4, -1
|
2020-08-01 01:48:58 +08:00
|
|
|
; VI-NEXT: v_not_b32_e32 v1, v0
|
|
|
|
|
; VI-NEXT: v_and_b32_e32 v1, s6, v1
|
|
|
|
|
; VI-NEXT: v_and_b32_e32 v0, 0x505, v0
|
|
|
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <2 x i8> %a, i8 5, i32 %b
|
|
|
|
|
store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; FIXME: post legalize i16 and i32 shifts aren't merged because of
|
|
|
|
|
; isTypeDesirableForOp in SimplifyDemandedBits
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, [8 x i32], <3 x i8> %a, [8 x i32], i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v3i8:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0xa
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x13
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, 0x5050505
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 3
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, 0xffff, s4
|
|
|
|
|
; SI-NEXT: v_bfi_b32 v0, s4, v0, v1
|
|
|
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v3i8:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x28
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x4c
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x5050505
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, s4, 3
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, 0xffff, s4
|
|
|
|
|
; VI-NEXT: v_bfi_b32 v0, s4, v0, v1
|
|
|
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x i8> %a, i8 5, i32 %b
|
|
|
|
|
store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, [8 x i32], <4 x i8> %a, [8 x i32], i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v4i8:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0xa
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x13
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, 0x5050505
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 3
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, 0xffff, s4
|
|
|
|
|
; SI-NEXT: v_bfi_b32 v0, s4, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v4i8:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x28
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x4c
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x5050505
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, s4, 3
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, 0xffff, s4
|
|
|
|
|
; VI-NEXT: v_bfi_b32 v0, s4, v0, v1
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <4 x i8> %a, i8 5, i32 %b
|
2016-05-28 08:51:06 +08:00
|
|
|
store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4
|
2014-02-02 08:05:35 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: s_dynamic_insertelement_v8i8:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[4:5], s[10:11], 0x0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s0, s8
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s8, s6, 3
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, 0xffff
|
|
|
|
|
; SI-NEXT: s_lshl_b64 s[6:7], s[6:7], s8
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, 0x5050505
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, s9
|
|
|
|
|
; SI-NEXT: s_and_b32 s9, s7, s8
|
|
|
|
|
; SI-NEXT: s_and_b32 s8, s6, s8
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
|
|
|
|
|
; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: s_dynamic_insertelement_v8i8:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, 0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[4:5], s[10:11], 0x0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s8
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s8, s6, 3
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, 0xffff
|
|
|
|
|
; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s8
|
|
|
|
|
; VI-NEXT: s_mov_b32 s8, 0x5050505
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s9
|
|
|
|
|
; VI-NEXT: s_and_b32 s9, s7, s8
|
|
|
|
|
; VI-NEXT: s_and_b32 s8, s6, s8
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
|
|
|
|
|
; VI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <8 x i8> %a, i8 5, i32 %b
|
2016-05-28 08:51:06 +08:00
|
|
|
store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8
|
2013-10-09 02:06:36 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v16i8:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s5, s11, 24
|
2020-07-30 19:56:06 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s5
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 15
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s5, s11, 16
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 14
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; SI-NEXT: s_movk_i32 s5, 0xff
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v1, s5, v1
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: s_lshr_b32 s6, s11, 8
|
2020-07-30 19:56:06 +08:00
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s6
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 13
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s11
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 12
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v2, s5, v2
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, 0xffff
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v1, s6, v1
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s10, 24
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v3, v1, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 11
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s10, 16
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 10
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v1, s5, v1
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s10, 8
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 9
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 8
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v2, s5, v2
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v1, s6, v1
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s9, 24
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v2, v1, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s9, 16
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v1, s5, v1
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s9, 8
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s9
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v4, s5, v4
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v1, v4, v1
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v1, s6, v1
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s8, 24
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s8, 16
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v4, s5, v4
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s7, s8, 8
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v4, v0
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s7
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s8
|
|
|
|
|
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v5, s5, v5
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
|
|
|
; SI-NEXT: v_and_b32_e32 v4, s6, v4
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v4, v0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v16i8:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s11, 24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 15
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_lshr_b32 s5, s11, 16
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 14
|
[AMDGPU] Enable compare operations to be selected by divergence
Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.
Reviewers: rampitec, arsenm
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82194
2020-06-19 22:51:54 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s11, 8
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 13
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 12
|
[AMDGPU] Enable compare operations to be selected by divergence
Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.
Reviewers: rampitec, arsenm
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82194
2020-06-19 22:51:54 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: s_lshr_b32 s5, s10, 24
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v3, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 11
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_lshr_b32 s5, s10, 16
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 10
|
[AMDGPU] Enable compare operations to be selected by divergence
Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.
Reviewers: rampitec, arsenm
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82194
2020-06-19 22:51:54 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s10, 8
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 9
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s10
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 8
|
[AMDGPU] Enable compare operations to be selected by divergence
Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.
Reviewers: rampitec, arsenm
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82194
2020-06-19 22:51:54 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: s_lshr_b32 s5, s9, 24
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v2, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_lshr_b32 s5, s9, 16
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6
|
[AMDGPU] Enable compare operations to be selected by divergence
Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.
Reviewers: rampitec, arsenm
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82194
2020-06-19 22:51:54 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s9, 8
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4
|
[AMDGPU] Enable compare operations to be selected by divergence
Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.
Reviewers: rampitec, arsenm
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82194
2020-06-19 22:51:54 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: s_lshr_b32 s5, s8, 24
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_lshr_b32 s5, s8, 16
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2
|
[AMDGPU] Enable compare operations to be selected by divergence
Summary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.
Reviewers: rampitec, arsenm
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82194
2020-06-19 22:51:54 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s8, 8
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s5
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s8
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-02-02 08:05:35 +08:00
|
|
|
%vecins = insertelement <16 x i8> %a, i8 5, i32 %b
|
|
|
|
|
store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16
|
2013-10-09 02:06:36 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
2014-04-08 03:45:45 +08:00
|
|
|
|
|
|
|
|
; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that
|
|
|
|
|
; the compiler doesn't crash.
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: insert_split_bb:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_cmp_lg_u32 s0, 0
|
|
|
|
|
; SI-NEXT: s_cbranch_scc0 BB26_2
|
|
|
|
|
; SI-NEXT: ; %bb.1: ; %else
|
|
|
|
|
; SI-NEXT: s_load_dword s1, s[6:7], 0x1
|
2020-04-06 21:05:58 +08:00
|
|
|
; SI-NEXT: s_mov_b64 s[2:3], 0
|
|
|
|
|
; SI-NEXT: s_andn2_b64 vcc, exec, s[2:3]
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b64 vcc, vcc
|
|
|
|
|
; SI-NEXT: s_cbranch_vccz BB26_3
|
|
|
|
|
; SI-NEXT: s_branch BB26_4
|
|
|
|
|
; SI-NEXT: BB26_2:
|
|
|
|
|
; SI-NEXT: BB26_3: ; %if
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_load_dword s1, s[6:7], 0x0
|
2020-04-06 21:05:58 +08:00
|
|
|
; SI-NEXT: BB26_4: ; %endif
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s7, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s1
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: insert_split_bb:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dword s0, s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_cmp_lg_u32 s0, 0
|
|
|
|
|
; VI-NEXT: s_cbranch_scc0 BB26_2
|
2020-05-13 05:18:53 +08:00
|
|
|
; VI-NEXT: ; %bb.1: ; %else
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_load_dword s1, s[6:7], 0x4
|
2020-07-15 09:22:42 +08:00
|
|
|
; VI-NEXT: s_cbranch_execz BB26_3
|
2020-04-06 21:05:58 +08:00
|
|
|
; VI-NEXT: s_branch BB26_4
|
|
|
|
|
; VI-NEXT: BB26_2:
|
|
|
|
|
; VI-NEXT: BB26_3: ; %if
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_load_dword s1, s[6:7], 0x0
|
2020-04-06 21:05:58 +08:00
|
|
|
; VI-NEXT: BB26_4: ; %endif
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s1
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-04-08 03:45:45 +08:00
|
|
|
entry:
|
|
|
|
|
%0 = insertelement <2 x i32> undef, i32 %a, i32 0
|
|
|
|
|
%1 = icmp eq i32 %a, 0
|
|
|
|
|
br i1 %1, label %if, label %else
|
|
|
|
|
|
|
|
|
|
if:
|
2015-02-28 05:17:42 +08:00
|
|
|
%2 = load i32, i32 addrspace(1)* %in
|
2014-04-08 03:45:45 +08:00
|
|
|
%3 = insertelement <2 x i32> %0, i32 %2, i32 1
|
|
|
|
|
br label %endif
|
|
|
|
|
|
|
|
|
|
else:
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%4 = getelementptr i32, i32 addrspace(1)* %in, i32 1
|
2015-02-28 05:17:42 +08:00
|
|
|
%5 = load i32, i32 addrspace(1)* %4
|
2014-04-08 03:45:45 +08:00
|
|
|
%6 = insertelement <2 x i32> %0, i32 %5, i32 1
|
|
|
|
|
br label %endif
|
|
|
|
|
|
|
|
|
|
endif:
|
|
|
|
|
%7 = phi <2 x i32> [%3, %if], [%6, %else]
|
|
|
|
|
store <2 x i32> %7, <2 x i32> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2014-09-20 07:02:18 +08:00
|
|
|
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, [8 x i32], <2 x double> %a, [8 x i32], i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v2f64:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xc
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x18
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, 0x40200000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v2f64:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x30
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x60
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0x40200000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-09-20 07:02:18 +08:00
|
|
|
%vecins = insertelement <2 x double> %a, double 8.0, i32 %b
|
|
|
|
|
store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v2i64:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v2i64:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-09-20 07:02:18 +08:00
|
|
|
%vecins = insertelement <2 x i64> %a, i64 5, i32 %b
|
|
|
|
|
store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v3i64:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0x10
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s13
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 2
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s12
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v4, v0, 5, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v3i64:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x40
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s13
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 2
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s12
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v4, v0, 5, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2016-05-28 08:51:06 +08:00
|
|
|
%vecins = insertelement <3 x i64> %a, i64 5, i32 %b
|
|
|
|
|
store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v4f64:
|
|
|
|
|
; SI: ; %bb.0:
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8
|
|
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x10
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, 0x40200000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s15
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 3
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s14
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s13
|
2020-06-24 22:27:23 +08:00
|
|
|
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 2
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v4f64:
|
|
|
|
|
; VI: ; %bb.0:
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x40
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, 0x40200000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s11
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s10
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s9
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s15
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 3
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s14
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s13
|
2020-06-24 22:27:23 +08:00
|
|
|
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 2
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; VI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
2014-09-20 07:02:18 +08:00
|
|
|
%vecins = insertelement <4 x double> %a, double 8.0, i32 %b
|
|
|
|
|
store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-05 00:34:35 +08:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 {
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-LABEL: dynamic_insertelement_v8f64:
|
|
|
|
|
; SI: ; %bb.0:
|
2020-05-13 05:18:53 +08:00
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x10
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_load_dword s4, s[4:5], 0x20
|
2020-05-13 05:18:53 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v16, 0x40200000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0x100f000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
2020-05-13 05:18:53 +08:00
|
|
|
; SI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 1
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v3, s11
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v5, s13
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v6, s14
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v7, s15
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v8, s16
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v9, s17
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v10, s18
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v11, s19
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v12, s20
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v13, s21
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v14, s22
|
|
|
|
|
; SI-NEXT: v_mov_b32_e32 v15, s23
|
|
|
|
|
; SI-NEXT: s_mov_b32 m0, s4
|
2020-05-14 02:46:28 +08:00
|
|
|
; SI-NEXT: v_movreld_b32_e32 v0, 0
|
|
|
|
|
; SI-NEXT: v_movreld_b32_e32 v1, v16
|
2020-05-13 05:18:53 +08:00
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: dynamic_insertelement_v8f64:
|
|
|
|
|
; VI: ; %bb.0:
|
2020-05-13 05:18:53 +08:00
|
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x40
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_load_dword s4, s[4:5], 0x80
|
2020-05-13 05:18:53 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40200000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0x1100f000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
2020-05-13 05:18:53 +08:00
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, s8
|
|
|
|
|
; VI-NEXT: s_lshl_b32 s4, s4, 1
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v1, s9
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, s10
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, s11
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v4, s12
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v5, s13
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v6, s14
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v7, s15
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v8, s16
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v9, s17
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v10, s18
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v11, s19
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v12, s20
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v13, s21
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v14, s22
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v15, s23
|
|
|
|
|
; VI-NEXT: s_mov_b32 m0, s4
|
2020-05-14 02:46:28 +08:00
|
|
|
; VI-NEXT: v_movreld_b32_e32 v0, 0
|
|
|
|
|
; VI-NEXT: v_movreld_b32_e32 v1, v16
|
2020-05-13 05:18:53 +08:00
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
2019-07-27 22:32:23 +08:00
|
|
|
; VI-NEXT: s_endpgm
|
2014-09-20 07:02:18 +08:00
|
|
|
%vecins = insertelement <8 x double> %a, double 8.0, i32 %b
|
|
|
|
|
store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2016-07-12 16:12:16 +08:00
|
|
|
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
2017-04-05 00:34:35 +08:00
|
|
|
|
|
|
|
|
attributes #0 = { nounwind }
|
|
|
|
|
attributes #1 = { nounwind readnone }
|