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llvm-project/clang/lib/Headers/avx512cdintrin.h

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Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
/*===------------- avx512cdintrin.h - AVX512CD intrinsics ------------------===
*
*
Move the builtin headers to use the new license file header. Summary: These all had somewhat custom file headers with different text from the ones I searched for previously, and so I missed them. Thanks to Hal and Kristina and others who prompted me to fix this, and sorry it took so long. Reviewers: hfinkel Subscribers: mcrosier, javed.absar, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60406 llvm-svn: 357941
2019-04-09 04:51:30 +08:00
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
* See https://llvm.org/LICENSE.txt for license information.
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
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*
*===-----------------------------------------------------------------------===
*/
#ifndef __IMMINTRIN_H
#error "Never use <avx512cdintrin.h> directly; include <immintrin.h> instead."
#endif
#ifndef __AVX512CDINTRIN_H
#define __AVX512CDINTRIN_H
/* Define the default attributes for the functions in this file. */
[Builtins][Attributes][X86] Tag all X86 builtins with their required vector width. Add a min_vector_width function attribute and tag all x86 instrinsics with it This is part of an ongoing attempt at making 512 bit vectors illegal in the X86 backend type legalizer due to CPU frequency penalties associated with wide vectors on Skylake Server CPUs. We want the loop vectorizer to be able to emit IR containing wide vectors as intermediate operations in vectorized code and allow these wide vectors to be legalized to 256 bits by the X86 backend even though we are targetting a CPU that supports 512 bit vectors. This is similar to what happens with an AVX2 CPU, the vectorizer can emit wide vectors and the backend will split them. We want this splitting behavior, but still be able to use new Skylake instructions that work on 256-bit vectors and support things like masking and gather/scatter. Of course if the user uses explicit vector code in their source code we need to not split those operations. Especially if they have used any of the 512-bit vector intrinsics from immintrin.h. And we need to make it so that merely using the intrinsics produces the expected code in order to be backwards compatible. To support this goal, this patch adds a new IR function attribute "min-legal-vector-width" that can indicate the need for a minimum vector width to be legal in the backend. We need to ensure this attribute is set to the largest vector width needed by any intrinsics from immintrin.h that the function uses. The inliner will be reponsible for merging this attribute when a function is inlined. We may also need a way to limit inlining in the future as well, but we can discuss that in the future. To make things more complicated, there are two different ways intrinsics are implemented in immintrin.h. Either as an always_inline function containing calls to builtins(can be target specific or target independent) or vector extension code. Or as a macro wrapper around a taget specific builtin. I believe I've removed all cases where the macro was around a target independent builtin. To support the always_inline function case this patch adds attribute((min_vector_width(128))) that can be used to tag these functions with their vector width. All x86 intrinsic functions that operate on vectors have been tagged with this attribute. To support the macro case, all x86 specific builtins have also been tagged with the vector width that they require. Use of any builtin with this property will implicitly increase the min_vector_width of the function that calls it. I've done this as a new property in the attribute string for the builtin rather than basing it on the type string so that we can opt into it on a per builtin basis and avoid any impact to target independent builtins. There will be future work to support vectors passed as function arguments and supporting inline assembly. And whatever else we can find that isn't covered by this patch. Special thanks to Chandler who suggested this direction and reviewed a preview version of this patch. And thanks to Eric Christopher who has had many conversations with me about this issue. Differential Revision: https://reviews.llvm.org/D48617 llvm-svn: 336583
2018-07-10 03:00:16 +08:00
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512cd"), __min_vector_width__(512)))
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
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static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_conflict_epi64 (__m512i __A)
{
[X86] Remove mask and passthru arguments from vpconflict builtins. Use select in IR instead. llvm-svn: 352173
2019-01-25 15:08:22 +08:00
return (__m512i) __builtin_ia32_vpconflictdi_512 ((__v8di) __A);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
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}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_mask_conflict_epi64 (__m512i __W, __mmask8 __U, __m512i __A)
{
[X86] Remove mask and passthru arguments from vpconflict builtins. Use select in IR instead. llvm-svn: 352173
2019-01-25 15:08:22 +08:00
return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
(__v8di)_mm512_conflict_epi64(__A),
(__v8di)__W);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
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}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_maskz_conflict_epi64 (__mmask8 __U, __m512i __A)
{
[X86] Remove mask and passthru arguments from vpconflict builtins. Use select in IR instead. llvm-svn: 352173
2019-01-25 15:08:22 +08:00
return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
(__v8di)_mm512_conflict_epi64(__A),
(__v8di)_mm512_setzero_si512 ());
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_conflict_epi32 (__m512i __A)
{
[X86] Remove mask and passthru arguments from vpconflict builtins. Use select in IR instead. llvm-svn: 352173
2019-01-25 15:08:22 +08:00
return (__m512i) __builtin_ia32_vpconflictsi_512 ((__v16si) __A);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_mask_conflict_epi32 (__m512i __W, __mmask16 __U, __m512i __A)
{
[X86] Remove mask and passthru arguments from vpconflict builtins. Use select in IR instead. llvm-svn: 352173
2019-01-25 15:08:22 +08:00
return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
(__v16si)_mm512_conflict_epi32(__A),
(__v16si)__W);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
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}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_maskz_conflict_epi32 (__mmask16 __U, __m512i __A)
{
[X86] Remove mask and passthru arguments from vpconflict builtins. Use select in IR instead. llvm-svn: 352173
2019-01-25 15:08:22 +08:00
return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
(__v16si)_mm512_conflict_epi32(__A),
(__v16si)_mm512_setzero_si512());
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
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}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_lzcnt_epi32 (__m512i __A)
{
[X86] Remove mask argument from some builtins that are handled completely in CGBuiltin.cpp. Just wrap a select builtin around them in the header file instead. llvm-svn: 333027
2018-05-23 04:48:24 +08:00
return (__m512i) __builtin_ia32_vplzcntd_512 ((__v16si) __A);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_mask_lzcnt_epi32 (__m512i __W, __mmask16 __U, __m512i __A)
{
[X86] Remove mask argument from some builtins that are handled completely in CGBuiltin.cpp. Just wrap a select builtin around them in the header file instead. llvm-svn: 333027
2018-05-23 04:48:24 +08:00
return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
(__v16si)_mm512_lzcnt_epi32(__A),
(__v16si)__W);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_maskz_lzcnt_epi32 (__mmask16 __U, __m512i __A)
{
[X86] Remove mask argument from some builtins that are handled completely in CGBuiltin.cpp. Just wrap a select builtin around them in the header file instead. llvm-svn: 333027
2018-05-23 04:48:24 +08:00
return (__m512i)__builtin_ia32_selectd_512((__mmask16)__U,
(__v16si)_mm512_lzcnt_epi32(__A),
(__v16si)_mm512_setzero_si512());
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_lzcnt_epi64 (__m512i __A)
{
[X86] Remove mask argument from some builtins that are handled completely in CGBuiltin.cpp. Just wrap a select builtin around them in the header file instead. llvm-svn: 333027
2018-05-23 04:48:24 +08:00
return (__m512i) __builtin_ia32_vplzcntq_512 ((__v8di) __A);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_mask_lzcnt_epi64 (__m512i __W, __mmask8 __U, __m512i __A)
{
[X86] Remove mask argument from some builtins that are handled completely in CGBuiltin.cpp. Just wrap a select builtin around them in the header file instead. llvm-svn: 333027
2018-05-23 04:48:24 +08:00
return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
(__v8di)_mm512_lzcnt_epi64(__A),
(__v8di)__W);
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_maskz_lzcnt_epi64 (__mmask8 __U, __m512i __A)
{
[X86] Remove mask argument from some builtins that are handled completely in CGBuiltin.cpp. Just wrap a select builtin around them in the header file instead. llvm-svn: 333027
2018-05-23 04:48:24 +08:00
return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
(__v8di)_mm512_lzcnt_epi64(__A),
(__v8di)_mm512_setzero_si512());
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
}
[Clang][BuiltIn][AVX512] Adding intrinsics without mask for VBROADCAST and VPBROADCAST instruction set . Differential Revision: http://reviews.llvm.org/D19196 llvm-svn: 267696
2016-04-27 19:43:14 +08:00
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_broadcastmb_epi64 (__mmask8 __A)
{
lowering broadcastm Change-Id: I0661abea3e3742860e0a03ff9e4fcdc367eff7db llvm-svn: 317456
2017-11-06 15:04:12 +08:00
return (__m512i) _mm512_set1_epi64((long long) __A);
[Clang][BuiltIn][AVX512] Adding intrinsics without mask for VBROADCAST and VPBROADCAST instruction set . Differential Revision: http://reviews.llvm.org/D19196 llvm-svn: 267696
2016-04-27 19:43:14 +08:00
}
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_broadcastmw_epi32 (__mmask16 __A)
{
lowering broadcastm Change-Id: I0661abea3e3742860e0a03ff9e4fcdc367eff7db llvm-svn: 317456
2017-11-06 15:04:12 +08:00
return (__m512i) _mm512_set1_epi32((int) __A);
[Clang][BuiltIn][AVX512] Adding intrinsics without mask for VBROADCAST and VPBROADCAST instruction set . Differential Revision: http://reviews.llvm.org/D19196 llvm-svn: 267696
2016-04-27 19:43:14 +08:00
}
Headers: Switch some headers to LF line endings for consistency. llvm-svn: 250388
2015-10-15 18:33:27 +08:00
#undef __DEFAULT_FN_ATTRS
#endif