maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/Transforms/VectorCombine/Hexagon/load.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

18 lines
727 B
LLVM
Raw Normal View History

[VectorCombine] add test for Hexagon that would crash; NFC This test verifies the code change from: rGb0b95dab1ce2 (although that would not be true if PR47128 is fixed)
2020-08-12 20:36:02 +08:00
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
[NewPM][test] Use -passes syntax in VectorCombine lit tests The legacy PM is deprecated, so use the new PM syntax in lit tests running the vector-combine pass.
2021-10-20 20:47:49 +08:00
; RUN: opt < %s -passes=vector-combine -S -mtriple=hexagon-- | FileCheck %s --check-prefixes=CHECK
[VectorCombine] add test for Hexagon that would crash; NFC This test verifies the code change from: rGb0b95dab1ce2 (although that would not be true if PR47128 is fixed)
2020-08-12 20:36:02 +08:00
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
; This would crash because TTI returns "0" for vector length.
define <4 x float> @load_f32_insert_v4f32(float* align 16 dereferenceable(16) %p) {
; CHECK-LABEL: @load_f32_insert_v4f32(
; CHECK-NEXT: [[S:%.*]] = load float, float* [[P:%.*]], align 4
; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> undef, float [[S]], i32 0
; CHECK-NEXT: ret <4 x float> [[R]]
;
%s = load float, float* %p, align 4
%r = insertelement <4 x float> undef, float %s, i32 0
ret <4 x float> %r
}