2010-12-05 07:57:24 +08:00
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//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
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2005-07-12 09:41:54 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-07-12 09:41:54 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2011-07-02 05:01:15 +08:00
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// This file implements the X86 specific subclass of TargetSubtargetInfo.
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2005-07-12 09:41:54 +08:00
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//
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//===----------------------------------------------------------------------===//
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#include "X86Subtarget.h"
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2009-07-10 15:20:05 +08:00
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#include "X86InstrInfo.h"
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2014-08-09 09:07:25 +08:00
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#include "X86TargetMachine.h"
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2013-02-16 06:31:27 +08:00
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/GlobalValue.h"
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2014-05-22 07:51:57 +08:00
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#include "llvm/Support/CommandLine.h"
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2009-01-03 12:04:46 +08:00
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#include "llvm/Support/Debug.h"
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2011-09-08 00:10:57 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2010-11-30 02:16:10 +08:00
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#include "llvm/Support/Host.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Support/raw_ostream.h"
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2006-12-23 06:29:05 +08:00
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#include "llvm/Target/TargetMachine.h"
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2011-09-08 00:10:57 +08:00
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#include "llvm/Target/TargetOptions.h"
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2011-07-02 04:45:01 +08:00
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2009-04-26 02:27:23 +08:00
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#if defined(_MSC_VER)
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2009-08-03 08:11:34 +08:00
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#include <intrin.h>
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2009-04-26 02:27:23 +08:00
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#endif
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2014-04-22 10:41:26 +08:00
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using namespace llvm;
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#define DEBUG_TYPE "subtarget"
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2014-04-22 10:03:14 +08:00
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "X86GenSubtargetInfo.inc"
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2014-05-22 07:40:26 +08:00
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// Temporary option to control early if-conversion for x86 while adding machine
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// models.
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static cl::opt<bool>
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X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
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cl::desc("Enable early if-conversion on X86"));
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2015-08-14 23:11:42 +08:00
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/// Classify a blockaddress reference for the current subtarget according to how
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/// we should reference it in a non-pcrel context.
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2013-04-03 07:06:40 +08:00
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unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
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2009-11-21 07:18:13 +08:00
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if (isPICStyleGOT()) // 32-bit ELF targets.
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return X86II::MO_GOTOFF;
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2012-08-02 02:39:17 +08:00
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2009-11-21 07:18:13 +08:00
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if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
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return X86II::MO_PIC_BASE_OFFSET;
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2012-08-02 02:39:17 +08:00
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2009-11-21 07:18:13 +08:00
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// Direct static reference to label.
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return X86II::MO_NO_FLAG;
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}
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2015-08-14 23:11:42 +08:00
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/// Classify a global variable reference for the current subtarget according to
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/// how we should reference it in a non-pcrel context.
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2009-07-10 15:20:05 +08:00
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unsigned char X86Subtarget::
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ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
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// DLLImport only exists on windows, it is implemented as a load from a
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// DLLIMPORT stub.
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2014-01-14 23:22:47 +08:00
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if (GV->hasDLLImportStorageClass())
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2009-07-10 15:20:05 +08:00
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return X86II::MO_DLLIMPORT;
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2015-07-06 04:52:35 +08:00
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bool isDef = GV->isStrongDefinitionForLinker();
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2009-07-17 06:53:10 +08:00
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2009-07-10 15:20:05 +08:00
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// X86-64 in PIC mode.
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if (isPICStyleRIPRel()) {
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// Large model never uses stubs.
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if (TM.getCodeModel() == CodeModel::Large)
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return X86II::MO_NO_FLAG;
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2012-08-02 02:39:17 +08:00
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2009-07-11 05:01:59 +08:00
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if (isTargetDarwin()) {
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// If symbol visibility is hidden, the extra load is not needed if
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// target is x86-64 or the symbol is definitely defined in the current
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// translation unit.
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2015-07-06 04:52:35 +08:00
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if (GV->hasDefaultVisibility() && !isDef)
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2009-07-11 05:01:59 +08:00
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return X86II::MO_GOTPCREL;
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2010-08-22 01:21:11 +08:00
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} else if (!isTargetWin64()) {
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2009-07-11 05:01:59 +08:00
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assert(isTargetELF() && "Unknown rip-relative target");
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2009-07-10 15:20:05 +08:00
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2009-07-11 05:01:59 +08:00
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// Extra load is needed for all externally visible.
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if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
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return X86II::MO_GOTPCREL;
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}
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2009-07-10 15:20:05 +08:00
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return X86II::MO_NO_FLAG;
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}
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2012-08-02 02:39:17 +08:00
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2009-07-10 15:20:05 +08:00
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if (isPICStyleGOT()) { // 32-bit ELF targets.
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return X86II::MO_GOTOFF;
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return X86II::MO_GOT;
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}
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2012-08-02 02:39:17 +08:00
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2009-07-11 05:00:45 +08:00
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if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
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2009-07-11 04:53:38 +08:00
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// Determine whether we have a stub reference and/or whether the reference
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// is relative to the PIC base or not.
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2012-08-02 02:39:17 +08:00
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2009-07-10 15:20:05 +08:00
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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2015-07-06 04:52:35 +08:00
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if (isDef)
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2009-07-11 04:53:38 +08:00
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return X86II::MO_PIC_BASE_OFFSET;
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2009-07-10 15:20:05 +08:00
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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2009-07-11 04:53:38 +08:00
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
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2012-08-02 02:39:17 +08:00
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2009-07-11 04:53:38 +08:00
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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2015-07-06 04:52:35 +08:00
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if (GV->isDeclarationForLinker() || GV->hasCommonLinkage()) {
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2009-07-11 04:53:38 +08:00
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// Hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
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2009-07-10 15:20:05 +08:00
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}
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2012-08-02 02:39:17 +08:00
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2009-07-11 04:53:38 +08:00
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// Otherwise, no stub.
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return X86II::MO_PIC_BASE_OFFSET;
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}
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2012-08-02 02:39:17 +08:00
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2009-07-11 05:00:45 +08:00
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if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
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2009-07-11 04:53:38 +08:00
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// Determine whether we have a stub reference.
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2012-08-02 02:39:17 +08:00
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2009-07-11 04:53:38 +08:00
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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2015-07-06 04:52:35 +08:00
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if (isDef)
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2009-07-11 04:53:38 +08:00
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return X86II::MO_NO_FLAG;
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2012-08-02 02:39:17 +08:00
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2009-07-11 04:53:38 +08:00
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY;
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2009-09-03 15:04:02 +08:00
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2009-07-10 15:20:05 +08:00
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// Otherwise, no stub.
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2009-07-11 04:53:38 +08:00
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return X86II::MO_NO_FLAG;
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2009-07-10 15:20:05 +08:00
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}
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2012-08-02 02:39:17 +08:00
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2009-07-10 15:20:05 +08:00
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// Direct static reference to global.
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return X86II::MO_NO_FLAG;
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}
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2006-12-01 06:42:55 +08:00
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2015-08-14 23:11:42 +08:00
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/// This function returns the name of a function which has an interface like
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/// the non-standard bzero function, if such a function exists on the
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/// current subtarget and it is considered preferable over memset with zero
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2008-10-01 05:22:07 +08:00
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/// passed as the second argument. Otherwise it returns null.
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2008-10-01 06:05:33 +08:00
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const char *X86Subtarget::getBZeroEntry() const {
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2008-04-02 04:38:36 +08:00
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// Darwin 10 has a __bzero entry point for this purpose.
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2011-04-20 08:14:25 +08:00
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if (getTargetTriple().isMacOSX() &&
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!getTargetTriple().isMacOSXVersionLT(10, 6))
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2008-10-01 06:05:33 +08:00
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return "__bzero";
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2008-04-02 04:38:36 +08:00
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2014-04-25 13:30:21 +08:00
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return nullptr;
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2008-04-02 04:38:36 +08:00
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}
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2013-01-29 10:32:37 +08:00
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bool X86Subtarget::hasSinCos() const {
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return getTargetTriple().isMacOSX() &&
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2013-01-31 06:56:35 +08:00
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!getTargetTriple().isMacOSXVersionLT(10, 9) &&
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is64Bit();
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2013-01-29 10:32:37 +08:00
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}
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2015-08-14 23:11:42 +08:00
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/// Return true if the subtarget allows calls to immediate address.
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2009-05-20 12:53:57 +08:00
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bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
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2014-03-29 05:40:47 +08:00
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// FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
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// but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
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// the following check for Win32 should be removed.
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if (In64BitMode || isTargetWin32())
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2009-05-20 12:53:57 +08:00
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return false;
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return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
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}
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2014-09-04 04:36:31 +08:00
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void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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2013-02-27 13:56:20 +08:00
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std::string CPUName = CPU;
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2014-04-12 09:34:29 +08:00
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if (CPUName.empty())
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CPUName = "generic";
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2011-07-09 07:43:01 +08:00
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2014-04-12 09:34:29 +08:00
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// Make sure 64-bit features are available in 64-bit mode. (But make sure
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// SSE2 can be turned off explicitly.)
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std::string FullFS = FS;
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if (In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+64bit,+sse2," + FullFS;
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else
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FullFS = "+64bit,+sse2";
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2006-09-08 14:48:29 +08:00
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}
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2011-07-11 11:57:24 +08:00
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2015-12-05 07:00:33 +08:00
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// LAHF/SAHF are always supported in non-64-bit mode.
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if (!In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+sahf," + FullFS;
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else
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FullFS = "+sahf";
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}
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2015-07-11 06:33:01 +08:00
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// Parse features string and set the CPU.
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2014-04-12 09:34:29 +08:00
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ParseSubtargetFeatures(CPUName, FullFS);
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2015-08-26 00:29:21 +08:00
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// All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
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// 16-bytes and under that are reasonably fast. These features were
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// introduced with Intel's Nehalem/Silvermont and AMD's Family10h
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// micro-architectures respectively.
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if (hasSSE42() || hasSSE4A())
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2015-09-02 04:51:51 +08:00
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IsUAMem16Slow = false;
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2015-08-26 00:29:21 +08:00
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2012-08-07 08:25:30 +08:00
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InstrItins = getInstrItineraryForCPU(CPUName);
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2012-02-02 07:20:51 +08:00
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2011-07-11 11:57:24 +08:00
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// It's important to keep the MCSubtargetInfo feature bits in sync with
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// target data structure which is shared with MC code emitter, etc.
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if (In64BitMode)
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ToggleFeature(X86::Mode64Bit);
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2014-01-06 12:55:54 +08:00
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else if (In32BitMode)
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ToggleFeature(X86::Mode32Bit);
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else if (In16BitMode)
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ToggleFeature(X86::Mode16Bit);
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else
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llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
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2011-07-11 11:57:24 +08:00
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2010-01-05 09:29:13 +08:00
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DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
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2009-08-03 08:11:34 +08:00
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<< ", 3DNowLevel " << X863DNowLevel
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<< ", 64bit " << HasX86_64 << "\n");
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2011-07-08 05:06:52 +08:00
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assert((!In64BitMode || HasX86_64) &&
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2009-02-03 08:04:43 +08:00
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"64-bit code requested on a subtarget that doesn't support it!");
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2006-09-08 14:48:29 +08:00
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2012-11-10 04:10:44 +08:00
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// Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
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2011-02-23 01:30:05 +08:00
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// 32 and 64 bit) and for all 64-bit targets.
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2011-06-24 01:54:54 +08:00
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if (StackAlignOverride)
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stackAlignment = StackAlignOverride;
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2012-11-10 04:10:44 +08:00
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else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
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In64BitMode)
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2005-07-12 09:41:54 +08:00
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stackAlignment = 16;
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2010-05-28 02:43:40 +08:00
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}
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2012-02-02 07:20:51 +08:00
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2013-02-16 09:36:26 +08:00
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void X86Subtarget::initializeEnvironment() {
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Move the MMX subtarget feature out of the SSE set of features and into
its own variable.
This is needed so that we can explicitly turn off MMX without turning
off SSE and also so that we can diagnose feature set incompatibilities
that involve MMX without SSE.
Rationale:
// sse3
__m128d test_mm_addsub_pd(__m128d A, __m128d B) {
return _mm_addsub_pd(A, B);
}
// mmx
void shift(__m64 a, __m64 b, int c) {
_mm_slli_pi16(a, c);
_mm_slli_pi32(a, c);
_mm_slli_si64(a, c);
_mm_srli_pi16(a, c);
_mm_srli_pi32(a, c);
_mm_srli_si64(a, c);
_mm_srai_pi16(a, c);
_mm_srai_pi32(a, c);
}
clang -msse3 -mno-mmx file.c -c
For this code we should be able to explicitly turn off MMX
without affecting the compilation of the SSE3 function and then
diagnose and error on compiling the MMX function.
This matches the existing gcc behavior and follows the spirit of
the SSE/MMX separation in llvm where we can (and do) turn off
MMX code generation except in the presence of intrinsics.
Updated a couple of tests, but primarily tested with a couple of tests
for turning on only mmx and only sse.
This is paired with a patch to clang to take advantage of this behavior.
llvm-svn: 249731
2015-10-09 04:10:06 +08:00
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X86SSELevel = NoSSE;
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2013-02-16 09:36:26 +08:00
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X863DNowLevel = NoThreeDNow;
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HasCMov = false;
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HasX86_64 = false;
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HasPOPCNT = false;
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HasSSE4A = false;
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HasAES = false;
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2015-10-16 14:03:09 +08:00
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HasFXSR = false;
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2015-10-12 19:47:46 +08:00
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HasXSAVE = false;
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HasXSAVEOPT = false;
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HasXSAVEC = false;
|
|
|
|
HasXSAVES = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
HasPCLMUL = false;
|
|
|
|
HasFMA = false;
|
|
|
|
HasFMA4 = false;
|
|
|
|
HasXOP = false;
|
2013-09-25 02:21:52 +08:00
|
|
|
HasTBM = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
HasMOVBE = false;
|
|
|
|
HasRDRAND = false;
|
|
|
|
HasF16C = false;
|
|
|
|
HasFSGSBase = false;
|
|
|
|
HasLZCNT = false;
|
|
|
|
HasBMI = false;
|
|
|
|
HasBMI2 = false;
|
2016-01-17 21:42:12 +08:00
|
|
|
HasVBMI = false;
|
2016-01-24 18:41:28 +08:00
|
|
|
HasIFMA = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
HasRTM = false;
|
2013-03-27 06:46:02 +08:00
|
|
|
HasHLE = false;
|
2013-07-28 16:28:38 +08:00
|
|
|
HasERI = false;
|
|
|
|
HasCDI = false;
|
2013-08-20 13:23:59 +08:00
|
|
|
HasPFI = false;
|
2014-07-21 22:54:21 +08:00
|
|
|
HasDQI = false;
|
|
|
|
HasBWI = false;
|
|
|
|
HasVLX = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
HasADX = false;
|
2015-12-15 21:35:29 +08:00
|
|
|
HasPKU = false;
|
2013-09-12 23:51:31 +08:00
|
|
|
HasSHA = false;
|
2013-03-27 01:47:11 +08:00
|
|
|
HasPRFCHW = false;
|
2013-03-29 07:41:26 +08:00
|
|
|
HasRDSEED = false;
|
2015-12-05 07:00:33 +08:00
|
|
|
HasLAHFSAHF = false;
|
2015-06-03 18:30:57 +08:00
|
|
|
HasMPX = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
IsBTMemSlow = false;
|
SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction.
AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size.
It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel.
llvm-svn: 195383
2013-11-22 07:21:26 +08:00
|
|
|
IsSHLDSlow = false;
|
2015-09-02 04:51:51 +08:00
|
|
|
IsUAMem16Slow = false;
|
2014-11-22 01:40:04 +08:00
|
|
|
IsUAMem32Slow = false;
|
2015-02-04 01:13:04 +08:00
|
|
|
HasSSEUnalignedMem = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
HasCmpxchg16b = false;
|
|
|
|
UseLeaForSP = false;
|
2016-02-13 07:37:57 +08:00
|
|
|
HasFastPartialYMMWrite = false;
|
2014-11-21 19:19:34 +08:00
|
|
|
HasSlowDivide32 = false;
|
|
|
|
HasSlowDivide64 = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
PadShortFunctions = false;
|
2013-03-28 03:14:02 +08:00
|
|
|
CallRegIndirect = false;
|
2013-04-26 04:29:37 +08:00
|
|
|
LEAUsesAG = false;
|
2014-05-20 16:55:50 +08:00
|
|
|
SlowLEA = false;
|
2014-06-09 19:40:41 +08:00
|
|
|
SlowIncDec = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
stackAlignment = 4;
|
|
|
|
// FIXME: this is a known good value for Yonah. How about others?
|
|
|
|
MaxInlineSizeThreshold = 128;
|
2015-05-12 09:26:05 +08:00
|
|
|
UseSoftFloat = false;
|
2013-02-16 09:36:26 +08:00
|
|
|
}
|
|
|
|
|
2014-06-11 08:25:19 +08:00
|
|
|
X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
|
|
|
|
StringRef FS) {
|
|
|
|
initializeEnvironment();
|
2014-09-04 04:36:31 +08:00
|
|
|
initSubtargetFeatures(CPU, FS);
|
2014-06-11 08:25:19 +08:00
|
|
|
return *this;
|
|
|
|
}
|
|
|
|
|
2015-06-10 20:11:26 +08:00
|
|
|
X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU,
|
2014-10-02 04:38:22 +08:00
|
|
|
const std::string &FS, const X86TargetMachine &TM,
|
2014-06-10 01:08:19 +08:00
|
|
|
unsigned StackAlignOverride)
|
2015-09-16 00:17:27 +08:00
|
|
|
: X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
|
2014-05-08 05:05:47 +08:00
|
|
|
PICStyle(PICStyles::None), TargetTriple(TT),
|
|
|
|
StackAlignOverride(StackAlignOverride),
|
|
|
|
In64BitMode(TargetTriple.getArch() == Triple::x86_64),
|
|
|
|
In32BitMode(TargetTriple.getArch() == Triple::x86 &&
|
|
|
|
TargetTriple.getEnvironment() != Triple::CODE16),
|
|
|
|
In16BitMode(TargetTriple.getArch() == Triple::x86 &&
|
2014-06-10 01:08:19 +08:00
|
|
|
TargetTriple.getEnvironment() == Triple::CODE16),
|
2015-07-09 10:10:08 +08:00
|
|
|
TSInfo(), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
|
|
|
|
TLInfo(TM, *this), FrameLowering(*this, getStackAlignment()) {
|
2014-08-09 09:07:25 +08:00
|
|
|
// Determine the PICStyle based on the target selected.
|
|
|
|
if (TM.getRelocationModel() == Reloc::Static) {
|
|
|
|
// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
|
|
|
|
setPICStyle(PICStyles::None);
|
|
|
|
} else if (is64Bit()) {
|
|
|
|
// PIC in 64 bit mode is always rip-rel.
|
|
|
|
setPICStyle(PICStyles::RIPRel);
|
|
|
|
} else if (isTargetCOFF()) {
|
|
|
|
setPICStyle(PICStyles::None);
|
|
|
|
} else if (isTargetDarwin()) {
|
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
|
|
setPICStyle(PICStyles::StubPIC);
|
|
|
|
else {
|
|
|
|
assert(TM.getRelocationModel() == Reloc::DynamicNoPIC);
|
|
|
|
setPICStyle(PICStyles::StubDynamicNoPIC);
|
|
|
|
}
|
|
|
|
} else if (isTargetELF()) {
|
|
|
|
setPICStyle(PICStyles::GOT);
|
|
|
|
}
|
|
|
|
}
|
2013-02-16 06:31:27 +08:00
|
|
|
|
2014-07-16 06:39:58 +08:00
|
|
|
bool X86Subtarget::enableEarlyIfConversion() const {
|
2014-05-22 07:51:57 +08:00
|
|
|
return hasCMov() && X86EarlyIfConv;
|
2014-05-22 07:40:26 +08:00
|
|
|
}
|
2014-07-16 06:39:58 +08:00
|
|
|
|