2017-06-17 01:32:43 +08:00
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//===- X86.cpp ------------------------------------------------------------===//
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//
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// The LLVM Linker
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "Symbols.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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[lld] unified COFF and ELF error handling on new Common/ErrorHandler
Summary:
The COFF linker and the ELF linker have long had similar but separate
Error.h and Error.cpp files to implement error handling. This change
introduces new error handling code in Common/ErrorHandler.h, changes the
COFF and ELF linkers to use it, and removes the old, separate
implementations.
Reviewers: ruiu
Reviewed By: ruiu
Subscribers: smeenai, jyknight, emaste, sdardis, nemanjai, nhaehnle, mgorny, javed.absar, kbarton, fedor.sergeev, llvm-commits
Differential Revision: https://reviews.llvm.org/D39259
llvm-svn: 316624
2017-10-26 06:28:38 +08:00
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#include "lld/Common/ErrorHandler.h"
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2017-06-17 01:32:43 +08:00
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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namespace {
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Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
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class X86 : public TargetInfo {
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2017-06-17 01:32:43 +08:00
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public:
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X86();
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2017-11-04 05:21:47 +08:00
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RelExpr getRelExpr(RelType Type, const Symbol &S,
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2017-06-17 01:32:43 +08:00
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const uint8_t *Loc) const override;
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2017-10-12 06:49:24 +08:00
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int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
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2017-06-17 01:32:43 +08:00
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void writeGotPltHeader(uint8_t *Buf) const override;
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2017-10-12 06:49:24 +08:00
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RelType getDynRel(RelType Type) const override;
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2017-11-04 05:21:47 +08:00
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void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
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void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override;
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2017-06-17 01:32:43 +08:00
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void writePltHeader(uint8_t *Buf) const override;
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void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
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int32_t Index, unsigned RelOff) const override;
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2017-10-12 06:49:24 +08:00
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void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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2017-06-17 01:32:43 +08:00
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2017-10-12 06:49:24 +08:00
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RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
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2017-06-17 01:32:43 +08:00
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RelExpr Expr) const override;
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2017-10-12 06:49:24 +08:00
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void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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2017-06-17 01:32:43 +08:00
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};
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} // namespace
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X86::X86() {
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CopyRel = R_386_COPY;
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GotRel = R_386_GLOB_DAT;
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PltRel = R_386_JUMP_SLOT;
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IRelativeRel = R_386_IRELATIVE;
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RelativeRel = R_386_RELATIVE;
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TlsGotRel = R_386_TLS_TPOFF;
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TlsModuleIndexRel = R_386_TLS_DTPMOD32;
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TlsOffsetRel = R_386_TLS_DTPOFF32;
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GotEntrySize = 4;
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GotPltEntrySize = 4;
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PltEntrySize = 16;
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PltHeaderSize = 16;
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TlsGdRelaxSkip = 2;
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2017-06-27 03:45:53 +08:00
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TrapInstr = 0xcccccccc; // 0xcc = INT3
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2017-06-17 01:32:43 +08:00
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}
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2017-10-12 11:14:06 +08:00
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static bool hasBaseReg(uint8_t ModRM) { return (ModRM & 0xc7) != 0x5; }
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2017-11-04 05:21:47 +08:00
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RelExpr X86::getRelExpr(RelType Type, const Symbol &S,
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2017-10-12 11:14:06 +08:00
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const uint8_t *Loc) const {
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2017-06-17 01:32:43 +08:00
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switch (Type) {
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case R_386_8:
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case R_386_16:
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case R_386_32:
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case R_386_TLS_LDO_32:
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return R_ABS;
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case R_386_TLS_GD:
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return R_TLSGD;
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case R_386_TLS_LDM:
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return R_TLSLD;
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case R_386_PLT32:
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return R_PLT_PC;
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case R_386_PC8:
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case R_386_PC16:
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case R_386_PC32:
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return R_PC;
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case R_386_GOTPC:
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return R_GOTONLY_PC_FROM_END;
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case R_386_TLS_IE:
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return R_GOT;
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case R_386_GOT32:
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case R_386_GOT32X:
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2017-10-12 10:09:11 +08:00
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// These relocations are arguably mis-designed because their calculations
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// depend on the instructions they are applied to. This is bad because we
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// usually don't care about whether the target section contains valid
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// machine instructions or not. But this is part of the documented ABI, so
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// we had to implement as the standard requires.
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2017-06-17 01:32:43 +08:00
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//
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2017-10-12 10:09:11 +08:00
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// x86 does not support PC-relative data access. Therefore, in order to
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// access GOT contents, a GOT address needs to be known at link-time
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// (which means non-PIC) or compilers have to emit code to get a GOT
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// address at runtime (which means code is position-independent but
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// compilers need to emit extra code for each GOT access.) This decision
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// is made at compile-time. In the latter case, compilers emit code to
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// load an GOT address to a register, which is usually %ebx.
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//
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// So, there are two ways to refer to symbol foo's GOT entry: foo@GOT or
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// foo@GOT(%reg).
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//
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// foo@GOT is not usable in PIC. If we are creating a PIC output and if we
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// find such relocation, we should report an error. foo@GOT is resolved to
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// an *absolute* address of foo's GOT entry, because both GOT address and
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// foo's offset are known. In other words, it's G + A.
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//
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// foo@GOT(%reg) needs to be resolved to a *relative* offset from a GOT to
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// foo's GOT entry in the table, because GOT address is not known but foo's
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// offset in the table is known. It's G + A - GOT.
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//
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// It's unfortunate that compilers emit the same relocation for these
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// different use cases. In order to distinguish them, we have to read a
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// machine instruction.
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//
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// The following code implements it. We assume that Loc[0] is the first
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// byte of a displacement or an immediate field of a valid machine
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// instruction. That means a ModRM byte is at Loc[-1]. By taking a look at
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// the byte, we can determine whether the instruction is register-relative
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// (i.e. it was generated for foo@GOT(%reg)) or absolute (i.e. foo@GOT).
|
2017-10-12 11:14:06 +08:00
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return hasBaseReg(Loc[-1]) ? R_GOT_FROM_END : R_GOT;
|
2017-06-17 01:32:43 +08:00
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case R_386_TLS_GOTIE:
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return R_GOT_FROM_END;
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case R_386_GOTOFF:
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return R_GOTREL_FROM_END;
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case R_386_TLS_LE:
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return R_TLS;
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case R_386_TLS_LE_32:
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return R_NEG_TLS;
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case R_386_NONE:
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return R_NONE;
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default:
|
2017-10-12 11:14:06 +08:00
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return R_INVALID;
|
2017-06-17 01:32:43 +08:00
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}
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}
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2017-10-12 06:49:24 +08:00
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RelExpr X86::adjustRelaxExpr(RelType Type, const uint8_t *Data,
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2017-06-17 01:32:43 +08:00
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RelExpr Expr) const {
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switch (Expr) {
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default:
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return Expr;
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case R_RELAX_TLS_GD_TO_IE:
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return R_RELAX_TLS_GD_TO_IE_END;
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case R_RELAX_TLS_GD_TO_LE:
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return R_RELAX_TLS_GD_TO_LE_NEG;
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}
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}
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void X86::writeGotPltHeader(uint8_t *Buf) const {
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write32le(Buf, InX::Dynamic->getVA());
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}
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2017-11-04 05:21:47 +08:00
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void X86::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
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2017-06-17 01:32:43 +08:00
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// Entries in .got.plt initially points back to the corresponding
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// PLT entries with a fixed offset to skip the first instruction.
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write32le(Buf, S.getPltVA() + 6);
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}
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2017-11-04 05:21:47 +08:00
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void X86::writeIgotPlt(uint8_t *Buf, const Symbol &S) const {
|
2017-06-17 01:32:43 +08:00
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// An x86 entry is the address of the ifunc resolver function.
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write32le(Buf, S.getVA());
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}
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2017-10-12 06:49:24 +08:00
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RelType X86::getDynRel(RelType Type) const {
|
2017-06-17 01:32:43 +08:00
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if (Type == R_386_TLS_LE)
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return R_386_TLS_TPOFF;
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if (Type == R_386_TLS_LE_32)
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return R_386_TLS_TPOFF32;
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return Type;
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}
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void X86::writePltHeader(uint8_t *Buf) const {
|
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if (Config->Pic) {
|
|
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const uint8_t V[] = {
|
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0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl GOTPLT+4(%ebx)
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0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *GOTPLT+8(%ebx)
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0x90, 0x90, 0x90, 0x90 // nop
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};
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memcpy(Buf, V, sizeof(V));
|
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uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
|
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uint32_t GotPlt = InX::GotPlt->getVA() - Ebx;
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write32le(Buf + 2, GotPlt + 4);
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write32le(Buf + 8, GotPlt + 8);
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return;
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}
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const uint8_t PltData[] = {
|
2017-12-27 14:54:18 +08:00
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0xff, 0x35, 0, 0, 0, 0, // pushl (GOTPLT+4)
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0xff, 0x25, 0, 0, 0, 0, // jmp *(GOTPLT+8)
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0x90, 0x90, 0x90, 0x90, // nop
|
2017-06-17 01:32:43 +08:00
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};
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memcpy(Buf, PltData, sizeof(PltData));
|
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uint32_t GotPlt = InX::GotPlt->getVA();
|
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write32le(Buf + 2, GotPlt + 4);
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write32le(Buf + 8, GotPlt + 8);
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}
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void X86::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
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uint64_t PltEntryAddr, int32_t Index,
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unsigned RelOff) const {
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const uint8_t Inst[] = {
|
2017-12-27 14:54:18 +08:00
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0xff, 0x00, 0, 0, 0, 0, // jmp *foo_in_GOT or jmp *foo@GOT(%ebx)
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0x68, 0, 0, 0, 0, // pushl $reloc_offset
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0xe9, 0, 0, 0, 0, // jmp .PLT0@PC
|
2017-06-17 01:32:43 +08:00
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};
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memcpy(Buf, Inst, sizeof(Inst));
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|
if (Config->Pic) {
|
|
|
|
// jmp *foo@GOT(%ebx)
|
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|
uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
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|
Buf[1] = 0xa3;
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|
write32le(Buf + 2, GotPltEntryAddr - Ebx);
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|
} else {
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|
|
|
// jmp *foo_in_GOT
|
|
|
|
Buf[1] = 0x25;
|
|
|
|
write32le(Buf + 2, GotPltEntryAddr);
|
|
|
|
}
|
|
|
|
|
|
|
|
write32le(Buf + 7, RelOff);
|
|
|
|
write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
int64_t X86::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
switch (Type) {
|
|
|
|
case R_386_8:
|
|
|
|
case R_386_PC8:
|
|
|
|
return SignExtend64<8>(*Buf);
|
|
|
|
case R_386_16:
|
|
|
|
case R_386_PC16:
|
|
|
|
return SignExtend64<16>(read16le(Buf));
|
|
|
|
case R_386_32:
|
|
|
|
case R_386_GOT32:
|
|
|
|
case R_386_GOT32X:
|
|
|
|
case R_386_GOTOFF:
|
|
|
|
case R_386_GOTPC:
|
|
|
|
case R_386_PC32:
|
|
|
|
case R_386_PLT32:
|
|
|
|
case R_386_TLS_LDO_32:
|
|
|
|
case R_386_TLS_LE:
|
|
|
|
return SignExtend64<32>(read32le(Buf));
|
2017-10-12 11:14:06 +08:00
|
|
|
default:
|
|
|
|
return 0;
|
2017-06-17 01:32:43 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void X86::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
switch (Type) {
|
|
|
|
case R_386_8:
|
2017-10-25 04:11:07 +08:00
|
|
|
// R_386_{PC,}{8,16} are not part of the i386 psABI, but they are
|
|
|
|
// being used for some 16-bit programs such as boot loaders, so
|
|
|
|
// we want to support them.
|
2017-06-17 01:32:43 +08:00
|
|
|
checkUInt<8>(Loc, Val, Type);
|
|
|
|
*Loc = Val;
|
|
|
|
break;
|
|
|
|
case R_386_PC8:
|
|
|
|
checkInt<8>(Loc, Val, Type);
|
|
|
|
*Loc = Val;
|
|
|
|
break;
|
|
|
|
case R_386_16:
|
|
|
|
checkUInt<16>(Loc, Val, Type);
|
|
|
|
write16le(Loc, Val);
|
|
|
|
break;
|
|
|
|
case R_386_PC16:
|
|
|
|
// R_386_PC16 is normally used with 16 bit code. In that situation
|
|
|
|
// the PC is 16 bits, just like the addend. This means that it can
|
|
|
|
// point from any 16 bit address to any other if the possibility
|
|
|
|
// of wrapping is included.
|
|
|
|
// The only restriction we have to check then is that the destination
|
|
|
|
// address fits in 16 bits. That is impossible to do here. The problem is
|
|
|
|
// that we are passed the final value, which already had the
|
|
|
|
// current location subtracted from it.
|
|
|
|
// We just check that Val fits in 17 bits. This misses some cases, but
|
|
|
|
// should have no false positives.
|
|
|
|
checkInt<17>(Loc, Val, Type);
|
|
|
|
write16le(Loc, Val);
|
|
|
|
break;
|
2017-10-12 11:14:06 +08:00
|
|
|
case R_386_32:
|
|
|
|
case R_386_GLOB_DAT:
|
|
|
|
case R_386_GOT32:
|
|
|
|
case R_386_GOT32X:
|
|
|
|
case R_386_GOTOFF:
|
|
|
|
case R_386_GOTPC:
|
|
|
|
case R_386_PC32:
|
|
|
|
case R_386_PLT32:
|
|
|
|
case R_386_RELATIVE:
|
2017-10-14 03:30:00 +08:00
|
|
|
case R_386_TLS_DTPMOD32:
|
|
|
|
case R_386_TLS_DTPOFF32:
|
2017-10-12 11:14:06 +08:00
|
|
|
case R_386_TLS_GD:
|
|
|
|
case R_386_TLS_GOTIE:
|
|
|
|
case R_386_TLS_IE:
|
|
|
|
case R_386_TLS_LDM:
|
|
|
|
case R_386_TLS_LDO_32:
|
|
|
|
case R_386_TLS_LE:
|
|
|
|
case R_386_TLS_LE_32:
|
2017-10-14 03:30:00 +08:00
|
|
|
case R_386_TLS_TPOFF:
|
|
|
|
case R_386_TLS_TPOFF32:
|
2017-06-17 01:32:43 +08:00
|
|
|
checkInt<32>(Loc, Val, Type);
|
|
|
|
write32le(Loc, Val);
|
2017-10-12 11:14:06 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
|
2017-06-17 01:32:43 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void X86::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
// Convert
|
|
|
|
// leal x@tlsgd(, %ebx, 1),
|
|
|
|
// call __tls_get_addr@plt
|
|
|
|
// to
|
|
|
|
// movl %gs:0,%eax
|
|
|
|
// subl $x@ntpoff,%eax
|
|
|
|
const uint8_t Inst[] = {
|
|
|
|
0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
|
2017-12-27 14:54:18 +08:00
|
|
|
0x81, 0xe8, 0, 0, 0, 0, // subl Val(%ebx), %eax
|
2017-06-17 01:32:43 +08:00
|
|
|
};
|
|
|
|
memcpy(Loc - 3, Inst, sizeof(Inst));
|
|
|
|
write32le(Loc + 5, Val);
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void X86::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
// Convert
|
|
|
|
// leal x@tlsgd(, %ebx, 1),
|
|
|
|
// call __tls_get_addr@plt
|
|
|
|
// to
|
|
|
|
// movl %gs:0, %eax
|
|
|
|
// addl x@gotntpoff(%ebx), %eax
|
|
|
|
const uint8_t Inst[] = {
|
|
|
|
0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
|
2017-12-27 14:54:18 +08:00
|
|
|
0x03, 0x83, 0, 0, 0, 0, // addl Val(%ebx), %eax
|
2017-06-17 01:32:43 +08:00
|
|
|
};
|
|
|
|
memcpy(Loc - 3, Inst, sizeof(Inst));
|
|
|
|
write32le(Loc + 5, Val);
|
|
|
|
}
|
|
|
|
|
|
|
|
// In some conditions, relocations can be optimized to avoid using GOT.
|
|
|
|
// This function does that for Initial Exec to Local Exec case.
|
2017-10-12 06:49:24 +08:00
|
|
|
void X86::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
// Ulrich's document section 6.2 says that @gotntpoff can
|
|
|
|
// be used with MOVL or ADDL instructions.
|
|
|
|
// @indntpoff is similar to @gotntpoff, but for use in
|
|
|
|
// position dependent code.
|
|
|
|
uint8_t Reg = (Loc[-1] >> 3) & 7;
|
|
|
|
|
|
|
|
if (Type == R_386_TLS_IE) {
|
|
|
|
if (Loc[-1] == 0xa1) {
|
|
|
|
// "movl foo@indntpoff,%eax" -> "movl $foo,%eax"
|
|
|
|
// This case is different from the generic case below because
|
|
|
|
// this is a 5 byte instruction while below is 6 bytes.
|
|
|
|
Loc[-1] = 0xb8;
|
|
|
|
} else if (Loc[-2] == 0x8b) {
|
|
|
|
// "movl foo@indntpoff,%reg" -> "movl $foo,%reg"
|
|
|
|
Loc[-2] = 0xc7;
|
|
|
|
Loc[-1] = 0xc0 | Reg;
|
|
|
|
} else {
|
|
|
|
// "addl foo@indntpoff,%reg" -> "addl $foo,%reg"
|
|
|
|
Loc[-2] = 0x81;
|
|
|
|
Loc[-1] = 0xc0 | Reg;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
assert(Type == R_386_TLS_GOTIE);
|
|
|
|
if (Loc[-2] == 0x8b) {
|
|
|
|
// "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg"
|
|
|
|
Loc[-2] = 0xc7;
|
|
|
|
Loc[-1] = 0xc0 | Reg;
|
|
|
|
} else {
|
|
|
|
// "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg"
|
|
|
|
Loc[-2] = 0x8d;
|
|
|
|
Loc[-1] = 0x80 | (Reg << 3) | Reg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
write32le(Loc, Val);
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void X86::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
2017-06-17 01:32:43 +08:00
|
|
|
if (Type == R_386_TLS_LDO_32) {
|
|
|
|
write32le(Loc, Val);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Convert
|
|
|
|
// leal foo(%reg),%eax
|
|
|
|
// call ___tls_get_addr
|
|
|
|
// to
|
|
|
|
// movl %gs:0,%eax
|
|
|
|
// nop
|
|
|
|
// leal 0(%esi,1),%esi
|
|
|
|
const uint8_t Inst[] = {
|
|
|
|
0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax
|
|
|
|
0x90, // nop
|
2017-12-27 14:54:18 +08:00
|
|
|
0x8d, 0x74, 0x26, 0x00, // leal 0(%esi,1),%esi
|
2017-06-17 01:32:43 +08:00
|
|
|
};
|
|
|
|
memcpy(Loc - 2, Inst, sizeof(Inst));
|
|
|
|
}
|
|
|
|
|
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
|
|
|
namespace {
|
|
|
|
class RetpolinePic : public X86 {
|
|
|
|
public:
|
|
|
|
RetpolinePic();
|
|
|
|
void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
|
|
|
|
void writePltHeader(uint8_t *Buf) const override;
|
|
|
|
void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
|
|
|
|
int32_t Index, unsigned RelOff) const override;
|
|
|
|
};
|
|
|
|
|
|
|
|
class RetpolineNoPic : public X86 {
|
|
|
|
public:
|
|
|
|
RetpolineNoPic();
|
|
|
|
void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
|
|
|
|
void writePltHeader(uint8_t *Buf) const override;
|
|
|
|
void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
|
|
|
|
int32_t Index, unsigned RelOff) const override;
|
|
|
|
};
|
|
|
|
} // namespace
|
|
|
|
|
|
|
|
RetpolinePic::RetpolinePic() {
|
|
|
|
PltHeaderSize = 48;
|
|
|
|
PltEntrySize = 32;
|
|
|
|
}
|
|
|
|
|
|
|
|
void RetpolinePic::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
|
|
|
|
write32le(Buf, S.getPltVA() + 17);
|
|
|
|
}
|
|
|
|
|
|
|
|
void RetpolinePic::writePltHeader(uint8_t *Buf) const {
|
|
|
|
const uint8_t Insn[] = {
|
|
|
|
0xff, 0xb3, 0, 0, 0, 0, // 0: pushl GOTPLT+4(%ebx)
|
|
|
|
0x50, // 6: pushl %eax
|
|
|
|
0x8b, 0x83, 0, 0, 0, 0, // 7: mov GOTPLT+8(%ebx), %eax
|
|
|
|
0xe8, 0x0e, 0x00, 0x00, 0x00, // d: call next
|
|
|
|
0xf3, 0x90, // 12: loop: pause
|
|
|
|
0x0f, 0xae, 0xe8, // 14: lfence
|
|
|
|
0xeb, 0xf9, // 17: jmp loop
|
|
|
|
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 19: int3; .align 16
|
|
|
|
0x89, 0x0c, 0x24, // 20: next: mov %ecx, (%esp)
|
|
|
|
0x8b, 0x4c, 0x24, 0x04, // 23: mov 0x4(%esp), %ecx
|
|
|
|
0x89, 0x44, 0x24, 0x04, // 27: mov %eax ,0x4(%esp)
|
|
|
|
0x89, 0xc8, // 2b: mov %ecx, %eax
|
|
|
|
0x59, // 2d: pop %ecx
|
|
|
|
0xc3, // 2e: ret
|
|
|
|
};
|
|
|
|
memcpy(Buf, Insn, sizeof(Insn));
|
|
|
|
|
|
|
|
uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
|
|
|
|
uint32_t GotPlt = InX::GotPlt->getVA() - Ebx;
|
|
|
|
write32le(Buf + 2, GotPlt + 4);
|
|
|
|
write32le(Buf + 9, GotPlt + 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
void RetpolinePic::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
|
|
|
|
uint64_t PltEntryAddr, int32_t Index,
|
|
|
|
unsigned RelOff) const {
|
|
|
|
const uint8_t Insn[] = {
|
|
|
|
0x50, // pushl %eax
|
|
|
|
0x8b, 0x83, 0, 0, 0, 0, // mov foo@GOT(%ebx), %eax
|
|
|
|
0xe8, 0, 0, 0, 0, // call plt+0x20
|
|
|
|
0xe9, 0, 0, 0, 0, // jmp plt+0x12
|
|
|
|
0x68, 0, 0, 0, 0, // pushl $reloc_offset
|
|
|
|
0xe9, 0, 0, 0, 0, // jmp plt+0
|
|
|
|
};
|
|
|
|
memcpy(Buf, Insn, sizeof(Insn));
|
|
|
|
|
|
|
|
uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
|
|
|
|
write32le(Buf + 3, GotPltEntryAddr - Ebx);
|
|
|
|
write32le(Buf + 8, -Index * PltEntrySize - PltHeaderSize - 12 + 32);
|
|
|
|
write32le(Buf + 13, -Index * PltEntrySize - PltHeaderSize - 17 + 18);
|
|
|
|
write32le(Buf + 18, RelOff);
|
|
|
|
write32le(Buf + 23, -Index * PltEntrySize - PltHeaderSize - 27);
|
|
|
|
}
|
|
|
|
|
|
|
|
RetpolineNoPic::RetpolineNoPic() {
|
2018-01-24 08:26:57 +08:00
|
|
|
PltHeaderSize = 48;
|
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
|
|
|
PltEntrySize = 32;
|
|
|
|
}
|
|
|
|
|
|
|
|
void RetpolineNoPic::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
|
|
|
|
write32le(Buf, S.getPltVA() + 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
void RetpolineNoPic::writePltHeader(uint8_t *Buf) const {
|
|
|
|
const uint8_t PltData[] = {
|
|
|
|
0xff, 0x35, 0, 0, 0, 0, // 0: pushl GOTPLT+4
|
|
|
|
0x50, // 6: pushl %eax
|
|
|
|
0xa1, 0, 0, 0, 0, // 7: mov GOTPLT+8, %eax
|
|
|
|
0xe8, 0x0f, 0x00, 0x00, 0x00, // c: call next
|
|
|
|
0xf3, 0x90, // 11: loop: pause
|
|
|
|
0x0f, 0xae, 0xe8, // 13: lfence
|
|
|
|
0xeb, 0xf9, // 16: jmp loop
|
|
|
|
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 18: int3
|
|
|
|
0xcc, 0xcc, 0xcc, // 1f: int3; .align 16
|
|
|
|
0x89, 0x0c, 0x24, // 20: next: mov %ecx, (%esp)
|
|
|
|
0x8b, 0x4c, 0x24, 0x04, // 23: mov 0x4(%esp), %ecx
|
|
|
|
0x89, 0x44, 0x24, 0x04, // 27: mov %eax ,0x4(%esp)
|
|
|
|
0x89, 0xc8, // 2b: mov %ecx, %eax
|
|
|
|
0x59, // 2d: pop %ecx
|
|
|
|
0xc3, // 2e: ret
|
|
|
|
};
|
|
|
|
memcpy(Buf, PltData, sizeof(PltData));
|
|
|
|
|
|
|
|
uint32_t GotPlt = InX::GotPlt->getVA();
|
|
|
|
write32le(Buf + 2, GotPlt + 4);
|
|
|
|
write32le(Buf + 8, GotPlt + 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
void RetpolineNoPic::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
|
|
|
|
uint64_t PltEntryAddr, int32_t Index,
|
|
|
|
unsigned RelOff) const {
|
|
|
|
const uint8_t Insn[] = {
|
|
|
|
0x50, // 0: pushl %eax
|
|
|
|
0xa1, 0, 0, 0, 0, // 1: mov foo_in_GOT, %eax
|
|
|
|
0xe8, 0, 0, 0, 0, // 6: call plt+0x20
|
|
|
|
0xe9, 0, 0, 0, 0, // b: jmp plt+0x11
|
|
|
|
0x68, 0, 0, 0, 0, // 10: pushl $reloc_offset
|
|
|
|
0xe9, 0, 0, 0, 0, // 15: jmp plt+0
|
|
|
|
};
|
|
|
|
memcpy(Buf, Insn, sizeof(Insn));
|
|
|
|
|
|
|
|
write32le(Buf + 2, GotPltEntryAddr);
|
|
|
|
write32le(Buf + 7, -Index * PltEntrySize - PltHeaderSize - 11 + 32);
|
|
|
|
write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16 + 17);
|
|
|
|
write32le(Buf + 17, RelOff);
|
|
|
|
write32le(Buf + 22, -Index * PltEntrySize - PltHeaderSize - 26);
|
|
|
|
}
|
|
|
|
|
2017-06-17 04:15:03 +08:00
|
|
|
TargetInfo *elf::getX86TargetInfo() {
|
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
|
|
|
if (Config->ZRetpolineplt) {
|
|
|
|
if (Config->Pic) {
|
|
|
|
static RetpolinePic T;
|
|
|
|
return &T;
|
|
|
|
}
|
|
|
|
static RetpolineNoPic T;
|
|
|
|
return &T;
|
|
|
|
}
|
|
|
|
|
|
|
|
static X86 T;
|
|
|
|
return &T;
|
2017-06-17 04:15:03 +08:00
|
|
|
}
|