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llvm-project/llvm/test/CodeGen/PowerPC/testComparesigesll.ll

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[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
[NFC][PowerPC] Consolidate testing of common linkage symbols Add a new file to test the code gen for common linkage symbol. Remove common linkage in some other testcases to avoid distraction. llvm-svn: 372426
2019-09-21 04:31:37 +08:00
@glob = local_unnamed_addr global i64 0, align 8
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
define signext i32 @test_igesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-BE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-LE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-BE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-LE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sge i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_igesll_z(i64 %a) {
; CHECK-LABEL: test_igesll_z:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[DAGCombiner] form 'not' ops ahead of shifts (PR39657) We fail to canonicalize IR this way (prefer 'not' ops to arbitrary 'xor'), but that would not matter without this patch because DAGCombiner was reversing that transform. I think we need this transform in the backend regardless of what happens in IR to catch cases where the shift-xor is formed late from GEP or other ops. https://rise4fun.com/Alive/NC1 Name: shl Pre: (-1 << C2) == C1 %shl = shl i8 %x, C2 %r = xor i8 %shl, C1 => %not = xor i8 %x, -1 %r = shl i8 %not, C2 Name: shr Pre: (-1 u>> C2) == C1 %sh = lshr i8 %x, C2 %r = xor i8 %sh, C1 => %not = xor i8 %x, -1 %r = lshr i8 %not, C2 https://bugs.llvm.org/show_bug.cgi?id=39657 llvm-svn: 347478
2018-11-23 03:24:10 +08:00
; CHECK-NEXT: not r3, r3
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesll_sext_z(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: not r3, r3
[DAGCombine] Prune unnused nodes. Summary: Nodes that have no uses are eventually pruned when they are selected from the worklist. Record nodes newly added to the worklist or DAG and perform pruning after every combine attempt. Reviewers: efriedma, RKSimon, craig.topper, spatel, jyknight Reviewed By: jyknight Subscribers: jdoerfert, jyknight, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58070 llvm-svn: 357283
2019-03-30 01:35:56 +08:00
; CHECK-BE-NEXT: sradi r3, r3, 63
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
[DAGCombine] Prune unnused nodes. Summary: Nodes that have no uses are eventually pruned when they are selected from the worklist. Record nodes newly added to the worklist or DAG and perform pruning after every combine attempt. Reviewers: efriedma, RKSimon, craig.topper, spatel, jyknight Reviewed By: jyknight Subscribers: jdoerfert, jyknight, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58070 llvm-svn: 357283
2019-03-30 01:35:56 +08:00
; CHECK-LE-NEXT: sradi r3, r3, 63
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sgt i64 %a, -1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_store:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-BE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-LE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext_store:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: sradi r6, r3, 63
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-NEXT: addis r5, r2, glob@toc@ha
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-NEXT: std r3, glob@toc@l(r5)
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-BE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-LE-NEXT: subc r3, r3, r4
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_igesll_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_z_store:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too. The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests. Note the asymmetry: we don't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction. Alive proofs: https://rise4fun.com/Alive/ysli Name: if pos, get -1 %c = icmp sgt i16 %x, -1 %r = sext i1 %c to i16 => %n = xor i16 %x, -1 %r = ashr i16 %n, 15 Name: if pos, get 1 %c = icmp sgt i16 %x, -1 %r = zext i1 %c to i16 => %n = xor i16 %x, -1 %r = lshr i16 %n, 15 Differential Revision: https://reviews.llvm.org/D48970 llvm-svn: 337130
2018-07-16 00:27:07 +08:00
; CHECK-NEXT: not r3, r3
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-NEXT: addis r4, r2, glob@toc@ha
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too. The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests. Note the asymmetry: we don't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction. Alive proofs: https://rise4fun.com/Alive/ysli Name: if pos, get -1 %c = icmp sgt i16 %x, -1 %r = sext i1 %c to i16 => %n = xor i16 %x, -1 %r = ashr i16 %n, 15 Name: if pos, get 1 %c = icmp sgt i16 %x, -1 %r = zext i1 %c to i16 => %n = xor i16 %x, -1 %r = lshr i16 %n, 15 Differential Revision: https://reviews.llvm.org/D48970 llvm-svn: 337130
2018-07-16 00:27:07 +08:00
; CHECK-NEXT: rldicl r3, r3, 1, 63
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-NEXT: std r3, glob@toc@l(r4)
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_igesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z_store:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: not r3, r3
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-NEXT: addis r4, r2, glob@toc@ha
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too. The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests. Note the asymmetry: we don't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction. Alive proofs: https://rise4fun.com/Alive/ysli Name: if pos, get -1 %c = icmp sgt i16 %x, -1 %r = sext i1 %c to i16 => %n = xor i16 %x, -1 %r = ashr i16 %n, 15 Name: if pos, get 1 %c = icmp sgt i16 %x, -1 %r = zext i1 %c to i16 => %n = xor i16 %x, -1 %r = lshr i16 %n, 15 Differential Revision: https://reviews.llvm.org/D48970 llvm-svn: 337130
2018-07-16 00:27:07 +08:00
; CHECK-NEXT: sradi r3, r3, 63
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-NEXT: std r3, glob@toc@l(r4)
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
; CHECK-NEXT: blr
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; CHECK-BE-LABEL: test_igesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: sradi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
2017-09-24 13:48:11 +08:00
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}