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llvm-project/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir

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[Power9] Allow gpr callee saved spills in prologue to vectors registers Currently in llvm, CalleeSavedInfo can only assign a callee saved register to stack frame index to be spilled in the prologue. We would like to enable spilling gprs to vector registers. This patch adds the capability to spill to other registers aside from just the stack. It also adds the changes for power9 to spill gprs to volatile vector registers when they are available. This happens only for leaf functions when using the option -ppc-enable-pe-vector-spills. Differential Revision: https://reviews.llvm.org/D39386 llvm-svn: 346512
2018-11-10 00:36:24 +08:00
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=prologepilog -ppc-enable-pe-vector-spills %s -o - | FileCheck %s
---
name: test1BB
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 16
[Power9] Allow gpr callee saved spills in prologue to vectors registers Currently in llvm, CalleeSavedInfo can only assign a callee saved register to stack frame index to be spilled in the prologue. We would like to enable spilling gprs to vector registers. This patch adds the capability to spill to other registers aside from just the stack. It also adds the changes for power9 to spill gprs to volatile vector registers when they are available. This happens only for leaf functions when using the option -ppc-enable-pe-vector-spills. Differential Revision: https://reviews.llvm.org/D39386 llvm-svn: 346512
2018-11-10 00:36:24 +08:00
tracksRegLiveness: true
liveins:
body: |
bb.0.entry:
$r14 = IMPLICIT_DEF
$r15 = IMPLICIT_DEF
$r16 = IMPLICIT_DEF
$f0 = IMPLICIT_DEF
$v20 = IMPLICIT_DEF
BLR8 implicit undef $lr8, implicit undef $rm
# CHECK-LABEL: name: test1BB
# CHECK: body: |
[PrologEpilogInserter][test] Improve SpilledToReg test D39386 made CalleeSavedInfo possible to spill a register to another register (vector register for POWER9) but did not actually test live-in.
2020-10-18 11:36:21 +08:00
# CHECK: liveins: $x14, $x15, $x16, $v20
[Power9] Allow gpr callee saved spills in prologue to vectors registers Currently in llvm, CalleeSavedInfo can only assign a callee saved register to stack frame index to be spilled in the prologue. We would like to enable spilling gprs to vector registers. This patch adds the capability to spill to other registers aside from just the stack. It also adds the changes for power9 to spill gprs to volatile vector registers when they are available. This happens only for leaf functions when using the option -ppc-enable-pe-vector-spills. Differential Revision: https://reviews.llvm.org/D39386 llvm-svn: 346512
2018-11-10 00:36:24 +08:00
# CHECK: $f1 = MTVSRD killed $x14
# CHECK-NEXT: $f2 = MTVSRD killed $x15
# CHECK-NEXT: $f3 = MTVSRD killed $x16
# CHECK: $x16 = MFVSRD killed $f3
# CHECK-NEXT: $x15 = MFVSRD killed $f2
# CHECK-NEXT: $x14 = MFVSRD killed $f1
...
---
name: test2BBs
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 16
[Power9] Allow gpr callee saved spills in prologue to vectors registers Currently in llvm, CalleeSavedInfo can only assign a callee saved register to stack frame index to be spilled in the prologue. We would like to enable spilling gprs to vector registers. This patch adds the capability to spill to other registers aside from just the stack. It also adds the changes for power9 to spill gprs to volatile vector registers when they are available. This happens only for leaf functions when using the option -ppc-enable-pe-vector-spills. Differential Revision: https://reviews.llvm.org/D39386 llvm-svn: 346512
2018-11-10 00:36:24 +08:00
tracksRegLiveness: true
liveins:
body: |
bb.0.entry:
successors: %bb.1, %bb.2
$cr0 = IMPLICIT_DEF
BCC 4, killed renamable $cr0, %bb.2
B %bb.1
bb.1:
$r14 = IMPLICIT_DEF
$r15 = IMPLICIT_DEF
$r16 = IMPLICIT_DEF
$r3 = IMPLICIT_DEF
B %bb.3
bb.2:
$r3 = IMPLICIT_DEF
bb.3:
BLR8 implicit undef $lr8, implicit undef $rm
[PrologEpilogInserter][test] Improve SpilledToReg test D39386 made CalleeSavedInfo possible to spill a register to another register (vector register for POWER9) but did not actually test live-in.
2020-10-18 11:36:21 +08:00
## The spilled-to registers have to be marked as live-in so that they will not be
## clobbered before restored in the epilogue.
[Power9] Allow gpr callee saved spills in prologue to vectors registers Currently in llvm, CalleeSavedInfo can only assign a callee saved register to stack frame index to be spilled in the prologue. We would like to enable spilling gprs to vector registers. This patch adds the capability to spill to other registers aside from just the stack. It also adds the changes for power9 to spill gprs to volatile vector registers when they are available. This happens only for leaf functions when using the option -ppc-enable-pe-vector-spills. Differential Revision: https://reviews.llvm.org/D39386 llvm-svn: 346512
2018-11-10 00:36:24 +08:00
# CHECK-LABEL: name: test2BB
# CHECK: body: |
[PrologEpilogInserter][test] Improve SpilledToReg test D39386 made CalleeSavedInfo possible to spill a register to another register (vector register for POWER9) but did not actually test live-in.
2020-10-18 11:36:21 +08:00
# CHECK: $f0 = MTVSRD killed $x14
# CHECK-NEXT: $f1 = MTVSRD killed $x15
# CHECK-NEXT: $f2 = MTVSRD killed $x16
# CHECK: bb.2:
# CHECK-NEXT: successors: %bb.3
# CHECK-NEXT: liveins: $f0, $f1, $f2
# CHECK: bb.3:
# CHECK-NEXT: liveins: $f0, $f1, $f2
# CHECK: $x16 = MFVSRD killed $f2
# CHECK-NEXT: $x15 = MFVSRD killed $f1
# CHECK-NEXT: $x14 = MFVSRD killed $f0
[Power9] Allow gpr callee saved spills in prologue to vectors registers Currently in llvm, CalleeSavedInfo can only assign a callee saved register to stack frame index to be spilled in the prologue. We would like to enable spilling gprs to vector registers. This patch adds the capability to spill to other registers aside from just the stack. It also adds the changes for power9 to spill gprs to volatile vector registers when they are available. This happens only for leaf functions when using the option -ppc-enable-pe-vector-spills. Differential Revision: https://reviews.llvm.org/D39386 llvm-svn: 346512
2018-11-10 00:36:24 +08:00
...