2017-08-07 22:58:04 +08:00
|
|
|
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
|
2017-07-07 04:57:05 +08:00
|
|
|
|
|
|
|
# GCN-LABEL: name: cluster_add_addc
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: S_NOP 0, implicit-def $vcc
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
|
|
|
# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %3, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: cluster_add_addc
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%2, %3 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
2018-02-01 06:04:26 +08:00
|
|
|
%6 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%7 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
S_NOP 0, implicit def $vcc
|
2019-03-19 03:35:44 +08:00
|
|
|
%4, %5 = V_ADDC_U32_e64 %6, %7, %3, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: interleave_add64s
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: dead %8:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
|
|
|
# GCN-NEXT: dead %12:vgpr_32, dead %13:sreg_64_xexec = V_ADDC_U32_e64 %4, %5, %9, 0, implicit $exec
|
|
|
|
# GCN-NEXT: dead %10:vgpr_32, %11:sreg_64_xexec = V_ADD_I32_e64 %2, %3, 0, implicit $exec
|
|
|
|
# GCN-NEXT: dead %14:vgpr_32, dead %15:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %11, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: interleave_add64s
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
|
|
|
- { id: 4, class: vgpr_32 }
|
|
|
|
- { id: 5, class: vgpr_32 }
|
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
- { id: 8, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 9, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 10, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 11, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 12, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 13, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 14, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 15, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%2 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%3 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%4 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%5 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%6 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%7 = V_MOV_B32_e32 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
|
2019-03-19 03:35:44 +08:00
|
|
|
%8, %9 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
|
|
|
%10, %11 = V_ADD_I32_e64 %2, %3, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
|
|
|
|
|
2019-03-19 03:35:44 +08:00
|
|
|
%12, %13 = V_ADDC_U32_e64 %4, %5, %9, 0, implicit $exec
|
|
|
|
%14, %15 = V_ADDC_U32_e64 %6, %7, %11, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: cluster_mov_addc
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: S_NOP 0, implicit-def $vcc
|
2017-10-25 02:04:54 +08:00
|
|
|
# GCN-NEXT: %2:sreg_64_xexec = S_MOV_B64 0
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN-NEXT: dead %3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 %0, %1, %2, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: cluster_mov_addc
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 2, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 3, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 4, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
%2 = S_MOV_B64 0
|
2018-02-01 06:04:26 +08:00
|
|
|
S_NOP 0, implicit def $vcc
|
2019-03-19 03:35:44 +08:00
|
|
|
%3, %4 = V_ADDC_U32_e64 %0, %1, %2, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: no_cluster_add_addc_diff_sgpr
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: dead %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN-NEXT: %6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
# GCN-NEXT: %7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
# GCN-NEXT: S_NOP 0, implicit-def $vcc
|
2017-10-25 02:04:54 +08:00
|
|
|
# GCN-NEXT: %8:sreg_64_xexec = S_MOV_B64 0
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN-NEXT: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %8, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: no_cluster_add_addc_diff_sgpr
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 8, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
%8 = S_MOV_B64 0
|
2019-03-19 03:35:44 +08:00
|
|
|
%2, %3 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
2018-02-01 06:04:26 +08:00
|
|
|
%6 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%7 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
S_NOP 0, implicit def $vcc
|
2019-03-19 03:35:44 +08:00
|
|
|
%4, %5 = V_ADDC_U32_e64 %6, %7, %8, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|
|
|
|
# GCN-LABEL: name: cluster_sub_subb
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: S_NOP 0, implicit-def $vcc
|
2019-03-19 03:35:44 +08:00
|
|
|
# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_SUB_I32_e64 %0, %1, 0, implicit $exec
|
|
|
|
# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_SUBB_U32_e64 %6, %7, %3, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: cluster_sub_subb
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
2019-03-19 03:35:44 +08:00
|
|
|
%2, %3 = V_SUB_I32_e64 %0, %1, 0, implicit $exec
|
2018-02-01 06:04:26 +08:00
|
|
|
%6 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%7 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
S_NOP 0, implicit def $vcc
|
2019-03-19 03:35:44 +08:00
|
|
|
%4, %5 = V_SUBB_U32_e64 %6, %7, %3, 0, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|
|
|
|
|
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
Summary:
There's a lot of test case churn but the overall effect is to increase
the number of back-to-back v_sub,v_subbrev pairs, which can execute with
no delay even on gfx10.
Reviewers: arsenm, rampitec, nhaehnle
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D75999
2020-03-12 01:01:24 +08:00
|
|
|
# GCN-LABEL: name: cluster_subrev_subbrev
|
|
|
|
# GCN: S_NOP 0, implicit-def $vcc
|
|
|
|
# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_SUBREV_I32_e64 %0, %1, 0, implicit $exec
|
|
|
|
# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_SUBBREV_U32_e64 %6, %7, %3, 0, implicit $exec
|
|
|
|
name: cluster_subrev_subbrev
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
|
|
|
- { id: 3, class: sreg_64_xexec }
|
|
|
|
- { id: 4, class: vgpr_32 }
|
|
|
|
- { id: 5, class: sreg_64_xexec }
|
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%2, %3 = V_SUBREV_I32_e64 %0, %1, 0, implicit $exec
|
|
|
|
%6 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%7 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
S_NOP 0, implicit def $vcc
|
|
|
|
%4, %5 = V_SUBBREV_U32_e64 %6, %7, %3, 0, implicit $exec
|
|
|
|
...
|
|
|
|
|
2017-07-07 04:57:05 +08:00
|
|
|
# GCN-LABEL: name: cluster_cmp_cndmask
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: S_NOP 0, implicit-def $vcc
|
|
|
|
# GCN-NEXT: %3:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN-NEXT: dead %4:vgpr_32 = V_CNDMASK_B32_e64 0, %0, 0, %1, %3, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: cluster_cmp_cndmask
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 3, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 4, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 5, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%3 = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
|
|
|
|
S_NOP 0, implicit def $vcc
|
2019-03-19 03:25:39 +08:00
|
|
|
%4 = V_CNDMASK_B32_e64 0, %0, 0, %1, %3, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: cluster_multi_use_cmp_cndmask
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 0, %2, 0, %1, %4, implicit $exec
|
|
|
|
# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 0, %1, 0, %3, %4, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: cluster_multi_use_cmp_cndmask
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 4, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 5, class: vgpr_32 }
|
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%2 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%3 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
|
|
|
|
%4 = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
|
|
|
|
S_NOP 0, implicit def $vcc
|
2019-03-19 03:25:39 +08:00
|
|
|
%5 = V_CNDMASK_B32_e64 0, %2, 0, %1, %4, implicit $exec
|
|
|
|
%6 = V_CNDMASK_B32_e64 0, %1, 0, %3, %4, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
# GCN-LABEL: name: cluster_multi_use_cmp_cndmask2
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 0, %2, 0, %1, %4, implicit $exec
|
2018-02-01 06:04:26 +08:00
|
|
|
# GCN-NEXT: %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 0, %1, 0, %3, %4, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
name: cluster_multi_use_cmp_cndmask2
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vgpr_32 }
|
|
|
|
- { id: 1, class: vgpr_32 }
|
|
|
|
- { id: 2, class: vgpr_32 }
|
|
|
|
- { id: 3, class: vgpr_32 }
|
AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.
Additionally, inline constants do not work. At least,
v_addc_u32_e64 v0, vcc, v0, v1, -1
which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.
The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine
s_mov_b64 s[0:1], exec
v_cndmask_b32_e64 v0, v1, v2, s[0:1]
into
v_mov_b32 v0, v3
but it's not particularly high priority.
Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*
llvm-svn: 314522
2017-09-29 23:37:31 +08:00
|
|
|
- { id: 4, class: sreg_64_xexec }
|
2017-07-07 04:57:05 +08:00
|
|
|
- { id: 5, class: vgpr_32 }
|
|
|
|
- { id: 6, class: vgpr_32 }
|
|
|
|
- { id: 7, class: vgpr_32 }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2018-02-01 06:04:26 +08:00
|
|
|
%0 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%1 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
%4 = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
|
|
|
|
%2 = V_MOV_B32_e32 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
%5 = V_CNDMASK_B32_e64 0, %2, 0, %1, %4, implicit $exec
|
2018-02-01 06:04:26 +08:00
|
|
|
%3 = V_MOV_B32_e32 0, implicit $exec
|
2019-03-19 03:25:39 +08:00
|
|
|
%6 = V_CNDMASK_B32_e64 0, %1, 0, %3, %4, implicit $exec
|
2017-07-07 04:57:05 +08:00
|
|
|
...
|