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llvm-project/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h

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stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
//===-- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax ----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARM MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef ARMINSTPRINTER_H
#define ARMINSTPRINTER_H
#include "llvm/MC/MCInstPrinter.h"
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
2011-09-08 01:24:38 +08:00
#include "llvm/MC/MCSubtargetInfo.h"
stub out a minimal ARMInstPrinter. llvm-svn: 84527
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namespace llvm {
We need to pass the TargetMachine object to the InstPrinter if we are printing the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
2011-03-21 12:13:46 +08:00
class MCOperand;
trailing whitespace llvm-svn: 114212
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stub out a minimal ARMInstPrinter. llvm-svn: 84527
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class ARMInstPrinter : public MCInstPrinter {
public:
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
2011-09-08 01:24:38 +08:00
ARMInstPrinter(const MCAsmInfo &MAI, const MCSubtargetInfo &STI);
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. llvm-svn: 139876
2011-09-16 07:38:46 +08:00
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. llvm-svn: 117609
2010-10-29 05:37:33 +08:00
virtual StringRef getOpcodeName(unsigned Opcode) const;
Don't hardcode the %reg format in the streamer. llvm-svn: 132451
2011-06-02 10:34:55 +08:00
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. llvm-svn: 117609
2010-10-29 05:37:33 +08:00
static const char *getInstructionName(unsigned Opcode);
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
// Autogenerated by tblgen.
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printInstruction(const MCInst *MI, raw_ostream &O);
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
static const char *getRegisterName(unsigned RegNo);
Remove the no longer used 'Modifier' optional operand to the ARM printOperand() asm printer helper functions. rdar://8425198 llvm-svn: 118140
2010-11-03 09:11:15 +08:00
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 07:38:37 +08:00
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Apply again changes to support ARM memory asm parsing. I removed all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
2011-04-01 07:26:08 +08:00
Thumb2 assembly parsing and encoding for TBB/TBH. llvm-svn: 140078
2011-09-20 06:21:13 +08:00
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Apply again changes to support ARM memory asm parsing. I removed all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
2011-04-01 07:26:08 +08:00
void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
2011-04-05 01:18:19 +08:00
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 07:50:40 +08:00
void printAM3PostIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O);
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,raw_ostream &O);
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
ARM use a dedicated printer for postidx_reg operands. llvm-svn: 136968
2011-08-05 23:48:21 +08:00
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
2011-08-05 02:24:14 +08:00
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
2011-04-05 01:18:19 +08:00
Remove the no longer used 'Modifier' optional operand to the ARM printOperand() asm printer helper functions. rdar://8425198 llvm-svn: 118140
2010-11-03 09:11:15 +08:00
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Add asm parsing support w/ testcases for strex/ldrex family of instructions llvm-svn: 128236
2011-03-25 05:04:58 +08:00
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero operands into their own PrintMethod, in order not to pollute the printOperand() impl with disassembly only Imm modifiers. llvm-svn: 98172
2010-03-11 02:59:38 +08:00
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
Cleaned up the for-disassembly-only entries in the arm instruction table so that the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
2010-08-13 04:46:17 +08:00
void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Rename sat_shift operand to shift_imm, in preparation for using it for other instructions besides saturate instructions. No functional changes. llvm-svn: 111168
2010-08-17 02:27:34 +08:00
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM PKH shift ammount operand printing tweaks. Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
2011-07-21 05:40:26 +08:00
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
More consistent thumb1 asm printing. llvm-svn: 89328
2009-11-19 14:57:41 +08:00
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM clean up the imm_sr operand class representation. Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
2011-08-18 05:51:27 +08:00
void printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
The tLDR et al instructions were emitting either a reg/reg or reg/imm instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
2010-12-14 11:36:38 +08:00
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O, unsigned Scale);
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
trailing whitespace llvm-svn: 114212
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change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
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void printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
imm12 operands aren't Thumb2 only, so rename the printer helper function. llvm-svn: 117291
2010-10-26 04:00:01 +08:00
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. llvm-svn: 139381
2011-09-10 02:37:27 +08:00
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
2010-10-14 05:00:04 +08:00
void printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 21:09:44 +08:00
void printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-14 05:46:02 +08:00
void printPImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printCImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM parsing and encoding for the <option> form of LDC/STC instructions. llvm-svn: 141786
2011-10-13 01:34:41 +08:00
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
2011-09-30 08:50:06 +08:00
void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Add instruction encoding for the Neon VMOV immediate instruction. This changes the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
2010-06-12 05:34:50 +08:00
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM assembly parsing and encoding for SSAT16 instruction. llvm-svn: 136006
2011-07-26 07:09:14 +08:00
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM cleanup of rot_imm encoding. Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
2011-07-27 05:28:43 +08:00
void printRotImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola. llvm-svn: 84553
2009-10-20 06:23:04 +08:00
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. llvm-svn: 140283
2011-09-22 07:44:46 +08:00
void printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM NEON assembly parsing and encoding for VDUP(scalar). llvm-svn: 141446
2011-10-08 07:56:00 +08:00
void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM VTBL (one register) assembly parsing and encoding. llvm-svn: 142441
2011-10-19 07:02:30 +08:00
void printVectorListOne(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM VLD parsing and encoding. Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
2011-10-22 02:54:25 +08:00
void printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Assembly parsing for 3-register variant of VLD1. llvm-svn: 142675
2011-10-22 04:02:19 +08:00
void printVectorListThree(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Assembly parsing for 4-register variant of VLD1. llvm-svn: 142682
2011-10-22 04:35:01 +08:00
void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
ARM parsing aliases for VLD1 single register all lanes. llvm-svn: 145464
2011-11-30 09:09:44 +08:00
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
ARM parsing for VLD1 two register all lanes, no writeback. llvm-svn: 145504
2011-12-01 02:21:25 +08:00
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
ARM NEON VST2 assembly parsing and encoding. Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
2011-12-15 03:35:22 +08:00
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
};
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
stub out a powerpc MCInstPrinter implementation. llvm-svn: 119059
2010-11-15 03:40:38 +08:00
} // end namespace llvm
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
#endif